int zd_rf_init_rf2959(struct zd_rf *rf)
{
struct zd_chip *chip = zd_rf_to_chip(rf);
if (zd_chip_is_zd1211b(chip)) {
dev_err(zd_chip_dev(chip),
"RF2959 is currently not supported for ZD1211B"
" devices\n");
return -ENODEV;
}
rf->init_hw = rf2959_init_hw;
rf->set_channel = rf2959_set_channel;
rf->switch_radio_on = rf2959_switch_radio_on;
rf->switch_radio_off = rf2959_switch_radio_off;
return 0;
}
int zd_rf_set_channel(struct zd_rf *rf, u8 channel)
{
int r;
ZD_ASSERT(mutex_is_locked(&zd_rf_to_chip(rf)->mutex));
if (channel < MIN_CHANNEL24)
return -EINVAL;
if (channel > MAX_CHANNEL24)
return -EINVAL;
dev_dbg_f(zd_chip_dev(zd_rf_to_chip(rf)), "channel: %d\n", channel);
r = rf->set_channel(rf, channel);
if (r >= 0)
rf->channel = channel;
return r;
}
static int zd1211b_al7230b_patch_6m(struct zd_rf *rf, u8 channel)
{
struct zd_chip *chip = zd_rf_to_chip(rf);
struct zd_ioreq16 ioreqs[] = {
{ CR128, 0x14 }, { CR129, 0x12 },
};
/* FIXME: Channel 11 is not the edge for all regulatory domains. */
if (channel == 1) {
ioreqs[0].value = 0x0e;
ioreqs[1].value = 0x10;
} else if (channel == 11) {
ioreqs[0].value = 0x10;
ioreqs[1].value = 0x10;
}
dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
}
int zd_rf_init_hw(struct zd_rf *rf, u8 type)
{
int r = 0;
int t;
struct zd_chip *chip = zd_rf_to_chip(rf);
ZD_ASSERT(mutex_is_locked(&chip->mutex));
switch (type) {
case RF2959_RF:
r = zd_rf_init_rf2959(rf);
break;
case AL2230_RF:
case AL2230S_RF:
r = zd_rf_init_al2230(rf);
break;
case AL7230B_RF:
r = zd_rf_init_al7230b(rf);
break;
case MAXIM_NEW_RF:
case UW2453_RF:
r = zd_rf_init_uw2453(rf);
break;
default:
dev_err(zd_chip_dev(chip),
"RF %s %#x is not supported\n", zd_rf_name(type), type);
rf->type = 0;
return -ENODEV;
}
if (r)
return r;
rf->type = type;
r = zd_chip_lock_phy_regs(chip);
if (r)
return r;
t = rf->init_hw(rf);
r = zd_chip_unlock_phy_regs(chip);
if (t)
r = t;
return r;
}
static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
const zd_addr_t *addr)
{
int r;
u32 parts[2];
r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
if (r) {
dev_dbg_f(zd_chip_dev(chip),
"error: couldn't read e2p macs. Error number %d\n", r);
return r;
}
mac_addr[0] = parts[0];
mac_addr[1] = parts[0] >> 8;
mac_addr[2] = parts[0] >> 16;
mac_addr[3] = parts[0] >> 24;
mac_addr[4] = parts[1];
mac_addr[5] = parts[1] >> 8;
return 0;
}
static int _zd_iowrite32v_async_locked(struct zd_chip *chip,
const struct zd_ioreq32 *ioreqs,
unsigned int count)
{
int i, j, r;
struct zd_ioreq16 ioreqs16[USB_MAX_IOWRITE32_COUNT * 2];
unsigned int count16;
/* Use stack for values and addresses. */
ZD_ASSERT(mutex_is_locked(&chip->mutex));
if (count == 0)
return 0;
if (count > USB_MAX_IOWRITE32_COUNT)
return -EINVAL;
count16 = 2 * count;
BUG_ON(count16 * sizeof(struct zd_ioreq16) > sizeof(ioreqs16));
for (i = 0; i < count; i++) {
j = 2*i;
/* We write the high word always first. */
ioreqs16[j].value = ioreqs[i].value >> 16;
ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
ioreqs16[j+1].value = ioreqs[i].value;
ioreqs16[j+1].addr = ioreqs[i].addr;
}
r = zd_usb_iowrite16v_async(&chip->usb, ioreqs16, count16);
#ifdef DEBUG
if (r) {
dev_dbg_f(zd_chip_dev(chip),
"error %d in zd_usb_write16v\n", r);
}
#endif /* DEBUG */
return r;
}
/* Read a variable number of 32-bit values. Parameter count is not allowed to
* exceed USB_MAX_IOREAD32_COUNT.
*/
int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
unsigned int count)
{
int r;
int i;
zd_addr_t a16[USB_MAX_IOREAD32_COUNT * 2];
u16 v16[USB_MAX_IOREAD32_COUNT * 2];
unsigned int count16;
if (count > USB_MAX_IOREAD32_COUNT)
return -EINVAL;
/* Use stack for values and addresses. */
count16 = 2 * count;
BUG_ON(count16 * sizeof(zd_addr_t) > sizeof(a16));
BUG_ON(count16 * sizeof(u16) > sizeof(v16));
for (i = 0; i < count; i++) {
int j = 2*i;
/* We read the high word always first. */
a16[j] = inc_addr(addr[i]);
a16[j+1] = addr[i];
}
r = zd_ioread16v_locked(chip, v16, a16, count16);
if (r) {
dev_dbg_f(zd_chip_dev(chip),
"error: %s. Error number %d\n", __func__, r);
return r;
}
for (i = 0; i < count; i++) {
int j = 2*i;
values[i] = (v16[j] << 16) | v16[j+1];
}
return 0;
}
int zd_rf_init_al2230(struct zd_rf *rf)
{
struct zd_chip *chip = zd_rf_to_chip(rf);
if (chip->al2230s_bit) {
dev_err(zd_chip_dev(chip), "AL2230S devices are not yet "
"supported by this driver.\n");
return -ENODEV;
}
rf->switch_radio_off = al2230_switch_radio_off;
if (chip->is_zd1211b) {
rf->init_hw = zd1211b_al2230_init_hw;
rf->set_channel = zd1211b_al2230_set_channel;
rf->switch_radio_on = zd1211b_al2230_switch_radio_on;
} else {
rf->init_hw = zd1211_al2230_init_hw;
rf->set_channel = zd1211_al2230_set_channel;
rf->switch_radio_on = zd1211_al2230_switch_radio_on;
}
rf->patch_6m_band_edge = 1;
return 0;
}
static int uw2453_init_hw(struct zd_rf *rf)
{
int i, r;
int found_config = -1;
u16 intr_status;
struct zd_chip *chip = zd_rf_to_chip(rf);
static const struct zd_ioreq16 ioreqs[] = {
{ CR10, 0x89 }, { CR15, 0x20 },
{ CR17, 0x28 }, /* 6112 no change */
{ CR23, 0x38 }, { CR24, 0x20 }, { CR26, 0x93 },
{ CR27, 0x15 }, { CR28, 0x3e }, { CR29, 0x00 },
{ CR33, 0x28 }, { CR34, 0x30 },
{ CR35, 0x43 }, /* 6112 3e->43 */
{ CR41, 0x24 }, { CR44, 0x32 },
{ CR46, 0x92 }, /* 6112 96->92 */
{ CR47, 0x1e },
{ CR48, 0x04 }, /* 5602 Roger */
{ CR49, 0xfa }, { CR79, 0x58 }, { CR80, 0x30 },
{ CR81, 0x30 }, { CR87, 0x0a }, { CR89, 0x04 },
{ CR91, 0x00 }, { CR92, 0x0a }, { CR98, 0x8d },
{ CR99, 0x28 }, { CR100, 0x02 },
{ CR101, 0x09 }, /* 6112 13->1f 6220 1f->13 6407 13->9 */
{ CR102, 0x27 },
{ CR106, 0x1c }, /* 5d07 5112 1f->1c 6220 1c->1f 6221 1f->1c */
{ CR107, 0x1c }, /* 6220 1c->1a 5221 1a->1c */
{ CR109, 0x13 },
{ CR110, 0x1f }, /* 6112 13->1f 6221 1f->13 6407 13->0x09 */
{ CR111, 0x13 }, { CR112, 0x1f }, { CR113, 0x27 },
{ CR114, 0x23 }, /* 6221 27->23 */
{ CR115, 0x24 }, /* 6112 24->1c 6220 1c->24 */
{ CR116, 0x24 }, /* 6220 1c->24 */
{ CR117, 0xfa }, /* 6112 fa->f8 6220 f8->f4 6220 f4->fa */
{ CR118, 0xf0 }, /* 5d07 6112 f0->f2 6220 f2->f0 */
{ CR119, 0x1a }, /* 6112 1a->10 6220 10->14 6220 14->1a */
{ CR120, 0x4f },
{ CR121, 0x1f }, /* 6220 4f->1f */
{ CR122, 0xf0 }, { CR123, 0x57 }, { CR125, 0xad },
{ CR126, 0x6c }, { CR127, 0x03 },
{ CR128, 0x14 }, /* 6302 12->11 */
{ CR129, 0x12 }, /* 6301 10->0f */
{ CR130, 0x10 }, { CR137, 0x50 }, { CR138, 0xa8 },
{ CR144, 0xac }, { CR146, 0x20 }, { CR252, 0xff },
{ CR253, 0xff },
};
static const u32 rv[] = {
UW2453_REGWRITE(4, 0x2b), /* configure reciever gain */
UW2453_REGWRITE(5, 0x19e4f), /* configure transmitter gain */
UW2453_REGWRITE(6, 0xf81ad), /* enable RX/TX filter tuning */
UW2453_REGWRITE(7, 0x3fffe), /* disable TX gain in test mode */
/* enter CAL_FIL mode, TX gain set by registers, RX gain set by pins,
* RSSI circuit powered down, reduced RSSI range */
UW2453_REGWRITE(0, 0x25f9c), /* 5d01 cal_fil */
/* synthesizer configuration for channel 1 */
UW2453_REGWRITE(1, 0x47),
UW2453_REGWRITE(2, 0x999),
/* disable manual VCO band selection */
UW2453_REGWRITE(3, 0x7602),
/* enable manual VCO band selection, configure current level */
UW2453_REGWRITE(3, 0x46063),
};
r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
if (r)
return r;
r = zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
if (r)
return r;
r = uw2453_init_mode(chip);
if (r)
return r;
/* Try all standard VCO configuration settings on channel 1 */
for (i = 0; i < ARRAY_SIZE(uw2453_std_vco_cfg) - 1; i++) {
/* Configure synthesizer for channel 1 */
r = uw2453_synth_set_channel(chip, 1, false);
if (r)
return r;
/* Write VCO config */
r = uw2453_write_vco_cfg(chip, uw2453_std_vco_cfg[i][0]);
if (r)
return r;
/* ack interrupt event */
r = zd_iowrite16_locked(chip, 0x0f, UW2453_INTR_REG);
if (r)
return r;
/* check interrupt status */
r = zd_ioread16_locked(chip, &intr_status, UW2453_INTR_REG);
if (r)
return r;
if (!(intr_status & 0xf)) {
dev_dbg_f(zd_chip_dev(chip),
"PLL locked on configuration %d\n", i);
found_config = i;
break;
}
}
if (found_config == -1) {
/* autocal */
dev_dbg_f(zd_chip_dev(chip),
"PLL did not lock, using autocal\n");
r = uw2453_synth_set_channel(chip, 1, true);
if (r)
return r;
r = uw2453_write_vco_cfg(chip, UW2453_AUTOCAL_VCO_CFG);
if (r)
return r;
}
/* To match the vendor driver behaviour, we use the configuration after
* the one that produced a lock. */
UW2453_PRIV(rf)->config = found_config + 1;
return zd_iowrite16_locked(chip, 0x06, CR203);
}
int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
{
int r;
struct zd_ioreq32 reqs[2] = {
[0] = { .addr = CR_MAC_ADDR_P1 },
[1] = { .addr = CR_MAC_ADDR_P2 },
};
reqs[0].value = (mac_addr[3] << 24)
| (mac_addr[2] << 16)
| (mac_addr[1] << 8)
| mac_addr[0];
reqs[1].value = (mac_addr[5] << 8)
| mac_addr[4];
dev_dbg_f(zd_chip_dev(chip),
"mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
mutex_lock(&chip->mutex);
r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
mutex_unlock(&chip->mutex);
return r;
}
int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
{
int r;
u32 value;
mutex_lock(&chip->mutex);
r = zd_ioread32_locked(chip, &value, E2P_SUBID);
