PUBLIC inline
void
Irq_muxer::handle(Upstream_irq const *ui)
{
assert (cpu_lock.test());
Irq_base::mask_and_ack();
ui->ack();
if (EXPECT_FALSE (!Irq_base::_next))
return;
int irqs = 0;
for (Irq_base *n = Irq_base::_next; n;)
{
++irqs;
n->__mask();
n = n->Irq_base::_next;
}
{
Smword old;
do
old = _mask_cnt;
while (!mp_cas(&_mask_cnt, old, old + irqs));
}
for (Irq_base *n = Irq_base::_next; n;)
{
Irq *i = nonull_static_cast<Irq*>(n);
i->hit(0);
n = i->Irq_base::_next;
}
}
/** Hardware interrupt entry point. Calls corresponding Dirq instance's
Dirq::hit() method.
@param irqobj hardware-interrupt object
*/
extern "C" FIASCO_FASTCALL
void
irq_interrupt(Mword _irqobj, Mword ip)
{
Mword irqobj = (Smword)((Signed32)_irqobj);
Thread::assert_irq_entry();
CNT_IRQ;
(void)ip;
// we're entered with disabled irqs
Irq_base *i = (Irq_base*)irqobj;
i->log();
irq_spinners(i->pin());
i->hit(0);
}
L4_msg_tag
Icu::op_icu_set_mode(Mword pin, Irq_chip::Mode mode)
{
Irq_mgr::Irq i = Irq_mgr::mgr->chip(pin);
if (!i.chip)
return commit_result(-L4_err::ENodev);
int r = i.chip->set_mode(i.pin, mode);
Irq_base *irq = i.chip->irq(i.pin);
if (irq)
{
auto g = lock_guard(irq->irq_lock());
if (irq->chip() == i.chip && irq->pin() == i.pin)
irq->switch_mode(i.chip->is_edge_triggered(i.pin));
}
return commit_result(r);
}
