void RegisterFile::initialize(const MCSchedModel &SM, unsigned NumRegs) {
// Create a default register file that "sees" all the machine registers
// declared by the target. The number of physical registers in the default
// register file is set equal to `NumRegs`. A value of zero for `NumRegs`
// means: this register file has an unbounded number of physical registers.
addRegisterFile({} /* all registers */, NumRegs);
if (!SM.hasExtraProcessorInfo())
return;
// For each user defined register file, allocate a RegisterMappingTracker
// object. The size of every register file, as well as the mapping between
// register files and register classes is specified via tablegen.
const MCExtraProcessorInfo &Info = SM.getExtraProcessorInfo();
for (unsigned I = 0, E = Info.NumRegisterFiles; I < E; ++I) {
const MCRegisterFileDesc &RF = Info.RegisterFiles[I];
// Skip invalid register files with zero physical registers.
unsigned Length = RF.NumRegisterCostEntries;
if (!RF.NumPhysRegs)
continue;
// The cost of a register definition is equivalent to the number of
// physical registers that are allocated at register renaming stage.
const MCRegisterCostEntry *FirstElt =
&Info.RegisterCostTable[RF.RegisterCostEntryIdx];
addRegisterFile(ArrayRef<MCRegisterCostEntry>(FirstElt, Length),
RF.NumPhysRegs);
}
}
RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
: NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
AvailableSlots(SM.MicroOpBufferSize), MaxRetirePerCycle(0) {
// Check if the scheduling model provides extra information about the machine
// processor. If so, then use that information to set the reorder buffer size
// and the maximum number of instructions retired per cycle.
if (SM.hasExtraProcessorInfo()) {
const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
if (EPI.ReorderBufferSize)
AvailableSlots = EPI.ReorderBufferSize;
MaxRetirePerCycle = EPI.MaxRetirePerCycle;
}
assert(AvailableSlots && "Invalid reorder buffer size!");
Queue.resize(AvailableSlots);
}
