/**
*
*
* This function defines the memory initialization flow for
* systems that only support RB processors.
*
* @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
*
* @return AGESA_STATUS
* - AGESA_ALERT
* - AGESA_FATAL
* - AGESA_SUCCESS
* - AGESA_WARNING
*/
AGESA_STATUS
MemMFlowDA (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
)
{
UINT8 Node;
UINT8 NodeCnt;
MEM_NB_BLOCK *NBPtr;
MEM_TECH_BLOCK *TechPtr;
NBPtr = MemMainPtr->NBPtr;
TechPtr = MemMainPtr->TechPtr;
NodeCnt = MemMainPtr->DieCount;
//----------------------------------------------------------------
// Initialize MCT
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemInitializeMCT, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
if (!NBPtr[Node].InitializeMCT (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// Low voltage DDR3
//----------------------------------------------------------------
// Levelize DDR3 voltage based on socket, as each socket has its own voltage for dimms.
AGESA_TESTPOINT (TpProcMemLvDdr3, &(MemMainPtr->MemPtr->StdHeader));
if (!MemFeatMain.LvDDR3 (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Initialize DRAM and DCTs, and Create Memory Map
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemInitMCT, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
// Initialize Memory Controller and Dram
IDS_HDT_CONSOLE ("!Node %d\n", Node);
if (!NBPtr[Node].InitMCT (&NBPtr[Node])) {
return AGESA_FATAL; // fatalexit
}
// Create memory map
AGESA_TESTPOINT (TpProcMemSystemMemoryMapping, &(MemMainPtr->MemPtr->StdHeader));
if (!NBPtr[Node].HtMemMapInit (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------
// If there is no dimm on the system, do fatal exit
//----------------------------------------------------
if (NBPtr[BSP_DIE].RefPtr->SysLimit == 0) {
PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &(MemMainPtr->MemPtr->StdHeader));
ASSERT (FALSE);
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Synchronize DCTs
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemSynchronizeDcts, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
if (!NBPtr[Node].SyncDctsReady (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// CpuMemTyping
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemMtrrConfiguration, &(MemMainPtr->MemPtr->StdHeader));
if (!NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE])) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Before Training Table values
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
MemFInitTableDrive (&NBPtr[Node], MTBeforeTrn);
}
//----------------------------------------------------------------
// Memory Context Restore
//----------------------------------------------------------------
if (!MemFeatMain.MemRestore (MemMainPtr)) {
// Do DQS training only if memory context restore fails
//----------------------------------------------------------------
// Training
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemDramTraining, &(MemMainPtr->MemPtr->StdHeader));
IDS_OPTION_HOOK (IDS_BEFORE_DQS_TRAINING, MemMainPtr, &(MemMainPtr->MemPtr->StdHeader));
MemMainPtr->mmSharedPtr->DimmExcludeFlag = TRAINING;
if (!MemFeatMain.Training (MemMainPtr)) {
return AGESA_FATAL;
}
IDS_HDT_CONSOLE ("\nEnd DQS training\n\n");
}
//----------------------------------------------------------------
// Disable chipselects that fail training
//----------------------------------------------------------------
MemMainPtr->mmSharedPtr->DimmExcludeFlag = END_TRAINING;
MemFeatMain.ExcludeDIMM (MemMainPtr);
MemMainPtr->mmSharedPtr->DimmExcludeFlag = NORMAL;
//----------------------------------------------------------------
// OtherTiming
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemOtherTiming, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
if (!NBPtr[Node].OtherTiming (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// After Training Table values
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
MemFInitTableDrive (&NBPtr[Node], MTAfterTrn);
}
//----------------------------------------------------------------
// SetDqsEccTimings
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemSetDqsEccTmgs, &(MemMainPtr->MemPtr->StdHeader));
for (Node = 0; Node < NodeCnt; Node++) {
if (!TechPtr[Node].SetDqsEccTmgs (&TechPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// Online Spare
//----------------------------------------------------------------
if (!MemFeatMain.OnlineSpare (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Interleave banks
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
if (NBPtr[Node].FeatPtr->InterleaveBanks (&NBPtr[Node])) {
if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
return AGESA_FATAL;
}
}
}
//----------------------------------------------------------------
// Interleave Nodes
//----------------------------------------------------------------
if (!MemFeatMain.InterleaveNodes (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Interleave channels
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
if (NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node])) {
if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
return AGESA_FATAL;
}
}
}
//----------------------------------------------------------------
// UMA Allocation & UMAMemTyping
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemUMAMemTyping, &(MemMainPtr->MemPtr->StdHeader));
if (!MemFeatMain.UmaAllocation (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Interleave region
//----------------------------------------------------------------
NBPtr[BSP_DIE].FeatPtr->InterleaveRegion (&NBPtr[BSP_DIE]);
//----------------------------------------------------------------
// ECC
//----------------------------------------------------------------
if (!MemFeatMain.InitEcc (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// Memory Clear
//----------------------------------------------------------------
AGESA_TESTPOINT (TpProcMemMemClr, &(MemMainPtr->MemPtr->StdHeader));
if (!MemFeatMain.MemClr (MemMainPtr)) {
return AGESA_FATAL;
}
//----------------------------------------------------------------
// OnDimm Thermal
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
if (NBPtr[Node].FeatPtr->OnDimmThermal (&NBPtr[Node])) {
if (NBPtr[Node].MCTPtr->ErrCode == AGESA_FATAL) {
return AGESA_FATAL;
}
}
}
//----------------------------------------------------------------
// Finalize MCT
//----------------------------------------------------------------
for (Node = 0; Node < NodeCnt; Node++) {
if (!NBPtr[Node].FinalizeMCT (&NBPtr[Node])) {
return AGESA_FATAL;
}
}
//----------------------------------------------------------------
// Memory Context Save
//----------------------------------------------------------------
MemFeatMain.MemSave (MemMainPtr);
//----------------------------------------------------------------
// Memory DMI support
//----------------------------------------------------------------
if (!MemFeatMain.MemDmi (MemMainPtr)) {
return AGESA_CRITICAL;
}
return AGESA_SUCCESS;
}
/**
*
* Check and disable Chip selects that fail training on all nodes.
*
* @param[in,out] *MemMainPtr - Pointer to the MEM_MAIN_DATA_BLOCK
*
* @return TRUE - No fatal error occurs.
* @return FALSE - Fatal error occurs.
*/
BOOLEAN
MemMRASExcludeDIMM (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
)
{
UINT8 Node;
BOOLEAN IsEnabled;
BOOLEAN RetVal;
BOOLEAN IsChannelIntlvEnabled[MAX_NODES_SUPPORTED];
UINT8 FirstEnabledNode;
UINT32 BottomIO;
MEM_NB_BLOCK *NBPtr;
MEM_PARAMETER_STRUCT *RefPtr;
S_UINT64 SMsr;
FirstEnabledNode = 0;
IsEnabled = FALSE;
RetVal = TRUE;
NBPtr = MemMainPtr->NBPtr;
RefPtr = NBPtr[BSP_DIE].RefPtr;
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
if (NBPtr[Node].FeatPtr->ExcludeDIMM (&NBPtr[Node])) {
if (!IsEnabled) {
// Record the first node that has exclude dimm enabled
FirstEnabledNode = Node;
IsEnabled = TRUE;
}
}
}
if (IsEnabled) {
// Check if all nodes have all dimms excluded. If yes, fatal exit
NBPtr[BSP_DIE].SharedPtr->CurrentNodeSysBase = 0;
BottomIO = (NBPtr[BSP_DIE].RefPtr->BottomIo & 0xF8) << 8;
// If the first node that has excluded dimms does not have a system base smaller
// than bottomIO, then we don't need to reset the GStatus, as we don't need to
// remap memory hole.
if (NBPtr[FirstEnabledNode].MCTPtr->NodeSysBase < BottomIO) {
RefPtr->GStatus[GsbHWHole] = FALSE;
RefPtr->GStatus[GsbSpIntRemapHole] = FALSE;
RefPtr->GStatus[GsbSoftHole] = FALSE;
RefPtr->HoleBase = 0;
RefPtr->SysLimit = 0;
}
// If Node Interleaving has been executed before the remapping then we need to
// start from the first node.
// There may be a few senarios:
// 1. Node interleaving is not enabled before the remap, and still cannot be enabled after
// remap
// 2. Node interleaving cannot be enabled before the remap, but it can be enabled after
// remap
// 3. Node interleaving is enabled before the remap, but it cannot be enabled after the remap
if (NBPtr->SharedPtr->NodeIntlv.IsValid) {
FirstEnabledNode = 0;
}
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
IsChannelIntlvEnabled [Node] = FALSE;
// Check if node interleaving has been enabled on this node
// if yes, disable it.
if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDramIntlvEn) != 0) {
NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvEn, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDramIntlvSel, 0);
}
if (Node >= FirstEnabledNode) {
// Remap memory on nodes with node number larger than the first node that has excluded dimms.
// If channel interleaving has already been enabled, need to disable it before remapping memory.
if (NBPtr[Node].GetBitField (&NBPtr[Node], BFDctSelIntLvEn) != 0) {
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelIntLvEn, 0);
IsChannelIntlvEnabled [Node] = TRUE;
}
NBPtr[Node].MCTPtr->Status[SbHWHole] = FALSE;
NBPtr[Node].MCTPtr->Status[SbSWNodeHole] = FALSE;
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseAddr, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHiRngEn, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelHi, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDctSelBaseOffset, 0);
NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
NBPtr[Node].HtMemMapInit (&NBPtr[Node]);
} else if (NBPtr[Node].MCTPtr->NodeMemSize != 0) {
// No change is needed in the memory map of this node.
// Need to adjust the current system base for other nodes processed later.
NBPtr[Node].SharedPtr->CurrentNodeSysBase = (NBPtr[Node].MCTPtr->NodeSysLimit + 1) & 0xFFFFFFF0;
RefPtr->SysLimit = NBPtr[Node].MCTPtr->NodeSysLimit;
// If the current node does not have the memory hole, then set DramHoleAddrReg to be 0.
// If memory hoisting is enabled later by other node, SyncAddrMapToAllNodes will set the base
// and DramMemHoistValid.
// Otherwise, do not change the register value, as we need to keep DramHoleOffset unchanged, as well
// DramHoleValid.
if (!NBPtr[Node].MCTPtr->Status[SbHWHole]) {
NBPtr[Node].SetBitField (&NBPtr[Node], BFDramHoleAddrReg, 0);
}
}
}
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
NBPtr[Node].SyncAddrMapToAllNodes (&NBPtr[Node]);
}
LibAmdMsrRead (TOP_MEM, (UINT64 *)&SMsr, &NBPtr->MemPtr->StdHeader);
// Only when TOM is set can CpuMemTyping be re-run
if ((SMsr.hi == 0) && (SMsr.lo == 0)) {
if (RefPtr->SysLimit != 0) {
NBPtr[BSP_DIE].CpuMemTyping (&NBPtr[BSP_DIE]);
}
}
// Re-run node interleaving if it has been exeucuted before the remap
if (NBPtr->SharedPtr->NodeIntlv.IsValid) {
MemFeatMain.InterleaveNodes (MemMainPtr);
}
// Re-enable channel interleaving if it was enabled before remapping memory
for (Node = 0; Node < MemMainPtr->DieCount; Node++) {
if (IsChannelIntlvEnabled [Node]) {
NBPtr[Node].FeatPtr->InterleaveChannels (&NBPtr[Node]);
}
}
}
// if all dimms on all nodes are excluded, do fatal exit
if (RefPtr->SysLimit == 0) {
PutEventLog (AGESA_FATAL, MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM, 0, 0, 0, 0, &NBPtr->MemPtr->StdHeader);
SetMemError (AGESA_FATAL, NBPtr[BSP_DIE].MCTPtr);
ASSERT (FALSE);
}
for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
RetVal &= (BOOLEAN) (NBPtr[Node].MCTPtr->ErrCode < AGESA_FATAL);
}
return RetVal;
}
