INT8
MemTGetLD3 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
INT8 LD;
MEM_NB_BLOCK *NBPtr;
NBPtr = TechPtr->NBPtr;
//
// For DDR3, BIOS calculates the latency difference (Ld) as equal to read CAS latency minus write CAS
// latency, in MEMCLKs (see F2x[1, 0]88[Tcl] and F2x[1, 0]84[Tcwl]) which can be a negative or positive
// value.
//
LD = ((INT8) NBPtr->GetBitField (NBPtr, BFTcl) + 4) - ((INT8) NBPtr->GetBitField (NBPtr, BFTcwl) + 5);
return LD;
}
VOID
MemRecTEMRS13 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT16 MrsAddress;
UINT8 DramTerm;
MEM_NB_BLOCK *NBPtr;
NBPtr = TechPtr->NBPtr;
// BA2=0,BA1=0,BA0=1
NBPtr->SetBitField (NBPtr, BFMrsBank, 1);
MrsAddress = 0;
// program MrsAddress[5,1]=output driver impedance control (DIC):
// based on F2x[1,0]84[DrvImpCtrl], which is 2'b01
MrsAddress |= ((UINT16) 1 << 1);
// program MrsAddress[9,6,2]=nominal termination resistance of ODT (RTT):
// based on F2x[1,0]84[DramTerm], which is 3'b001 (60 Ohms)
if (!(NBPtr->IsSupported[CheckDramTerm])) {
DramTerm = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTerm);
} else {
DramTerm = NBPtr->PsPtr->DramTerm;
}
if ((DramTerm & 1) != 0) {
MrsAddress |= ((UINT16) 1 << 2);
}
if ((DramTerm & 2) != 0) {
MrsAddress |= ((UINT16) 1 << 6);
}
if ((DramTerm & 4) != 0) {
MrsAddress |= ((UINT16) 1 << 9);
}
// program MrsAddress[12]=output disable (QOFF):
// based on F2x[1,0]84[Qoff], which is 1'b0
// program MrsAddress[11]=TDQS:
// based on F2x[1,0]94[RDqsEn], which is 1'b0
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
/**
*
* This function is the interface to call the PCI register access function
* defined in NB block.
*
* @param[in] *NBPtr - Pointer to the parameter structure MEM_NB_BLOCK
* @param[in] NodeID - Node ID number of the target Northbridge
* @param[in] DctNum - DCT number if applicable, otherwise, put 0
* @param[in] BitFieldName - targeted bitfield
*
* @retval UINT32 - 32 bits PCI register value
*
*/
UINT32
MemFGetPCI (
IN MEM_NB_BLOCK *NBPtr,
IN UINT8 NodeID,
IN UINT8 DctNum,
IN BIT_FIELD_NAME BitFieldName
)
{
MEM_NB_BLOCK *LocalNBPtr;
UINT8 Die;
// Find NBBlock that associates with node NodeID
for (Die = 0; (Die < MAX_NODES_SUPPORTED) && (NBPtr[Die].Node != NodeID); Die ++);
ASSERT (Die < MAX_NODES_SUPPORTED);
// Get the northbridge pointer for the targeted node.
LocalNBPtr = &NBPtr[Die];
LocalNBPtr->FamilySpecificHook[DCTSelectSwitch] (LocalNBPtr, &DctNum);
LocalNBPtr->Dct = DctNum;
// The caller of this function will take care of the ganged/unganged situation.
// So Ganged is set to be false here, and do PCI read on the DCT specified by DctNum.
return LocalNBPtr->GetBitField (LocalNBPtr, BitFieldName);
}
VOID
MemRecTEMRS23 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
UINT16 MrsAddress;
UINT8 DramTermDyn;
MEM_NB_BLOCK *NBPtr;
NBPtr = TechPtr->NBPtr;
// BA2=0,BA1=1,BA0=0
NBPtr->SetBitField (NBPtr, BFMrsBank, 2);
// program MrsAddress[5:3]=CAS write latency (CWL):
// based on F2x[1,0]84[Tcwl], which is 3'b000
//
MrsAddress = 0;
// program MrsAddress[6]=auto self refresh method (ASR):
// based on F2x[1,0]84[ASR], which is 1'b1
// program MrsAddress[7]=self refresh temperature range (SRT):
// based on F2x[1,0]84[SRT], which is also 1'b0
//
MrsAddress |= (UINT16) 1 << 6;
// program MrsAddress[10:9]=dynamic termination during writes (RTT_WR):
// based on F2x[1,0]84[DramTermDyn]
//
if (!(NBPtr->IsSupported[CheckDramTermDyn])) {
DramTermDyn = (UINT8) NBPtr->GetBitField (NBPtr, BFDramTermDyn);
} else {
DramTermDyn = NBPtr->PsPtr->DynamicDramTerm;
}
MrsAddress |= (UINT16) DramTermDyn << 9;
NBPtr->SetBitField (NBPtr, BFMrsAddress, MrsAddress);
}
VOID
MemTBeginTraining (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
S_UINT64 SMsr;
MEM_DATA_STRUCT *MemPtr;
MEM_NB_BLOCK *NBPtr;
NBPtr = TechPtr->NBPtr;
MemPtr = NBPtr->MemPtr;
LibAmdReadCpuReg (CR4_REG, &TechPtr->CR4reg);
LibAmdWriteCpuReg (CR4_REG, TechPtr->CR4reg | ((UINT32)1 << 9)); // enable SSE2
LibAmdMsrRead (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader); // HWCR
TechPtr->HwcrLo = SMsr.lo;
SMsr.lo |= 0x00020000; // turn on HWCR.wrap32dis
SMsr.lo &= 0xFFFF7FFF; // turn off HWCR.SSEDIS
LibAmdMsrWrite (HWCR, (UINT64 *) (&SMsr), &MemPtr->StdHeader);
TechPtr->DramEcc = (UINT8) NBPtr->GetBitField (NBPtr, BFDramEccEn);
NBPtr->SetBitField (NBPtr, BFDramEccEn, 0); // Disable ECC
}
