int32_t CenMbaTdCtlrCommon::setRtEteThresholds() { #define PRDF_FUNC "[CenMbaTdCtlrCommon::setRtEteThresholds] " int32_t o_rc = SUCCESS; do { const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR"; SCAN_COMM_REGISTER_CLASS * mbstr = iv_membChip->getRegister( reg_str ); // MBSTR's content could be modified from cleanupCmd() // so we need to refresh o_rc = mbstr->ForceRead(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "ForceRead() failed on %s", reg_str ); break; } uint16_t softIntCe = 0; o_rc = getScrubCeThreshold( iv_mbaChip, iv_rank, softIntCe ); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "getScrubCeThreshold() failed." ); break; } // Only care about retry CEs if there are a lot of them. So the // threshold will be high in the field. However, in MNFG the retry CEs // will be handled differently by putting every occurrence in the RCE // table and doing targeted diagnostics when needed. uint16_t retryCe = mfgMode() ? 1 : 2047; uint16_t hardCe = 1; // Always stop on first occurrence. mbstr->SetBitFieldJustified( 4, 12, softIntCe ); mbstr->SetBitFieldJustified( 16, 12, softIntCe ); mbstr->SetBitFieldJustified( 28, 12, hardCe ); mbstr->SetBitFieldJustified( 40, 12, retryCe ); // Set the per symbol counters to count hard CEs only. This is so that // when the scrub stops on the first hard CE, we can use the per symbol // counters to tell us which symbol reported the hard CE. mbstr->SetBitFieldJustified( 55, 3, 0x1 ); o_rc = mbstr->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str ); break; } } while(0); return o_rc; #undef PRDF_FUNC }
// Do the setup for mnfg IPL CE int32_t CenMbaTdCtlr::mnfgCeSetup() { #define PRDF_FUNC "[CenMbaTdCtlr::mnfgCeSetup] " int32_t o_rc = SUCCESS; do { const char * reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR"; SCAN_COMM_REGISTER_CLASS * mbstr = iv_membChip->getRegister( reg_str ); // MBSTR's content could be modified from cleanupCmd() // so we need to refresh o_rc = mbstr->ForceRead(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC"Read() failed on %s", reg_str ); break; } if ( TPS_PHASE_1 == iv_tdState ) { // Enable per-symbol error counters to count soft CEs mbstr->SetBit(55); mbstr->SetBit(56); // Disable per-symbol error counters to count hard CEs mbstr->ClearBit(57); } else if ( TPS_PHASE_2 == iv_tdState ) { // Disable per-symbol error counters to count soft CEs mbstr->ClearBit(55); mbstr->ClearBit(56); // Enable per-symbol error counters to count hard CEs mbstr->SetBit(57); } else { PRDF_ERR( PRDF_FUNC"Inavlid State:%u", iv_tdState ); o_rc = FAIL; break; } o_rc = mbstr->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC"Write() failed on %s", reg_str ); break; } } while(0); return o_rc; #undef PRDF_FUNC }
int32_t CenMbaTdCtlrCommon::prepareNextCmd( bool i_clearStats ) { #define PRDF_FUNC "[CenMbaTdCtlrCommon::prepareNextCmd] " int32_t o_rc = SUCCESS; do { //---------------------------------------------------------------------- // Clean up previous command //---------------------------------------------------------------------- o_rc = cleanupPrevCmd(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "cleanupPrevCmd() failed" ); break; } //---------------------------------------------------------------------- // Clear ECC counters //---------------------------------------------------------------------- const char * reg_str = NULL; if ( i_clearStats ) { reg_str = (0 == iv_mbaPos) ? "MBA0_MBSTR" : "MBA1_MBSTR"; SCAN_COMM_REGISTER_CLASS * mbstr = iv_membChip->getRegister( reg_str ); // MBSTR's content could be modified from cleanupCmd() // so we need to refresh o_rc = mbstr->ForceRead(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "ForceRead() failed on %s", reg_str ); break; } mbstr->SetBit(53); // Setting this bit clears all counters. o_rc = mbstr->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str ); break; } // Hardware automatically clears bit 53, so flush this register out // of the register cache to avoid clearing the counters again with // a write from the out-of-date cached copy. RegDataCache & cache = RegDataCache::getCachedRegisters(); cache.flush( iv_membChip, mbstr ); } //---------------------------------------------------------------------- // Clear ECC FIRs //---------------------------------------------------------------------- reg_str = (0 == iv_mbaPos) ? "MBA0_MBSECCFIR_AND" : "MBA1_MBSECCFIR_AND"; SCAN_COMM_REGISTER_CLASS * firand = iv_membChip->getRegister( reg_str ); firand->setAllBits(); // Clear all scrub MPE bits. // This will need to be done when starting a TD procedure or background // scrubbing. iv_rank may not be set when starting background scrubbing // and technically there should only be one of these MPE bits on at a // time so we should not have to worry about losing an attention by // clearing them all. firand->SetBitFieldJustified( 20, 8, 0 ); // Clear scrub NCE, SCE, MCE, RCE, SUE, UE bits (36-41) firand->SetBitFieldJustified( 36, 6, 0 ); o_rc = firand->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on %s", reg_str ); break; } SCAN_COMM_REGISTER_CLASS * spaAnd = iv_mbaChip->getRegister("MBASPA_AND"); spaAnd->setAllBits(); // Clear threshold exceeded attentions spaAnd->SetBitFieldJustified( 1, 4, 0 ); o_rc = spaAnd->Write(); if ( SUCCESS != o_rc ) { PRDF_ERR( PRDF_FUNC "Write() failed on MBASPA_AND" ); break; } } while (0); return o_rc; #undef PRDF_FUNC }