/// \brief Perform target specific adjustments to the latency of a schedule /// dependency. void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst, SDep &Dep) const { MachineInstr *SrcInst = Src->getInstr(); MachineInstr *DstInst = Dst->getInstr(); if (!Src->isInstr() || !Dst->isInstr()) return; const HexagonInstrInfo *QII = static_cast<const HexagonInstrInfo *>(getInstrInfo()); // Instructions with .new operands have zero latency. if (QII->canExecuteInBundle(*SrcInst, *DstInst) && isBestZeroLatency(Src, Dst, QII)) { Dep.setLatency(0); return; } if (!hasV60TOps()) return; // Don't adjust the latency of post-increment part of the instruction. if (QII->isPostIncrement(*SrcInst) && Dep.isAssignedRegDep()) { if (SrcInst->mayStore()) return; if (Dep.getReg() != SrcInst->getOperand(0).getReg()) return; } else if (QII->isPostIncrement(*DstInst) && Dep.getKind() == SDep::Anti) { if (DstInst->mayStore()) return; if (Dep.getReg() != DstInst->getOperand(0).getReg()) return; } else if (QII->isPostIncrement(*DstInst) && DstInst->mayStore() && Dep.isAssignedRegDep()) { MachineOperand &Op = DstInst->getOperand(DstInst->getNumOperands() - 1); if (Op.isReg() && Dep.getReg() != Op.getReg()) return; } // Check if we need to change any the latency values when Phis are added. if (useBSBScheduling() && SrcInst->isPHI()) { changePhiLatency(*SrcInst, Dst, Dep); return; } // If it's a REG_SEQUENCE, use its destination instruction to determine // the correct latency. if (DstInst->isRegSequence() && Dst->NumSuccs == 1) DstInst = Dst->Succs[0].getSUnit()->getInstr(); // Try to schedule uses near definitions to generate .cur. if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) && isBestZeroLatency(Src, Dst, QII)) { Dep.setLatency(0); return; } updateLatency(*SrcInst, *DstInst, Dep); }