void b_transport(tlm_generic_payload& trans, sc_time& delay){
tlm_command cmd = trans.get_command();
sc_dt::uint64 adr = trans.get_address();
unsigned char* ptr = trans.get_data_ptr();
unsigned int len = trans.get_data_length();
unsigned char* byt = trans.get_byte_enable_ptr();
unsigned int wid = trans.get_streaming_width();
#ifdef DEBUGMODE
cerr << sc_time_stamp() << ": " << name() << " - Transaction " << trans.is_write() << " for Address " << adr << " with ";
cerr << "data length " << len << " and streaming width " << wid << endl;
// ofstream outFile("cache.txt", ios::app);
// outFile << sc_time_stamp() << " " << trans.get_address() << " " << trans.get_data_length() << " " << trans.is_write() << endl;
#endif
unsigned int words = len / sizeof(BUSWIDTH);
if (len%sizeof(BUSWIDTH) != 0) words++;
if(this->scratchpadEn && adr >= this->scratchStart && adr + len <= (this->scratchStart + this->scratchSize)) {
//Using local scratchpad
if(this->scratchMemory == NULL){
THROW_EXCEPTION(__PRETTY_FUNCTION__ << ": Trying to access a NULL scratchpad");
}
if(cmd == TLM_READ_COMMAND)
memcpy(ptr, &scratchMemory[adr - this->scratchStart], len);
else if(cmd == TLM_WRITE_COMMAND)
memcpy(&scratchMemory[adr - this->scratchStart], ptr, len);
else THROW_EXCEPTION(__PRETTY_FUNCTION__ << ": Undefined TLM command");
this->numScratchAcc++;
wait(words*this->scratchLatency);
trans.set_response_status(TLM_OK_RESPONSE);
return;
}
else if (adr > cacheLimit){
this->initSocket->b_transport(trans,delay);
}
else {
if (cmd == TLM_READ_COMMAND) {
this->readFromCache(adr, ptr, len);
trans.set_response_status(TLM_OK_RESPONSE);
}
else if (cmd == TLM_WRITE_COMMAND) {
this->writeToCache(adr, ptr, len);
if (writePolicy == THROUGH || writePolicy == THROUGH_ALL) {
this->initSocket->b_transport(trans,delay);
}
else trans.set_response_status(TLM_OK_RESPONSE);
}
else THROW_EXCEPTION(__PRETTY_FUNCTION__ << ": Undefined TLM command");
this->numAccesses++;
}
#ifdef DEBUGMODE
cerr << sc_time_stamp() << ": " << name() << " - Transaction " << trans.is_write() << " for Address " << adr << " completed with data ";
if (trans.get_data_length() == 4) cerr << (unsigned int) (*trans.get_data_ptr()) << endl;
else cerr << "ND" << endl;
#endif
trans.set_dmi_allowed(false); // Disables DMI in order to insert the cache latency for each transaction
}
