static BaseSemantics::RiscOperatorsPtr make_ops() {
SymbolicSemantics::RiscOperatorsPtr retval = SymbolicSemantics::RiscOperators::instance(regdict);
retval->computingDefiners(do_usedef ? SymbolicSemantics::TRACK_ALL_DEFINERS : SymbolicSemantics::TRACK_NO_DEFINERS);
TestSemantics<SymbolicSemantics::SValuePtr, BaseSemantics::RegisterStateGenericPtr,
SymbolicSemantics::MemoryStatePtr, BaseSemantics::StatePtr,
SymbolicSemantics::RiscOperatorsPtr> tester;
tester.test(retval);
return retval;
}
static BaseSemantics::RiscOperatorsPtr make_ops() {
SymbolicSemantics::RiscOperatorsPtr retval = SymbolicSemantics::RiscOperators::instance(regdict);
retval->set_compute_usedef(do_usedef);
TestSemantics<SymbolicSemantics::SValuePtr, BaseSemantics::RegisterStateGenericPtr,
SymbolicSemantics::MemoryStatePtr, BaseSemantics::StatePtr,
SymbolicSemantics::RiscOperatorsPtr> tester;
tester.test(retval);
return retval;
}
int
main() {
const RegisterDictionary *regdict = RegisterDictionary::dictionary_i386();
SymbolicSemantics::RiscOperatorsPtr ops = SymbolicSemantics::RiscOperators::instance(regdict);
RegisterStateGenericPtr rstate = RegisterStateGeneric::promote(ops->currentState()->registerState());
SValuePtr x;
Formatter fmt;
fmt.set_line_prefix(" ");
// Write all 32 bits of a register
std::cout <<"write reg@0+32\n";
RegisterDescriptor r_0_32(x86_regclass_gpr, 0, 0, 32);
rstate->writeRegister(r_0_32, ops->undefined_(32), ops.get());
rstate->print(std::cout, fmt);
// Write low-order 16 bits of a register
std::cout <<"\nwrite reg@0+16\n";
RegisterDescriptor r_0_16(x86_regclass_gpr, 0, 0, 16);
rstate->writeRegister(r_0_16, ops->undefined_(16), ops.get());
rstate->print(std::cout, fmt);
// Read bits 8-31. Bits [8-15] are from one register and [16-31] are from another
std::cout <<"\nread reg@8+24\n";
RegisterDescriptor r_8_24(x86_regclass_gpr, 0, 8, 24);
x = rstate->readRegister(r_8_24, ops->undefined_(r_8_24.get_nbits()), ops.get());
std::cout <<" got " <<*x <<"\n";
rstate->print(std::cout, fmt);
}
void visit(SgNode *node) {
SgAsmBlock *block = isSgAsmBlock(node);
if (block && block->has_instructions()) {
using namespace rose::BinaryAnalysis::InstructionSemantics2;
const RegisterDictionary *regdict = RegisterDictionary::dictionary_i386();
SymbolicSemantics::RiscOperatorsPtr ops = SymbolicSemantics::RiscOperators::instance(regdict);
ops->computingDefiners(SymbolicSemantics::TRACK_ALL_DEFINERS); // only used so we can test that it works
BaseSemantics::DispatcherPtr dispatcher = DispatcherX86::instance(ops, 32);
const SgAsmStatementPtrList &stmts = block->get_statementList();
for (SgAsmStatementPtrList::const_iterator si=stmts.begin(); si!=stmts.end(); ++si) {
SgAsmX86Instruction *insn = isSgAsmX86Instruction(*si);
if (insn) {
std::cout <<unparseInstructionWithAddress(insn) <<"\n";
dispatcher->processInstruction(insn);
std::cout <<*ops <<"\n";
}
}
}
}
NoOperation::NoOperation(Disassembler *disassembler) {
normalizer_ = StateNormalizer::instance();
if (disassembler) {
const RegisterDictionary *registerDictionary = disassembler->get_registers();
ASSERT_not_null(registerDictionary);
size_t addrWidth = disassembler->instructionPointerRegister().get_nbits();
SMTSolver *solver = NULL;
SymbolicSemantics::RiscOperatorsPtr ops = SymbolicSemantics::RiscOperators::instance(registerDictionary, solver);
ops->computingDefiners(SymbolicSemantics::TRACK_NO_DEFINERS);
ops->computingMemoryWriters(SymbolicSemantics::TRACK_LATEST_WRITER); // necessary to erase non-written memory
BaseSemantics::MemoryCellListPtr mstate = BaseSemantics::MemoryCellList::promote(ops->currentState()->memoryState());
ASSERT_not_null(mstate);
mstate->occlusionsErased(true);
cpu_ = disassembler->dispatcher()->create(ops, addrWidth, registerDictionary);
}
}