/**
* PCIe Post Init
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
PciePostEarlyInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
IDS_OPTION_HOOK (IDS_BEFORE_GPP_TRAINING, Pcie, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
PciePortsVisibilityControlV5 (UnhidePorts, Pcie);
Status = PciePostEarlyPortInitML (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieTrainingV2 (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
PciePortsVisibilityControlV5 (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostEarlyInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
STATIC
PcieEarlyInitTN (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieFP2CriteriaTN (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallbackTN, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
PcieEarlyStaticInitTN (Pcie);
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLetPllPersonalityInitCallbackTN, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
PcieOscInitTN (Pcie);
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackTN, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackTN, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
PcieSetVoltageTN (PcieGen1, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitTN Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
PcieEarlyInterfaceCZ (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceCZ Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
PciePortsVisibilityControlV5 (UnhidePorts, Pcie);
Status = PcieEarlyInitCZ (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieEarlyPortInitCZ (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieTrainingV2 (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
PciePortsVisibilityControlV5 (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInterfaceCZ Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* PCIe Mid Init
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
PcieInitAtMid (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
PciePortsVisibilityControl (UnhidePorts, Pcie);
Status = PciePortLateInit (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieLateInit (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
PciePortsVisibilityControl (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
NbInitAtLatePost (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_PLATFORM_CONFIG Gnb;
UINT32 NumberOfSockets;
UINT32 SocketId;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Enter\n");
Status = NbAllocateConfigData (StdHeader, &Gnb);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
NumberOfSockets = GnbGetNumberOfSockets (StdHeader);
for (SocketId = 0; SocketId < NumberOfSockets; SocketId++) {
UINT32 NumberOfSilicons;
UINT32 SiliconId;
if (!GnbIsDevicePresentInSocket (SocketId, StdHeader)) {
continue;
}
NumberOfSilicons = GnbGetNumberOfSiliconsOnSocket (SocketId, StdHeader);
for (SiliconId = 0; SiliconId < NumberOfSilicons; SiliconId++) {
Gnb.GnbPciAddress = GnbGetPciAddress (SocketId, SiliconId, StdHeader);
Status = NbInitPowerManagement (&Gnb);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
GnbLock (Gnb.GnbPciAddress, StdHeader);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "NbInitAtLatePost Exit[0x%x]\n", Status);
return Status;
}
/**
* PCIe Post Init
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
PciePostS3InterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
PciePortsVisibilityControlV5 (UnhidePorts, Pcie);
Status = PciePostInitML (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
Status = PciePostS3PortInitML (Pcie);
} else {
Status = PciePostPortInitML (Pcie);
}
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieTrainingV2 (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
PciePortsVisibilityControlV5 (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostS3InterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* PCIe Mid Init
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
PcieMidInterfaceKV (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PCIe_INFO_BUFFER PcieInfoBuffer;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceKV Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
PciePortsVisibilityControlV5 (UnhidePorts, Pcie);
Status = PcieMidCharacterizationKV (&PcieInfoBuffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieMidPortInitKV (&PcieInfoBuffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieMidInitKV (&PcieInfoBuffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
PciePortsVisibilityControlV5 (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInterfaceKV Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GnbEarlierInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINT32 D0F0xBC_xC00C002C;
FIRMWARE_HEADER_V7 *SmuFwHeader;
UINTN SmuFwSize;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
UINT32 PspMBox;
AgesaStatus = AGESA_SUCCESS;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEarlierInitTableBeforeSmuML,
0,
0,
StdHeader
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
SmuFwHeader = NULL;
GnbRegisterReadML (GnbHandle, D0F0xBC_xC00C002C_TYPE, D0F0xBC_xC00C002C_ADDRESS, &D0F0xBC_xC00C002C, 0, StdHeader);
D0F0xBC_xC00C002C &= (BIT1 + BIT2 + BIT3 + BIT4 + BIT5);
IDS_HDT_CONSOLE (GNB_TRACE, " D0F0xBC_xC00C002C = 0x%x\n", D0F0xBC_xC00C002C);
Status = GnbLoadBuildOptionDataML (StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
//Load the SMU for non secure part & blank part
if ((D0F0xBC_xC00C002C == 0) || (D0F0xBC_xC00C002C == BIT5 + BIT3)) {
Status = GnbGetSmuFirmwareML ((UINTN *)&SmuFwHeader, &SmuFwSize);
ASSERT (SmuFwHeader != NULL);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GnbSmuFirmwareLoadV7 (GnbHandle, SmuFwHeader, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
} else {
Status = GnbPspMBoxRead (&PspMBox, GnbHandle, StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, " PSP Mailbox Status = 0x%x\n", PspMBox);
if (Status == AGESA_SUCCESS) {
if ((PspMBox & MBOX_STATUS_RECOVERY) == MBOX_STATUS_RECOVERY) {
/// SET CfgUseSMUServices flag for recovery mode
GnbBuildOptionData->CfgUseSMUServices = FALSE;
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceML Exit [0x%x]\n", Status);
return AgesaStatus;
}
/**
* GNB Scs interface
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
GnbScsInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINTN ScsDataAddress;
UINTN ScsDataSize;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = AGESA_SUCCESS;
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
if ((GnbBuildOptionData->CfgUseSMUServices == TRUE) &&
(GnbBuildOptionData->GnbCommonOptions.CfgScsSupport == TRUE)) {
IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Supported\n");
GnbHandle = GnbGetHandle (StdHeader);
Status = GnbGetScsDataML (&ScsDataAddress, &ScsDataSize);
ASSERT (ScsDataAddress != NULL);
Status = GnbSmuLoadScsDataV7 (GnbHandle, (UINT8 *)ScsDataAddress, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Exit [0x%x]\n", Status);
return AgesaStatus;
}
AGESA_STATUS
PcieEdpPortPowerCheckCZ (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
GMMx1206C_STRUCT GMMx1206C;
BOOLEAN EdpPresent;
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEdpPortPowerCheckCZ Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
EdpPresent = FALSE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
DdiEdpPortDetectCallbackCZ,
(VOID *)&EdpPresent,
Pcie
);
if (EdpPresent == FALSE) {
// Power off
GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx1206C_TYPE, GMMx1206C_ADDRESS, &GMMx1206C.Value, 0, GnbLibGetHeader (Pcie));
GMMx1206C.Field.LVTMA_PWRSEQ_EN = 0;
GMMx1206C.Field.LVTMA_PWRSEQ_TARGET_STATE = 0;
GMMx1206C.Field.LVTMA_BLON_OVRD = 0;
GnbRegisterWriteCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx1206C_TYPE, GMMx1206C_ADDRESS, &GMMx1206C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidBeforeGfxInitCZ Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
PcieConfigRunProcForAllWrappers (
IN UINT32 DescriptorFlags,
IN PCIe_RUN_ON_WRAPPER_CALLBACK Callback,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_WRAPPER_CONFIG *Wrapper;
AgesaStatus = AGESA_SUCCESS;
Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetChild (DESCRIPTOR_ALL_WRAPPERS, &Pcie->Header);
while (Wrapper != NULL) {
if (!(PcieLibIsVirtualDesciptor (Wrapper) && (DescriptorFlags & DESCRIPTOR_VIRTUAL) == 0)) {
if ((DescriptorFlags & DESCRIPTOR_ALL_WRAPPERS & Wrapper->Header.DescriptorFlags) != 0) {
Status = Callback (Wrapper, Buffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
}
Wrapper = (PCIe_WRAPPER_CONFIG *) PcieConfigGetNextTopologyDescriptor (Wrapper, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
return AgesaStatus;
}
AGESA_STATUS
PcieConfigRunProcForAllDescriptors (
IN UINT32 InDescriptorFlags,
IN UINT32 OutDescriptorFlags,
IN UINT32 TerminationFlags,
IN PCIe_RUN_ON_DESCRIPTOR_CALLBACK Callback,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_DESCRIPTOR_HEADER *Descriptor;
AgesaStatus = AGESA_SUCCESS;
Descriptor = PcieConfigGetChild (InDescriptorFlags & DESCRIPTOR_ALL_TYPES, &Pcie->Header);
while (Descriptor != NULL) {
if ((InDescriptorFlags & Descriptor->DescriptorFlags) != 0 && (OutDescriptorFlags && Descriptor->DescriptorFlags) == 0) {
Status = Callback (Descriptor, Buffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
Descriptor = (PCIe_DESCRIPTOR_HEADER *) PcieConfigGetNextTopologyDescriptor (Descriptor, TerminationFlags);
}
return AgesaStatus;
}
/**
* Enumerate all display connectors for specific display device type.
*
*
*
* @param[in] Engine Engine configuration info
* @param[in,out] Buffer Buffer pointer
* @param[in] Pcie PCIe configuration info
*/
VOID
STATIC
GfxIntegratedDdiInterfaceCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
CONNECTOR_ENUM_INFO *ConnectorEnumInfo;
EXT_CONNECTOR_INFO *ExtConnectorInfo;
ConnectorEnumInfo = (CONNECTOR_ENUM_INFO*) Buffer;
ExtConnectorInfo = GfxIntegratedExtConnectorInfo (Engine->Type.Ddi.DdiData.ConnectorType);
if (ExtConnectorInfo == NULL) {
AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo->Status);
PcieConfigDisableEngine (Engine);
return;
}
if (ExtConnectorInfo->DisplayDeviceEnum != ConnectorEnumInfo->DisplayDeviceEnum) {
//Not device type we are looking for
return;
}
if (Engine->Type.Ddi.DisplayPriorityIndex >= ConnectorEnumInfo->RequestedPriorityIndex &&
Engine->Type.Ddi.DisplayPriorityIndex < ConnectorEnumInfo->CurrentPriorityIndex) {
ConnectorEnumInfo->CurrentPriorityIndex = Engine->Type.Ddi.DisplayPriorityIndex;
ConnectorEnumInfo->Engine = Engine;
}
}
AGESA_STATUS
PcieInit (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallback, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
PcieFmPreInit (Pcie);
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitCallback, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
STATIC
PcieEarlyInitCZ (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCZ Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieConfigRunProcForAllDescriptors (DESCRIPTOR_SILICON, 0, DESCRIPTOR_TERMINATE_TOPOLOGY, PciePortMapInitCallbackCZ, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePhyLaneInitInitCallbackCZ, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieEarlyInitCallbackCZ, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCZ Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Build integrated info table
* GMC FB access requred
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
GfxIntInfoTableInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
GFX_PLATFORM_CONFIG *Gfx;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Enter\n");
AgesaStatus = AGESA_SUCCESS;
if (GfxLibIsControllerPresent (StdHeader)) {
Status = GfxLocateConfigData (StdHeader, &Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status != AGESA_FATAL) {
Status = GfxIntInfoTableInitTN (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInterfaceTN Exit[0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* PCIe Post Init
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
PciePostInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
IDS_OPTION_HOOK (IDS_BEFORE_GEN2_INIT, Pcie, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
if ((Status == AGESA_SUCCESS) &&
(GnbBuildOptionData->CfgUseSMUServices == TRUE)) {
PciePortsVisibilityControlV5 (UnhidePorts, Pcie);
Status = PciePostInitML (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PciePostPortInitML (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
Status = PcieTrainingV2 (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader);
GnbSmuBiosTableGetPcieInfoML (StdHeader, Pcie);
PciePortsVisibilityControlV5 (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
STATIC
PcieMidInitKV (
IN OUT PCIe_INFO_BUFFER *PcieInfoBuffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitKV Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieMidInitCallbackKV, (VOID *) PcieInfoBuffer, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = PciePowerGateKV (Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidInitKV Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Enumerate all display connectors
*
*
*
* @param[out] DisplayPathList Display path list
* @param[in,out] Pcie PCIe platform configuration info
* @param[in] Gfx Gfx configuration info
*/
AGESA_STATUS
GfxIntegratedEnumerateAllConnectors (
OUT EXT_DISPLAY_PATH *DisplayPathList,
IN OUT PCIe_PLATFORM_CONFIG *Pcie,
IN GFX_PLATFORM_CONFIG *Gfx
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Enter\n");
Status = GfxIntegratedEnumConnectorsForDevice (
DEVICE_DFP,
DisplayPathList,
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxIntegratedEnumConnectorsForDevice (
DEVICE_CRT,
DisplayPathList,
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxIntegratedEnumConnectorsForDevice (
DEVICE_LCD,
DisplayPathList,
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAllConnectors Exit [0x%x]\n", Status);
return AgesaStatus;
}
AGESA_STATUS
STATIC
PcieMapPortsPciAddresses (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_WRAPPER_CONFIG *WrapperList;
PCIe_ENGINE_CONFIG *EngineList;
AgesaStatus = AGESA_SUCCESS;
WrapperList = PcieConfigGetChildWrapper (Silicon);
while (WrapperList != NULL) {
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieLibIsPcieEngine (EngineList) && PcieLibIsEngineAllocated (EngineList)) {
Status = PcieFmMapPortPciAddress (EngineList);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
EngineList->Type.Port.Address.AddressValue = MAKE_SBDFO (
0,
Silicon->Address.Address.Bus,
EngineList->Type.Port.PortData.DeviceNumber,
EngineList->Type.Port.PortData.FunctionNumber,
0
);
} else {
EngineList->Type.Port.PortData.PortPresent = OFF;
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to allocate PCI address for PCIe port\n"
);
//Report error
PutEventLog (
AGESA_ERROR,
GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION,
EngineList->Type.Port.PortData.DeviceNumber,
0,
0,
0,
GnbLibGetHeader (Pcie)
);
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
return AgesaStatus;
}
AGESA_STATUS
PcieMapTopologyOnComplex (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN PCIe_COMPLEX_CONFIG *Complex,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *Silicon;
PCIe_WRAPPER_CONFIG *Wrapper;
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n");
Silicon = PcieConfigGetChildSilicon (Complex);
while (Silicon != NULL) {
Wrapper = PcieConfigGetChildWrapper (Silicon);
while (Wrapper != NULL) {
Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n",
PcieFmDebugGetWrapperNameString (Wrapper)
);
ASSERT (FALSE);
}
Wrapper = PcieLibGetNextDescriptor (Wrapper);
}
Status = PcieMapPortsPciAddresses (Silicon, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Silicon = PcieLibGetNextDescriptor (Silicon);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GnbLibDispatchFeatures (
IN OPTION_GNB_CONFIGURATION *ConfigTable,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
AgesaStatus = AGESA_SUCCESS;
while (ConfigTable->GnbFeature != NULL) {
Status = ConfigTable->GnbFeature (StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ConfigTable++;
}
return AgesaStatus;
}
AGESA_STATUS
PciePostInit (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
PcieFmSetBootUpVoltage (
PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie),
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
STATIC
PcieMidCharacterizationKV (
IN OUT PCIe_INFO_BUFFER *PcieInfoBuffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
UINT8 Index;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidCharacterizationKV Enter\n");
AgesaStatus = AGESA_SUCCESS;
// Set initial stats for all PcieInfoBuffer fields
for (Index = 0; Index < NUMBER_OF_SUBLINKS; Index++) {
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->SublinkInfo[Index].GppPortCount = 0;
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->SublinkInfo[Index].MaxGenCapability = Gen1;
}
for (Index = 0; Index < NUMBER_OF_WRAPPERS; Index++) {
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].MinAspmL1ExitLatency = 255;
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].AnyDevFailPllpdnb = FALSE;
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].DisableL1OnWrapper = FALSE;
}
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieMidPortCharacterizationCallbackKV,
(VOID *) PcieInfoBuffer,
Pcie
);
Status = PcieConfigRunProcForAllWrappers (
DESCRIPTOR_ALL_WRAPPERS,
PcieMidWrapperCharacterizationCallbackKV,
(VOID *) PcieInfoBuffer,
Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidCharacterizationKV Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GnbEarlyInterfaceML (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GNB_HANDLE *GnbHandle;
UINT32 Property;
GNB_BUILD_OPTIONS_ML *GnbBuildOptionData;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Enter\n");
GnbHandle = GnbGetHandle (StdHeader);
GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
ASSERT (GnbBuildOptionData != NULL);
Property = TABLE_PROPERTY_DEFAULT;
Property |= UserOptions.CfgGnbSyncFloodPinAsNmi ? TABLE_PROPERTY_NMI_SYNCFLOOD : 0;
IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG, GnbHandle, StdHeader);
GnbInitSmuBiosTableML (StdHeader);
Status = GnbProcessTable (
GnbHandle,
GnbEarlyInitTableML,
Property,
0,
StdHeader
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (GnbBuildOptionData->CfgUseSMUServices == TRUE) {
GnbRequestVddNbPminML (GnbHandle, StdHeader);
}
Status = GfxGBifEnableML (StdHeader);
ASSERT (Status == AGESA_SUCCESS);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GnbLibDispatchFeatures (
IN OPTION_GNB_CONFIGURATION *ConfigTable,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
CPU_LOGICAL_ID LogicalId;
AgesaStatus = AGESA_SUCCESS;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
while (ConfigTable->GnbFeature != NULL) {
if ((ConfigTable->Type & LogicalId.Family) != 0) {
Status = ConfigTable->GnbFeature (StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
ConfigTable++;
}
return AgesaStatus;
}
AGESA_STATUS
PcieFmAlibBuildAcpiTable (
IN VOID *AlibSsdtPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
UINT32 AmlObjName;
GFX_PLATFORM_CONFIG *Gfx;
VOID *AmlObjPtr;
BOOLEAN AltVddNbSupport;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n");
AgesaStatus = AGESA_SUCCESS;
AltVddNbSupport = TRUE;
// AmlObjName = 'A0DA';
AmlObjName = 0x41304441;
AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
Status = GfxLocateConfigData (StdHeader, &Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
ASSERT (Status == AGESA_SUCCESS);
if ((Status != AGESA_SUCCESS) || (GnbBuildOptions.CfgAltVddNb == FALSE) || (Gfx->UmaInfo.MemClock > DDR1333_FREQUENCY) ||
((Gfx->GfxDiscreteCardInfo.AmdPcieGfxCardBitmap != 0) && GfxLibIsControllerPresent (StdHeader))) {
AltVddNbSupport = FALSE;
}
// CBS/IDS can change AltVddNbSupport
IDS_OPTION_HOOK (IDS_GNB_ALTVDDNB, &AltVddNbSupport, StdHeader);
if (!AltVddNbSupport) {
IDS_HDT_CONSOLE (GNB_TRACE, " AltVddNb - Disabled\n");
*(UINT8*)((UINT8*) AmlObjPtr + 5) = 0;
}
} else {
AgesaStatus = AGESA_ERROR;
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GfxMidInterfaceTN (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GFX_PLATFORM_CONFIG *Gfx;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = GfxLocateConfigData (StdHeader, &Gfx);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_FATAL) {
GfxFmDisableController (StdHeader);
} else {
if (Gfx->UmaInfo.UmaMode != UMA_NONE) {
Status = GfxEnableGmmAccess (Gfx);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status != AGESA_SUCCESS) {
// Can not initialize GMM registers going to disable GFX controller
IDS_HDT_CONSOLE (GNB_TRACE, " Fail to establish GMM access\n");
Gfx->UmaInfo.UmaMode = UMA_NONE;
GfxFmDisableController (StdHeader);
} else {
Status = GfxGmcInitTN (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxSetBootUpVoltageTN (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxInitSsid (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxIntegratedEnumerateAudioConnectors (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
exec803 /* GfxAzWorkaroundTN */ (Gfx);
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxMidInterfaceTN Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
GfxInitSview (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
GFX_PLATFORM_CONFIG *Gfx;
UINT32 OriginalCmdReg;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Enter\n");
AgesaStatus = AGESA_SUCCESS;
Status = GfxLocateConfigData (StdHeader, &Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
if (GfxLibIsControllerPresent (StdHeader)) {
if (!GfxFmIsVbiosPosted (Gfx)) {
GFX_VBIOS_IMAGE_INFO VbiosImageInfo;
LibAmdMemCopy (&VbiosImageInfo.StdHeader, StdHeader, sizeof (AMD_CONFIG_PARAMS), StdHeader);
VbiosImageInfo.ImagePtr = NULL;
VbiosImageInfo.GfxPciAddress = Gfx->GfxPciAddress;
VbiosImageInfo.Flags = GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST;
GnbLibPciRead (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, &OriginalCmdReg, StdHeader);
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0xff, BIT1 | BIT2 | BIT0, StdHeader);
Status = AgesaGetVbiosImage (0, &VbiosImageInfo);
if (Status == AGESA_SUCCESS && VbiosImageInfo.ImagePtr != NULL) {
GfxLibCopyMemToFb (VbiosImageInfo.ImagePtr, 0, (*((UINT8*) VbiosImageInfo.ImagePtr + 2)) << 9, Gfx);
} else {
GfxFmDisableController (StdHeader);
AgesaStatus = AGESA_ERROR;
}
GnbLibPciRMW (Gfx->GfxPciAddress.AddressValue | 0x4, AccessS3SaveWidth8, 0x00, OriginalCmdReg, StdHeader);
}
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxInitSview Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
PcieAlibBuildAcpiTableV2 (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT VOID **AlibSsdtPtr
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
VOID *AlibSsdtBuffer;
VOID *AlibSsdtTable;
UINTN AlibSsdtlength;
UINT32 AmlObjName;
VOID *AmlObjPtr;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTableV2 Enter\n");
AgesaStatus = AGESA_SUCCESS;
AlibSsdtTable = GnbFmAlibGetBaseTable (StdHeader);
AlibSsdtlength = ((ACPI_TABLE_HEADER*) AlibSsdtTable)->TableLength;
if (*AlibSsdtPtr == NULL) {
AlibSsdtBuffer = GnbAllocateHeapBuffer (
AMD_ACPI_ALIB_BUFFER_HANDLE,
AlibSsdtlength,
StdHeader
);
ASSERT (AlibSsdtBuffer != NULL);
if (AlibSsdtBuffer == NULL) {
return AGESA_ERROR;
}
*AlibSsdtPtr = AlibSsdtBuffer;
} else {
AlibSsdtBuffer = *AlibSsdtPtr;
}
// Check length of port data
ASSERT (sizeof (_ALIB_PORT_DATA) <= 20);
// Check length of global data
ASSERT (sizeof (_ALIB_GLOBAL_DATA) <= 32);
// Copy template to buffer
LibAmdMemCopy (AlibSsdtBuffer, AlibSsdtTable, AlibSsdtlength, StdHeader);
// Update table OEM fields.
LibAmdMemCopy (
(VOID *) &((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->OemId,
(VOID *) &GnbBuildOptions.OemIdString,
sizeof (GnbBuildOptions.OemIdString),
StdHeader);
LibAmdMemCopy (
(VOID *) &((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->OemTableId,
(VOID *) &GnbBuildOptions.OemTableIdString,
sizeof (GnbBuildOptions.OemTableIdString),
StdHeader);
//
// Update register base base
//
PcieAlibUpdateGnbData (AlibSsdtBuffer, StdHeader);
//
// Update transfer block
//
AmlObjName = STRING_TO_UINT32 ('A', 'D', 'A', 'T');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
if (AmlObjPtr != NULL) {
AmlObjPtr = (UINT8 *) AmlObjPtr + 10;
}
// Dispatch function from table
Status = GnbLibDispatchFeaturesV2 (&AlibDispatchTableV2[0], AmlObjPtr, StdHeader);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (AgesaStatus != AGESA_SUCCESS) {
//Shrink table length to size of the header
((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
}
ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibBuildAcpiTableV2 Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
