void at91rm9200_emac_init(void *arg)
{
at91rm9200_emac_softc_t *sc = arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
/*
*This is for stuff that only gets done once (at91rm9200_emac_init()
* gets called multiple times
*/
if (sc->txDaemonTid == 0) {
/* Set up EMAC hardware */
at91rm9200_emac_init_hw(sc);
/* Start driver tasks */
sc->rxDaemonTid = rtems_bsdnet_newproc("ENrx",
4096,
at91rm9200_emac_rxDaemon,
sc);
sc->txDaemonTid = rtems_bsdnet_newproc("ENtx",
4096,
at91rm9200_emac_txDaemon,
sc);
} /* if txDaemonTid */
/* set our priority in the AIC */
AIC_SMR_REG(AIC_SMR_EMAC) = AIC_SMR_PRIOR(EMAC_INT_PRIORITY);
/* install the interrupt handler */
BSP_install_rtems_irq_handler(&at91rm9200_emac_isr_data);
/* EMAC doesn't support promiscuous, so ignore requests */
if (ifp->if_flags & IFF_PROMISC) {
printk ("Warning - AT91RM9200 Ethernet driver"
" doesn't support Promiscuous Mode!\n");
}
/*
* Tell the world that we're running.
*/
ifp->if_flags |= IFF_RUNNING;
/* Enable TX/RX and clear the statistics counters */
EMAC_REG(EMAC_CTL) = (EMAC_CTL_TE | EMAC_CTL_RE | EMAC_CTL_CSR);
/* clear any pending interrupts */
EMAC_REG(EMAC_TSR) = 0xffffffff;
EMAC_REG(EMAC_RSR) = 0xffffffff;
} /* at91rm9200_emac_init() */
void Clock_driver_support_initialize_hardware(void)
{
uint32_t st_str;
int slck;
/* the system timer is driven from SLCK */
slck = at91rm9200_get_slck();
st_pimr_value =
(((rtems_configuration_get_microseconds_per_tick() * slck) + (1000000/2))/ 1000000);
st_pimr_reload = st_pimr_value;
/* read the status to clear the int */
st_str = ST_REG(ST_SR);
/* set priority */
AIC_SMR_REG(AIC_SMR_SYSIRQ) = AIC_SMR_PRIOR(0x7);
/* set the timer value */
ST_REG(ST_PIMR) = st_pimr_reload;
}
error_t sama5d3GigabitEthInit(NetInterface *interface)
{
error_t error;
volatile uint32_t status;
//Debug message
TRACE_INFO("Initializing SAMA5D3 Gigabit Ethernet MAC...\r\n");
//Enable GMAC peripheral clock
PMC->PMC_PCER1 = (1 << (ID_GMAC - 32));
//Enable IRQ controller peripheral clock
PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
//GPIO configuration
sama5d3GigabitEthInitGpio(interface);
//Configure MDC clock speed
GMAC->GMAC_NCFGR = GMAC_NCFGR_DBW_DBW64 | GMAC_NCFGR_CLK_MCK_224;
//Enable management port (MDC and MDIO)
GMAC->GMAC_NCR |= GMAC_NCR_MPE;
//PHY transceiver initialization
error = interface->phyDriver->init(interface);
//Failed to initialize PHY transceiver?
if(error) return error;
//Set the MAC address
GMAC->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
GMAC->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
//Configure the receive filter
GMAC->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
//Initialize hash table
GMAC->GMAC_HRB = 0;
GMAC->GMAC_HRT = 0;
//Initialize buffer descriptors
sama5d3GigabitEthInitBufferDesc(interface);
//Clear transmit status register
GMAC->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_UND | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
//Clear receive status register
GMAC->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
//First disable all GMAC interrupts
GMAC->GMAC_IDR = 0xFFFFFFFF;
//Only the desired ones are enabled
GMAC->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
//Read GMAC ISR register to clear any pending interrupt
status = GMAC->GMAC_ISR;
//Configure interrupt controller
AIC->AIC_SSR = ID_GMAC;
AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_GIGABIT_ETH_IRQ_PRIORITY);
AIC->AIC_SVR = (uint32_t) sama5d3GigabitEthIrqHandler;
//Enable the GMAC to transmit and receive data
GMAC->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
//Force the TCP/IP stack to check the link state
osSetEvent(&interface->nicRxEvent);
//SAMA5D3 Gigabit Ethernet MAC is now ready to send
osSetEvent(&interface->nicTxEvent);
//Successful initialization
return NO_ERROR;
}
