//*****************************************************************************
//
//! @brief Get the current stimer capture register value.
//!
//! @param ui32CaptureNum is the Capture Register Number to read.
//!
//! This function can be used to read the value in an stimer capture register.
//!
//!
//! @return None.
//
//*****************************************************************************
uint32_t am_hal_stimer_capture_get(uint32_t ui32CaptureNum)
{
if ( ui32CaptureNum > 7 )
{
return 0;
}
return AM_REGVAL(AM_REG_STIMER_CAPTURE(0, ui32CaptureNum));
}
//*****************************************************************************
//
//! @brief Get the current stimer compare register value.
//!
//! @param ui32CmprInstance is the compare register instance number (0-7).
//!
//! This function can be used to read the value in an stimer compare register.
//!
//!
//! @return None.
//
//*****************************************************************************
uint32_t
am_hal_stimer_compare_get(uint32_t ui32CmprInstance)
{
if ( ui32CmprInstance > 7 )
{
return 0;
}
return AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance));
}
//*****************************************************************************
//
//! @brief Set the compare value.
//!
//! @param ui32CmprInstance is the compare register instance number (0-7).
//! @param ui32Delta is the value to add to the STimer counter and load into
//! the comparator register.
//!
//! NOTE: There is no way to set an absolute value into a comparator register.
//! Only deltas added to the STimer counter can be written to the compare
//! registers.
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_stimer_compare_delta_set(uint32_t ui32CmprInstance, uint32_t ui32Delta)
{
if ( ui32CmprInstance > 7 )
{
return;
}
AM_REGVAL(AM_REG_STIMER_COMPARE(0, ui32CmprInstance)) = ui32Delta;
}
//*****************************************************************************
//
//! @brief Enables the ITM
//!
//! This function enables the ARM ITM by setting the TRCENA bit in the DEMCR
//! register.
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_itm_enable(void)
{
if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M)
{
return;
}
//
// To be able to access ITM registers, set the Trace Enable bit
// in the Debug Exception and Monitor Control Register (DEMCR).
//
AM_REG(SYSCTRL, DEMCR) |= AM_REG_SYSCTRL_DEMCR_TRCENA(1);
while ( !(AM_REG(SYSCTRL, DEMCR) & AM_REG_SYSCTRL_DEMCR_TRCENA(1)) );
//
// Write the key to the ITM Lock Access register to unlock the ITM_TCR.
//
AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL;
//
// Set the enable bits in the ITM trace enable register, and the ITM
// control registers to enable trace data output.
//
AM_REGVAL(AM_REG_ITM_TPR_O) = 0x0000000f;
AM_REGVAL(AM_REG_ITM_TER_O) = 0xffffffff;
//
// Write to the ITM control and status register (don't enable yet).
//
AM_REGVAL(AM_REG_ITM_TCR_O) =
AM_WRITE_SM(AM_REG_ITM_TCR_ATB_ID, 0x15) |
AM_WRITE_SM(AM_REG_ITM_TCR_TS_FREQ, 1) |
AM_WRITE_SM(AM_REG_ITM_TCR_TS_PRESCALE, 1) |
AM_WRITE_SM(AM_REG_ITM_TCR_SWV_ENABLE, 1) |
AM_WRITE_SM(AM_REG_ITM_TCR_DWT_ENABLE, 0) |
AM_WRITE_SM(AM_REG_ITM_TCR_SYNC_ENABLE, 0) |
AM_WRITE_SM(AM_REG_ITM_TCR_TS_ENABLE, 0) |
AM_WRITE_SM(AM_REG_ITM_TCR_ITM_ENABLE, 1);
}
//*****************************************************************************
//
//! @brief Disables the ITM
//!
//! This function completely disables the ARM ITM by resetting the TRCENA bit
//! in the DEMCR register.
//!
//! @return None.
//
//*****************************************************************************
void
am_hal_itm_disable(void)
{
if (g_ui32HALflags & AM_HAL_FLAGS_ITMSKIPENABLEDISABLE_M)
{
return;
}
//
// Make sure the ITM_TCR is unlocked.
//
AM_REGVAL(AM_REG_ITM_LOCKAREG_O) = AM_REG_ITM_LOCKAREG_KEYVAL;
//
// Make sure the ITM/TPIU is not busy.
//
while ( AM_REG(ITM, TCR) & AM_REG_ITM_TCR_BUSY(1) );
//
// Disable the ITM.
//
for (int ix = 0; ix < 100; ix++)
{
AM_REG(ITM, TCR) &= ~AM_REG_ITM_TCR_ITM_ENABLE(1);
while ( AM_REG(ITM, TCR) & (AM_REG_ITM_TCR_ITM_ENABLE(1) | AM_REG_ITM_TCR_BUSY(1)) );
}
//
// Reset the TRCENA bit in the DEMCR register, which should disable the ITM
// for operation.
//
AM_REG(SYSCTRL, DEMCR) &= ~AM_REG_SYSCTRL_DEMCR_TRCENA(1);
//
// Disable the TPIU clock source in MCU control.
//
AM_REG(MCUCTRL, TPIUCTRL) = AM_REG_MCUCTRL_TPIUCTRL_CLKSEL_0MHz |
AM_REG_MCUCTRL_TPIUCTRL_ENABLE_DIS;
}