void platform_init_interrupts(void)
{
GICDISTREG(DISTCONTROL) = 0;
GICDISTREG(CLRENABLE) = 0xffff0000;
GICDISTREG(SETENABLE) = 0x0000ffff;
GICDISTREG(CLRPEND) = 0xffffffff;
GICDISTREG(GROUP) = 0;
GICCPUREG(PMR) = 0xf0;
for (int i = 0; i < 32 / 4; i++) {
GICDISTREG(PRIORITY + i * 4) = 0x80808080;
}
for (int i = 32/16; i < MAX_INT / 16; i++) {
GICDISTREG(NSACR + i * 4) = 0xffffffff;
}
for (int i = 32/32; i < MAX_INT / 32; i++) {
GICDISTREG(CLRENABLE + i * 4) = 0xffffffff;
GICDISTREG(CLRPEND + i * 4) = 0xffffffff;
GICDISTREG(GROUP + i * 4) = 0;
}
for (int i = 32/4; i < MAX_INT / 4; i++) {
GICDISTREG(_TARGET + i * 4) = 0;
GICDISTREG(PRIORITY + i * 4) = 0x80808080;
}
GICDISTREG(DISTCONTROL) = 1; // enable GIC0, IRQ only
GICCPUREG(CONTROL) = (0<<3)|(0<<2)||1; // enable GIC0, IRQ only, group 0 set to IRQ
#if 0
hexdump((void *)GIC_PROC_BASE, 0x20);
hexdump((void *)GIC_DISTRIB_BASE, 0x10);
printf("config: "); hexdump((void *)GIC_DISTRIB_BASE + CONFIG, 0x10);
printf("group: "); hexdump((void *)GIC_DISTRIB_BASE + GROUP, 0x10);
printf("priority: "); hexdump((void *)GIC_DISTRIB_BASE + PRIORITY, 0x40);
printf("enable: "); hexdump((void *)GIC_DISTRIB_BASE + SETENABLE, 0x10);
printf("pending: "); hexdump((void *)GIC_DISTRIB_BASE + SETPEND, 0x10);
printf("active: "); hexdump((void *)GIC_DISTRIB_BASE + SETACTIVE, 0x10);
// trigger interrupt
gic_set_enable(34, true);
//GICDISTREG(SETPEND + 4) = (1<<2);
//GICDISTREG(SETACTIVE + 4) = (1<<2);
GICDISTREG(SGIR) = (2 << 24) | 1;
printf("ISR 0x%x\n", (uint32_t)ARM64_READ_SYSREG(isr_el1));
printf("daif 0x%x\n", (uint32_t)ARM64_READ_SYSREG(daif));
arch_enable_interrupts();
printf("daif 0x%x\n", (uint32_t)ARM64_READ_SYSREG(daif));
#endif
}
void arch_init(void)
{
arch_mp_init_percpu();
#if WITH_SMP
LTRACEF("midr_el1 0x%llx\n", ARM64_READ_SYSREG(midr_el1));
secondaries_to_init = SMP_MAX_CPUS - 1; /* TODO: get count from somewhere else, or add cpus as they boot */
lk_init_secondary_cpus(secondaries_to_init);
LTRACEF("releasing %d secondary cpus\n", secondaries_to_init);
/* release the secondary cpus */
spin_unlock(&arm_boot_cpu_lock);
/* flush the release of the lock, since the secondary cpus are running without cache on */
arch_clean_cache_range((addr_t)&arm_boot_cpu_lock, sizeof(arm_boot_cpu_lock));
#endif
}
static uint64_t read_counter(void)
{
return ARM64_READ_SYSREG(CNTPCT_EL0);
}
