Static void
ar9287_olpc_temp_compensation(struct athn_softc *sc)
{
const struct ar9287_eeprom *eep = sc->sc_eep;
int8_t pdadc, slope, tcomp;
uint32_t reg;
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc);
if (sc->sc_pdadc == 0 || pdadc == 0)
return; /* No frames transmitted yet. */
/* Compute Tx gain temperature compensation. */
if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
slope = eep->baseEepHeader.tempSensSlope;
else
slope = 0;
if (slope != 0) /* Prevents division by zero. */
tcomp = ((pdadc - sc->sc_pdadc) * 4) / slope;
else
tcomp = 0;
DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp);
/* Write compensation value for both Tx chains. */
reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11);
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg);
reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11);
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg);
AR_WRITE_BARRIER(sc);
}
int
ar9380_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
uint32_t freq = c->ic_freq;
uint32_t chansel, phy;
if (IEEE80211_IS_CHAN_2GHZ(c)) {
if (AR_SREV_9485(sc))
chansel = ((freq << 16) - 215) / 15;
else
chansel = (freq << 16) / 15;
AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE);
} else {
chansel = (freq << 15) / 15;
chansel >>= 1;
AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, 0);
}
/* Enable Long Shift Select for synthesizer. */
AR_SETBITS(sc, AR_PHY_65NM_CH0_SYNTH4,
AR_PHY_SYNTH4_LONG_SHIFT_SELECT);
AR_WRITE_BARRIER(sc);
/* Program synthesizer. */
phy = (chansel << 2) | AR9380_FRACMODE;
DPRINTFN(4, ("AR_PHY_65NM_CH0_SYNTH7=0x%08x\n", phy));
AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy);
AR_WRITE_BARRIER(sc);
/* Toggle Load Synth Channel bit. */
AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH);
AR_WRITE_BARRIER(sc);
return (0);
}
void
ar9380_set_correction(struct athn_softc *sc, struct ieee80211_channel *c)
{
const struct ar9380_eeprom *eep = sc->eep;
const struct ar9380_modal_eep_header *modal;
uint32_t reg;
int8_t slope;
int i, corr, temp, temp0;
if (IEEE80211_IS_CHAN_2GHZ(c))
modal = &eep->modalHeader2G;
else
modal = &eep->modalHeader5G;
for (i = 0; i < AR9380_MAX_CHAINS; i++) {
ar9380_get_correction(sc, c, i, &corr, &temp);
if (i == 0)
temp0 = temp;
reg = AR_READ(sc, AR_PHY_TPC_11_B(i));
reg = RW(reg, AR_PHY_TPC_11_OLPC_GAIN_DELTA, corr);
AR_WRITE(sc, AR_PHY_TPC_11_B(i), reg);
/* Enable open loop power control. */
reg = AR_READ(sc, AR_PHY_TPC_6_B(i));
reg = RW(reg, AR_PHY_TPC_6_ERROR_EST_MODE, 3);
AR_WRITE(sc, AR_PHY_TPC_6_B(i), reg);
}
/* Enable temperature compensation. */
if (IEEE80211_IS_CHAN_5GHZ(c) &&
eep->base_ext2.tempSlopeLow != 0) {
if (c->ic_freq <= 5500) {
slope = athn_interpolate(c->ic_freq,
5180, eep->base_ext2.tempSlopeLow,
5500, modal->tempSlope);
} else {
slope = athn_interpolate(c->ic_freq,
5500, modal->tempSlope,
5785, eep->base_ext2.tempSlopeHigh);
}
} else
slope = modal->tempSlope;
reg = AR_READ(sc, AR_PHY_TPC_19);
reg = RW(reg, AR_PHY_TPC_19_ALPHA_THERM, slope);
AR_WRITE(sc, AR_PHY_TPC_19, reg);
reg = AR_READ(sc, AR_PHY_TPC_18);
reg = RW(reg, AR_PHY_TPC_18_THERM_CAL, temp0);
AR_WRITE(sc, AR_PHY_TPC_18, reg);
AR_WRITE_BARRIER(sc);
}
int
ar9485_pmu_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
{
int ntries;
AR_WRITE(sc, addr, val);
/* Wait for write to complete. */
for (ntries = 0; ntries < 100; ntries++) {
if (AR_READ(sc, addr) == val)
return (0);
AR_WRITE(sc, addr, val); /* Insist. */
AR_WRITE_BARRIER(sc);
DELAY(10);
}
return (ETIMEDOUT);
}
void
ar9380_spur_mitigate_cck(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
/* NB: It is safe to call this function for 5GHz channels. */
static const int16_t freqs[] = { 2420, 2440, 2464, 2480 };
int i, spur, freq;
uint32_t reg;
for (i = 0; i < nitems(freqs); i++) {
spur = freqs[i] - c->ic_freq;
if (abs(spur) < 10) /* +/- 10MHz range. */
break;
}
if (i == nitems(freqs)) {
/* Disable CCK spur mitigation. */
reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0);
reg &= ~AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
AR_WRITE_BARRIER(sc);
return;
}
freq = (spur * 524288) / 11;
reg = AR_READ(sc, AR_PHY_AGC_CONTROL);
reg = RW(reg, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
AR_WRITE(sc, AR_PHY_AGC_CONTROL, reg);
reg = AR_READ(sc, AR_PHY_CCK_SPUR_MIT);
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, freq);
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
reg = RW(reg, AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, 0x2);
reg |= AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT;
AR_WRITE(sc, AR_PHY_CCK_SPUR_MIT, reg);
AR_WRITE_BARRIER(sc);
}
PUBLIC void
ar9287_1_3_setup_async_fifo(struct athn_softc *sc)
{
uint32_t reg;
/*
* MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is
* enabled, so the following counters have to be changed.
*/
AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER,
AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
reg = AR_READ(sc, AR_AHB_MODE);
reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
AR_WRITE(sc, AR_AHB_MODE, reg);
AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
AR_WRITE_BARRIER(sc);
}
Static void
ar9287_olpc_init(struct athn_softc *sc)
{
uint32_t reg;
AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
reg = AR_READ(sc, AR9287_AN_TXPC0);
reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,
AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
AR_WRITE(sc, AR9287_AN_TXPC0, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
}
void
ar9280_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
{
const struct athn_gain *prog = sc->tx_gain;
const uint32_t *pvals;
int i;
if (IEEE80211_IS_CHAN_2GHZ(c))
pvals = prog->vals_2g;
else
pvals = prog->vals_5g;
for (i = 0; i < prog->nregs; i++)
AR_WRITE(sc, prog->regs[i], pvals[i]);
}
void
ar9380_init_swreg(struct athn_softc *sc)
{
const struct ar9380_eeprom *eep = sc->eep;
if (eep->baseEepHeader.featureEnable & AR_EEP_INTERNAL_REGULATOR) {
/* Internal regulator is ON. */
AR_CLRBITS(sc, AR_RTC_REG_CONTROL1,
AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
AR_WRITE(sc, AR_RTC_REG_CONTROL0, eep->baseEepHeader.swreg);
AR_SETBITS(sc, AR_RTC_REG_CONTROL1,
AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
} else
AR_SETBITS(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_SWREG_PRD);
AR_WRITE_BARRIER(sc);
}
void
ar9280_olpc_temp_compensation(struct athn_softc *sc)
{
const struct ar5416_eeprom *eep = sc->eep;
int8_t pdadc, txgain, tcomp;
uint32_t reg;
int i;
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
DPRINTFN(3, ("PD Avg Out=%d\n", pdadc));
if (sc->pdadc == 0 || pdadc == 0)
return; /* No frames transmitted yet. */
/* Compute Tx gain temperature compensation. */
if (sc->eep_rev >= AR_EEP_MINOR_VER_20 &&
eep->baseEepHeader.dacHiPwrMode_5G)
tcomp = (pdadc - sc->pdadc + 4) / 8;
else
tcomp = (pdadc - sc->pdadc + 5) / 10;
DPRINTFN(3, ("OLPC temp compensation=%d\n", tcomp));
if (tcomp == sc->tcomp)
return; /* Don't rewrite the same values. */
sc->tcomp = tcomp;
/* Adjust Tx gain values. */
for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
txgain = sc->tx_gain_tbl[i] - tcomp;
if (txgain < 0)
txgain = 0;
reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
reg = RW(reg, AR_PHY_TX_GAIN, txgain);
AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
}
AR_WRITE_BARRIER(sc);
}
void
ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
const struct ar_spur_chan *spurchans;
int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;
int spur_off, range, i;
/* NB: Always clear. */
AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
range = (extc != NULL) ? 19 : 10;
spurchans = sc->ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
spur = spurchans[i].spurChan;
if (spur == AR_NO_SPUR)
return; /* XXX disable if it was enabled! */
spur /= 10;
if (IEEE80211_IS_CHAN_2GHZ(c))
spur += AR_BASE_FREQ_2GHZ;
else
spur += AR_BASE_FREQ_5GHZ;
spur -= c->ic_freq;
if (abs(spur) < range)
break;
}
if (i == AR_EEPROM_MODAL_SPURS)
return; /* XXX disable if it was enabled! */
DPRINTFN(2, ("enabling spur mitigation\n"));
AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
AR_WRITE(sc, AR_PHY_SPUR_REG,
AR_PHY_SPUR_REG_MASK_RATE_CNTL |
AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
AR_PHY_SPUR_REG_MASK_RATE_SELECT |
AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
#ifndef IEEE80211_NO_HT
if (extc != NULL) {
spur_delta_phase = (spur * 262144) / 10;
if (spur < 0) {
spur_subchannel_sd = 1;
spur_off = spur + 10;
} else {
spur_subchannel_sd = 0;
spur_off = spur - 10;
}
} else
#endif
{
spur_delta_phase = (spur * 524288) / 10;
spur_subchannel_sd = 0;
spur_off = spur;
}
if (IEEE80211_IS_CHAN_2GHZ(c))
spur_freq_sd = (spur_off * 2048) / 44;
else
spur_freq_sd = (spur_off * 2048) / 40;
AR_WRITE(sc, AR_PHY_TIMING11,
AR_PHY_TIMING11_USE_SPUR_IN_AGC |
SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
AR_WRITE(sc, AR_PHY_SFCORR_EXT,
SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
AR_WRITE_BARRIER(sc);
bin = spur * 320;
ar5008_set_viterbi_mask(sc, bin);
}
Static void
ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
{
const struct ar9287_eeprom *eep = sc->sc_eep;
uint8_t boundaries[AR_PD_GAINS_IN_MASK];
uint8_t pdadcs[AR_NUM_PDADC_VALUES];
uint8_t xpdgains[AR9287_NUM_PD_GAINS];
int8_t txpower;
uint8_t overlap;
uint32_t reg, offset;
int i, j, nxpdgains;
if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) {
overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
}
else
overlap = eep->modalHeader.pdGainOverlap;
if (sc->sc_flags & ATHN_FLAG_OLPC) {
/* XXX not here. */
sc->sc_pdadc =
((const struct ar_cal_data_per_freq_olpc *)
eep->calPierData2G[0])->vpdPdg[0][0];
}
nxpdgains = 0;
memset(xpdgains, 0, sizeof(xpdgains));
for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
if (nxpdgains >= AR9287_NUM_PD_GAINS)
break; /* Can't happen. */
if (eep->modalHeader.xpdGain & (1 << i))
xpdgains[nxpdgains++] = i;
}
reg = AR_READ(sc, AR_PHY_TPCRG1);
reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
AR_WRITE(sc, AR_PHY_TPCRG1, reg);
AR_WRITE_BARRIER(sc);
for (i = 0; i < AR9287_MAX_CHAINS; i++) {
if (!(sc->sc_txchainmask & (1 << i)))
continue;
offset = i * 0x1000;
if (sc->sc_flags & ATHN_FLAG_OLPC) {
ar9287_olpc_get_pdgain(sc, c, i, &txpower);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
/* NB: txpower is in half dB. */
reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset);
reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);
AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg);
AR_WRITE_BARRIER(sc);
continue; /* That's it for open loop mode. */
}
/* Closed loop power control. */
ar9287_get_pdadcs(sc, c, i, nxpdgains, overlap,
boundaries, pdadcs);
/* Write boundaries. */
if (i == 0) {
reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
overlap);
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
boundaries[0]);
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
boundaries[1]);
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
boundaries[2]);
reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
boundaries[3]);
AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
}
/* Write PDADC values. */
for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) {
AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
pdadcs[j + 0] << 0 |
pdadcs[j + 1] << 8 |
pdadcs[j + 2] << 16 |
pdadcs[j + 3] << 24);
}
AR_WRITE_BARRIER(sc);
}
}
Static void
ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
const struct ar9287_eeprom *eep = sc->sc_eep;
const struct ar9287_modal_eep_header *modal = &eep->modalHeader;
uint32_t reg, offset;
int i;
AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
for (i = 0; i < AR9287_MAX_CHAINS; i++) {
offset = i * 0x1000;
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
modal->antCtrlChain[i]);
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
modal->iqCalICh[i]);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
modal->iqCalQCh[i]);
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
modal->bswMargin[i]);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
modal->bswAtten[i]);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
modal->rxTxMarginCh[i]);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
modal->txRxAttenCh[i]);
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
}
reg = AR_READ(sc, AR_PHY_SETTLING);
#ifndef IEEE80211_NO_HT
if (extc != NULL)
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
else
#endif
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
reg = AR_READ(sc, AR_PHY_RF_CTL3);
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
reg = AR_READ(sc, AR_PHY_CCA(0));
reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
AR_WRITE(sc, AR_PHY_CCA(0), reg);
reg = AR_READ(sc, AR_PHY_EXT_CCA0);
reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
reg = AR_READ(sc, AR9287_AN_RF2G3_CH0);
reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR9287_AN_RF2G3_CH1);
reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_PHY_RF_CTL2);
reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart);
reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
reg = AR_READ(sc, AR9287_AN_TOP2);
reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
AR_WRITE(sc, AR9287_AN_TOP2, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
}
void
ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
const struct ar9285_eeprom *eep = sc->eep;
const struct ar9285_modal_eep_header *modal = &eep->modalHeader;
uint32_t reg, offset = 0x1000;
uint8_t ob[5], db1[5], db2[5];
uint8_t txRxAtten;
AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain);
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
if (sc->eep_rev >= AR_EEP_MINOR_VER_3) {
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
modal->bswMargin);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
modal->bswAtten);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
modal->xatten2Margin);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
modal->xatten2Db);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg);
/* Duplicate values of chain 0 for chain 1. */
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
modal->bswMargin);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
modal->bswAtten);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
modal->xatten2Margin);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
modal->xatten2Db);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
}
if (sc->eep_rev >= AR_EEP_MINOR_VER_3)
txRxAtten = modal->txRxAtten;
else /* Workaround for ROM versions < 14.3. */
txRxAtten = 23;
reg = AR_READ(sc, AR_PHY_RXGAIN);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
AR_WRITE(sc, AR_PHY_RXGAIN, reg);
/* Duplicate values of chain 0 for chain 1. */
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
if (modal->version >= 3) {
/* Setup antenna diversity from ROM. */
reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL);
reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0);
reg = RW(reg, AR9285_PHY_ANT_DIV_CTL,
(modal->ob_234 >> 12) & 0x1);
reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF,
(modal->db1_234 >> 12) & 0x3);
reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF,
(modal->db1_234 >> 14) & 0x3);
reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB,
(modal->ob_234 >> 13) & 0x1);
reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB,
(modal->ob_234 >> 14) & 0x1);
AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg);
reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); /* Flush. */
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
if (modal->ob_234 & (1 << 15))
reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
else
reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
reg = AR_READ(sc, AR_PHY_CCK_DETECT); /* Flush. */
}
void
ar9380_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
const struct ar9380_eeprom *eep = sc->eep;
const struct ar9380_modal_eep_header *modal;
uint8_t db, margin, ant_div_ctrl;
uint32_t reg;
int i, maxchains;
if (IEEE80211_IS_CHAN_2GHZ(c))
modal = &eep->modalHeader2G;
else
modal = &eep->modalHeader5G;
/* Apply XPA bias level. */
if (AR_SREV_9485(sc)) {
reg = AR_READ(sc, AR9485_PHY_65NM_CH0_TOP2);
reg = RW(reg, AR9485_PHY_65NM_CH0_TOP2_XPABIASLVL,
modal->xpaBiasLvl);
AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg);
} else {
reg = AR_READ(sc, AR_PHY_65NM_CH0_TOP);
reg = RW(reg, AR_PHY_65NM_CH0_TOP_XPABIASLVL,
modal->xpaBiasLvl & 0x3);
AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg);
reg = AR_READ(sc, AR_PHY_65NM_CH0_THERM);
reg = RW(reg, AR_PHY_65NM_CH0_THERM_XPABIASLVL_MSB,
modal->xpaBiasLvl >> 2);
reg |= AR_PHY_65NM_CH0_THERM_XPASHORT2GND;
AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg);
}
/* Apply antenna control. */
reg = AR_READ(sc, AR_PHY_SWITCH_COM);
reg = RW(reg, AR_SWITCH_TABLE_COM_ALL, modal->antCtrlCommon);
AR_WRITE(sc, AR_PHY_SWITCH_COM, reg);
reg = AR_READ(sc, AR_PHY_SWITCH_COM_2);
reg = RW(reg, AR_SWITCH_TABLE_COM_2_ALL, modal->antCtrlCommon2);
AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg);
maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS;
for (i = 0; i < maxchains; i++) {
reg = AR_READ(sc, AR_PHY_SWITCH_CHAIN(i));
reg = RW(reg, AR_SWITCH_TABLE_ALL, modal->antCtrlChain[i]);
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg);
}
if (AR_SREV_9485(sc)) {
ant_div_ctrl = eep->base_ext1.ant_div_control;
reg = AR_READ(sc, AR_PHY_MC_GAIN_CTRL);
reg = RW(reg, AR_PHY_MC_GAIN_CTRL_ANT_DIV_CTRL_ALL,
MS(ant_div_ctrl, AR_EEP_ANT_DIV_CTRL_ALL));
if (ant_div_ctrl & AR_EEP_ANT_DIV_CTRL_ANT_DIV)
reg |= AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV;
else
reg &= ~AR_PHY_MC_GAIN_CTRL_ENABLE_ANT_DIV;
AR_WRITE(sc, AR_PHY_MC_GAIN_CTRL, reg);
reg = AR_READ(sc, AR_PHY_CCK_DETECT);
if (ant_div_ctrl & AR_EEP_ANT_DIV_CTRL_FAST_DIV)
reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
else
reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
}
if (eep->baseEepHeader.miscConfiguration & AR_EEP_DRIVE_STRENGTH) {
/* Apply drive strength. */
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS1);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_0, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_1, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_2, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_3, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_4, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS1_5, 5);
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS1, reg);
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS2);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_0, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_1, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_2, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_3, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_4, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_5, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_6, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_7, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS2_8, 5);
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS2, reg);
reg = AR_READ(sc, AR_PHY_65NM_CH0_BIAS4);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_0, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_1, 5);
reg = RW(reg, AR_PHY_65NM_CH0_BIAS4_2, 5);
AR_WRITE(sc, AR_PHY_65NM_CH0_BIAS4, reg);
}
/* Apply attenuation settings. */
maxchains = AR_SREV_9485(sc) ? 1 : AR9380_MAX_CHAINS;
for (i = 0; i < maxchains; i++) {
if (IEEE80211_IS_CHAN_5GHZ(c) &&
eep->base_ext2.xatten1DBLow[i] != 0) {
if (c->ic_freq <= 5500) {
db = athn_interpolate(c->ic_freq,
5180, eep->base_ext2.xatten1DBLow[i],
5500, modal->xatten1DB[i]);
} else {
db = athn_interpolate(c->ic_freq,
5500, modal->xatten1DB[i],
5785, eep->base_ext2.xatten1DBHigh[i]);
}
} else
db = modal->xatten1DB[i];
if (IEEE80211_IS_CHAN_5GHZ(c) &&
eep->base_ext2.xatten1MarginLow[i] != 0) {
if (c->ic_freq <= 5500) {
margin = athn_interpolate(c->ic_freq,
5180, eep->base_ext2.xatten1MarginLow[i],
5500, modal->xatten1Margin[i]);
} else {
margin = athn_interpolate(c->ic_freq,
5500, modal->xatten1Margin[i],
5785, eep->base_ext2.xatten1MarginHigh[i]);
}
} else
margin = modal->xatten1Margin[i];
reg = AR_READ(sc, AR_PHY_EXT_ATTEN_CTL(i));
reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, db);
reg = RW(reg, AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, margin);
AR_WRITE(sc, AR_PHY_EXT_ATTEN_CTL(i), reg);
}
/* Initialize switching regulator. */
if (AR_SREV_9485(sc))
ar9485_init_swreg(sc);
else
ar9485_init_swreg(sc);
/* Apply tuning capabilities. */
if (AR_SREV_9485(sc) &&
(eep->baseEepHeader.featureEnable & AR_EEP_TUNING_CAPS)) {
reg = AR_READ(sc, AR9485_PHY_CH0_XTAL);
reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPINDAC,
eep->baseEepHeader.params_for_tuning_caps[0]);
reg = RW(reg, AR9485_PHY_CH0_XTAL_CAPOUTDAC,
eep->baseEepHeader.params_for_tuning_caps[0]);
AR_WRITE(sc, AR9485_PHY_CH0_XTAL, reg);
}
AR_WRITE_BARRIER(sc);
}
void
ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
const struct ar5416_eeprom *eep = sc->eep;
const struct ar5416_modal_eep_header *modal;
uint32_t reg, offset;
uint8_t txRxAtten;
int i;
modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
for (i = 0; i < AR9280_MAX_CHAINS; i++) {
if (sc->rxchainmask == 0x5 || sc->txchainmask == 0x5)
offset = chainoffset[i];
else
offset = i * 0x1000;
AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
modal->antCtrlChain[i]);
reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
modal->iqCalICh[i]);
reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
modal->iqCalQCh[i]);
AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
if (sc->eep_rev >= AR_EEP_MINOR_VER_3) {
reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
modal->bswMargin[i]);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
modal->bswAtten[i]);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
modal->xatten2Margin[i]);
reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
modal->xatten2Db[i]);
AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
}
if (sc->eep_rev >= AR_EEP_MINOR_VER_3)
txRxAtten = modal->txRxAttenCh[i];
else /* Workaround for ROM versions < 14.3. */
txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44;
reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
txRxAtten);
reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
modal->rxTxMarginCh[i]);
AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
}
if (IEEE80211_IS_CHAN_2GHZ(c)) {
reg = AR_READ(sc, AR_AN_RF2G1_CH0);
reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_AN_RF2G1_CH1);
reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
} else {
reg = AR_READ(sc, AR_AN_RF5G1_CH0);
reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_AN_RF5G1_CH1);
reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
}
reg = AR_READ(sc, AR_AN_TOP2);
if ((sc->flags & ATHN_FLAG_USB) && IEEE80211_IS_CHAN_5GHZ(c)) {
/*
* Hardcode the output voltage of x-PA bias LDO to the
* lowest value for UB94 such that the card doesn't get
* too hot.
*/
reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);
} else
reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
if (modal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)
reg |= AR_AN_TOP2_LOCALBIAS;
else
reg &= ~AR_AN_TOP2_LOCALBIAS;
AR_WRITE(sc, AR_AN_TOP2, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_PHY_XPA_CFG);
if (modal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)
reg |= AR_PHY_FORCE_XPA_CFG;
else
reg &= ~AR_PHY_FORCE_XPA_CFG;
AR_WRITE(sc, AR_PHY_XPA_CFG, reg);
reg = AR_READ(sc, AR_PHY_SETTLING);
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
reg = AR_READ(sc, AR_PHY_RF_CTL3);
reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
reg = AR_READ(sc, AR_PHY_CCA(0));
reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
AR_WRITE(sc, AR_PHY_CCA(0), reg);
reg = AR_READ(sc, AR_PHY_EXT_CCA0);
reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
if (sc->eep_rev >= AR_EEP_MINOR_VER_2) {
reg = AR_READ(sc, AR_PHY_RF_CTL2);
reg = RW(reg, AR_PHY_TX_END_DATA_START,
modal->txFrameToDataStart);
reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
}
#ifndef IEEE80211_NO_HT
if (sc->eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
/* Overwrite switch settling with HT-40 value. */
reg = AR_READ(sc, AR_PHY_SETTLING);
reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
AR_WRITE(sc, AR_PHY_SETTLING, reg);
}
#endif
if (sc->eep_rev >= AR_EEP_MINOR_VER_19) {
reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
MS(modal->miscBits, AR5416_EEP_MISC_TX_DAC_SCALE_CCK));
AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
}
if (AR_SREV_9280_20(sc) &&
sc->eep_rev >= AR_EEP_MINOR_VER_20) {
reg = AR_READ(sc, AR_AN_TOP1);
if (eep->baseEepHeader.dacLpMode &&
(IEEE80211_IS_CHAN_2GHZ(c) ||
!eep->baseEepHeader.dacHiPwrMode_5G))
reg |= AR_AN_TOP1_DACLPMODE;
else
reg &= ~AR_AN_TOP1_DACLPMODE;
AR_WRITE(sc, AR_AN_TOP1, reg);
AR_WRITE_BARRIER(sc);
DELAY(100);
reg = AR_READ(sc, AR_PHY_FRAME_CTL);
reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,
MS(modal->miscBits, AR5416_EEP_MISC_TX_CLIP));
AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);
reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);
reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,
eep->baseEepHeader.desiredScaleCCK);
AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
}
AR_WRITE_BARRIER(sc);
}
int
ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
uint32_t phy, reg, ndiv = 0;
uint32_t freq = c->ic_freq;
phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;
if (IEEE80211_IS_CHAN_2GHZ(c)) {
phy |= (freq << 16) / 15;
phy |= AR9280_BMODE | AR9280_FRACMODE;
if (AR_SREV_9287_11_OR_LATER(sc)) {
/* NB: Magic values from the Linux driver. */
if (freq == 2484) { /* Channel 14. */
/* Japanese regulatory requirements. */
AR_WRITE(sc, AR_PHY(637), 0x00000000);
AR_WRITE(sc, AR_PHY(638), 0xefff0301);
AR_WRITE(sc, AR_PHY(639), 0xca9228ee);
} else {
AR_WRITE(sc, AR_PHY(637), 0x00fffeff);
AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff);
AR_WRITE(sc, AR_PHY(639), 0xb79f6427);
}
} else {
reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
if (freq == 2484) /* Channel 14. */
reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
else
reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
}
} else {
if (AR_SREV_9285_10_OR_LATER(sc) ||
sc->eep_rev < AR_EEP_MINOR_VER_22 ||
!((struct ar5416_base_eep_header *)sc->eep)->frac_n_5g) {
if ((freq % 20) == 0) {
ndiv = (freq * 3) / 60;
phy |= SM(AR9280_AMODE_REFSEL, 3);
} else if ((freq % 10) == 0) {
ndiv = (freq * 6) / 60;
phy |= SM(AR9280_AMODE_REFSEL, 2);
}
}
if (ndiv != 0) {
phy |= (ndiv & 0x1ff) << 17;
phy |= (ndiv & ~0x1ff) * 2;
} else {
phy |= (freq << 15) / 15;
phy |= AR9280_FRACMODE;
reg = AR_READ(sc, AR_AN_SYNTH9);
reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
AR_WRITE(sc, AR_AN_SYNTH9, reg);
}
}
AR_WRITE_BARRIER(sc);
DPRINTFN(4, ("AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy));
AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
AR_WRITE_BARRIER(sc);
return (0);
}
void
ar9380_spur_mitigate_ofdm(struct athn_softc *sc, struct ieee80211_channel *c,
struct ieee80211_channel *extc)
{
const struct ar9380_eeprom *eep = sc->eep;
const uint8_t *spurchans;
uint32_t reg;
int idx, spur_delta_phase, spur_off, range, i;
int freq, spur, spur_freq_sd, spur_subchannel_sd;
if (IEEE80211_IS_CHAN_2GHZ(c))
spurchans = eep->modalHeader2G.spurChans;
else
spurchans = eep->modalHeader5G.spurChans;
if (spurchans[0] == 0)
return;
/* Disable OFDM spur mitigation. */
AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
reg = AR_READ(sc, AR_PHY_TIMING11);
reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
reg &= ~AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
AR_WRITE(sc, AR_PHY_TIMING11, reg);
AR_CLRBITS(sc, AR_PHY_SFCORR_EXT,
AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD);
AR_CLRBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
reg = AR_READ(sc, AR_PHY_SPUR_REG);
reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
reg &= ~AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
reg &= ~AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
reg &= ~AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
AR_WRITE_BARRIER(sc);
freq = c->ic_freq;
#ifndef IEEE80211_NO_HT
if (extc != NULL) {
range = 19; /* +/- 19MHz range. */
if (AR_READ(sc, AR_PHY_GEN_CTRL) & AR_PHY_GC_DYN2040_PRI_CH)
freq += 10;
else
freq -= 10;
} else
#endif
range = 10; /* +/- 10MHz range. */
for (i = 0; i < AR9380_EEPROM_MODAL_SPURS; i++) {
spur = spurchans[i];
if (spur == 0)
return;
/* Convert to frequency. */
if (IEEE80211_IS_CHAN_2GHZ(c))
spur = 2300 + spur;
else
spur = 4900 + (spur * 5);
spur -= freq;
if (abs(spur) < range)
break;
}
if (i == AR9380_EEPROM_MODAL_SPURS)
return;
/* Enable OFDM spur mitigation. */
#ifndef IEEE80211_NO_HT
if (extc != NULL) {
spur_delta_phase = (spur * 131072) / 5;
reg = AR_READ(sc, AR_PHY_GEN_CTRL);
if (spur < 0) {
spur_subchannel_sd =
(reg & AR_PHY_GC_DYN2040_PRI_CH) == 0;
spur_off = spur + 10;
} else {
spur_subchannel_sd =
(reg & AR_PHY_GC_DYN2040_PRI_CH) != 0;
spur_off = spur - 10;
}
} else
#endif
{
spur_delta_phase = (spur * 262144) / 5;
spur_subchannel_sd = 0;
spur_off = spur;
}
spur_freq_sd = (spur_off * 512) / 11;
AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER);
reg = AR_READ(sc, AR_PHY_TIMING11);
reg = RW(reg, AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
reg = RW(reg, AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC;
reg |= AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR;
AR_WRITE(sc, AR_PHY_TIMING11, reg);
reg = AR_READ(sc, AR_PHY_SFCORR_EXT);
if (spur_subchannel_sd)
reg |= AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
else
reg &= ~AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD;
AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
AR_SETBITS(sc, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI);
reg = AR_READ(sc, AR_PHY_SPUR_REG);
reg = RW(reg, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
reg = RW(reg, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
reg |= AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI;
if (AR_READ(sc, AR_PHY_MODE) & AR_PHY_MODE_DYNAMIC)
reg |= AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT;
reg |= AR_PHY_SPUR_REG_ENABLE_MASK_PPM;
AR_WRITE(sc, AR_PHY_SPUR_REG, reg);
idx = (spur * 16) / 5;
if (idx < 0)
idx--;
/* Write pilot mask. */
AR_SETBITS(sc, AR_PHY_TIMING4,
AR_PHY_TIMING4_ENABLE_PILOT_MASK |
AR_PHY_TIMING4_ENABLE_CHAN_MASK);
reg = AR_READ(sc, AR_PHY_PILOT_SPUR_MASK);
reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0x0c);
AR_WRITE(sc, AR_PHY_PILOT_SPUR_MASK, reg);
reg = AR_READ(sc, AR_PHY_SPUR_MASK_A);
reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
AR_WRITE(sc, AR_PHY_SPUR_MASK_A, reg);
reg = AR_READ(sc, AR_PHY_CHAN_SPUR_MASK);
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, idx);
reg = RW(reg, AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0x0c);
AR_WRITE(sc, AR_PHY_CHAN_SPUR_MASK, reg);
AR_WRITE_BARRIER(sc);
}