/**
Reads a 32-bit PCI configuration register.
Reads and returns the 32-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are
serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@return The read value from the PCI configuration register.
**/
UINT32
EFIAPI
PciExpressRead32 (
IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);
}
/**
Registers a PCI device so PCI configuration registers may be accessed after
SetVirtualAddressMap().
Registers the PCI device specified by Address so all the PCI configuration registers
associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
If Address > 0x0FFFFFFF, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@retval RETURN_SUCCESS The PCI device was registered for runtime access.
@retval RETURN_UNSUPPORTED An attempt was made to call this function
after ExitBootServices().
@retval RETURN_UNSUPPORTED The resources required to access the PCI device
at runtime could not be mapped.
@retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
complete the registration.
**/
RETURN_STATUS
EFIAPI
PciRegisterForRuntimeAccess (
IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return RETURN_UNSUPPORTED;
}
/**
Reads a 32-bit PCI configuration register.
Reads and returns the 32-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are
serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@return The read value from the PCI configuration register.
**/
UINT32
EFIAPI
PciRead32 (
IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
return PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);
}
/**
Reads a 16-bit PCI configuration register.
Reads and returns the 16-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are
serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@return The read value from the PCI configuration register.
**/
UINT16
EFIAPI
PciRead16 (
IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
return (UINT16) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);
}
/**
Reads a 32-bit PCI configuration register.
Reads and returns the 32-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are
serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@return The read value from the PCI configuration register.
**/
UINT32
EFIAPI
PciRead32 (
IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
return DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint32);
}
/**
Writes an 8-bit PCI configuration register.
Writes the 8-bit PCI configuration register specified by Address with the
value specified by Value. Value is returned. This function must guarantee
that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
**/
UINT8
EFIAPI
PciExpressWrite8 (
IN UINTN Address,
IN UINT8 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);
}
/**
Reads an 8-bit PCI configuration register.
Reads and returns the 8-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are
serialized.
If Address > 0x0FFFFFFF, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@return The read value from the PCI configuration register.
**/
UINT8
EFIAPI
PciRead8 (
IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return (UINT8) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);
}
/**
Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
value.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData, and
writes the result to the 32-bit PCI configuration register specified by
Address. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are
serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@param AndData The value to AND with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
PciExpressAnd32 (
IN UINTN Address,
IN UINT32 AndData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);
}
/**
Reads an 8-bit PCI configuration register.
Reads and returns the 8-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are
serialized.
If Address > 0x0FFFFFFF, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@return The read value from the PCI configuration register.
**/
UINT8
EFIAPI
PciRead8 (
IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return (UINT8) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);
}
/**
Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
a 16-bit value.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise inclusive OR between the read result and the value specified by
OrData, and writes the result to the 16-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
PciExpressOr16 (
IN UINTN Address,
IN UINT16 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);
}
/**
Reads a 16-bit PCI configuration register.
Reads and returns the 16-bit PCI configuration register specified by Address.
This function must guarantee that all PCI read and write operations are
serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@return The read value from the PCI configuration register.
**/
UINT16
EFIAPI
PciRead16 (
IN UINTN Address
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
return (UINT16) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);
}
/**
Writes a 16-bit PCI configuration register.
Writes the 16-bit PCI configuration register specified by Address with the
value specified by Value. Value is returned. This function must guarantee
that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
**/
UINT16
EFIAPI
PciWrite16 (
IN UINTN Address,
IN UINT16 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
return (UINT16) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);
}
/**
Writes a 32-bit PCI configuration register.
Writes the 32-bit PCI configuration register specified by Address with the
value specified by Value. Value is returned. This function must guarantee
that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
**/
UINT32
EFIAPI
PciWrite32 (
IN UINTN Address,
IN UINT32 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
return PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);
}
/**
Writes a 32-bit PCI configuration register.
Writes the 32-bit PCI configuration register specified by Address with the
value specified by Value. Value is returned. This function must guarantee
that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
**/
UINT32
EFIAPI
PciWrite32 (
IN UINTN Address,
IN UINT32 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 3);
return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Value);
}
/**
Writes an 8-bit PCI configuration register.
Writes the 8-bit PCI configuration register specified by Address with the
value specified by Value. Value is returned. This function must guarantee
that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
**/
UINT8
EFIAPI
PciWrite8 (
IN UINTN Address,
IN UINT8 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return (UINT8) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);
}
/**
Writes a 16-bit PCI configuration register.
Writes the 16-bit PCI configuration register specified by Address with the
value specified by Value. Value is returned. This function must guarantee
that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
**/
UINT16
EFIAPI
PciWrite16 (
IN UINTN Address,
IN UINT16 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 1);
return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Value);
}
/**
Writes an 8-bit PCI configuration register.
Writes the 8-bit PCI configuration register specified by Address with the
value specified by Value. Value is returned. This function must guarantee
that all PCI read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
@param Address The address that encodes the PCI Bus, Device, Function and
Register.
@param Value The value to write.
@return The value written to the PCI configuration register.
**/
UINT8
EFIAPI
PciWrite8 (
IN UINTN Address,
IN UINT8 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address, 0);
return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Value);
}
/**
Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
value, followed a bitwise inclusive OR with another 8-bit value.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData,
performs a bitwise inclusive OR between the result of the AND operation and
the value specified by OrData, and writes the result to the 8-bit PCI
configuration register specified by Address. The value written to the PCI
configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized.
If Address > 0x0FFFFFFF, then ASSERT().
@param Address Address that encodes the PCI Bus, Device, Function and
Register.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register.
**/
UINT8
EFIAPI
PciExpressAndThenOr8 (
IN UINTN Address,
IN UINT8 AndData,
IN UINT8 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioAndThenOr8 (
(UINTN) GetPciExpressBaseAddress () + Address,
AndData,
OrData
);
}
/**
Reads a bit field of a PCI configuration register.
Reads the bit field in a 32-bit PCI configuration register. The bit field is
specified by the StartBit and the EndBit. The value of the bit field is
returned.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to read.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@return The value of the bit field read from the PCI configuration register.
**/
UINT32
EFIAPI
PciExpressBitFieldRead32 (
IN UINTN Address,
IN UINTN StartBit,
IN UINTN EndBit
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioBitFieldRead32 (
(UINTN) GetPciExpressBaseAddress () + Address,
StartBit,
EndBit
);
}
/**
Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
AND, and writes the result back to the bit field in the 16-bit register.
Reads the 16-bit PCI configuration register specified by Address, performs a
bitwise AND between the read result and the value specified by AndData, and
writes the result to the 16-bit PCI configuration register specified by
Address. The value written to the PCI configuration register is returned.
This function must guarantee that all PCI read and write operations are
serialized. Extra left bits in AndData are stripped.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param AndData The value to AND with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
PciExpressBitFieldAnd16 (
IN UINTN Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 AndData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioBitFieldAnd16 (
(UINTN) GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
AndData
);
}
/**
Writes a bit field to a PCI configuration register.
Writes Value to the bit field of the PCI configuration register. The bit
field is specified by the StartBit and the EndBit. All other bits in the
destination PCI configuration register are preserved. The new value of the
16-bit register is returned.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 16-bit boundary, then ASSERT().
If StartBit is greater than 15, then ASSERT().
If EndBit is greater than 15, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..15.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..15.
@param Value New value of the bit field.
@return The value written back to the PCI configuration register.
**/
UINT16
EFIAPI
PciExpressBitFieldWrite16 (
IN UINTN Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT16 Value
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioBitFieldWrite16 (
(UINTN) GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
Value
);
}
/**
Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
writes the result back to the bit field in the 8-bit port.
Reads the 8-bit PCI configuration register specified by Address, performs a
bitwise inclusive OR between the read result and the value specified by
OrData, and writes the result to the 8-bit PCI configuration register
specified by Address. The value written to the PCI configuration register is
returned. This function must guarantee that all PCI read and write operations
are serialized. Extra left bits in OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT().
If StartBit is greater than 7, then ASSERT().
If EndBit is greater than 7, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..7.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..7.
@param OrData The value to OR with the PCI configuration register.
@return The value written back to the PCI configuration register.
**/
UINT8
EFIAPI
PciExpressBitFieldOr8 (
IN UINTN Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT8 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioBitFieldOr8 (
(UINTN) GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
OrData
);
}
/**
Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
bitwise inclusive OR, and writes the result back to the bit field in the
32-bit port.
Reads the 32-bit PCI configuration register specified by Address, performs a
bitwise AND followed by a bitwise inclusive OR between the read result and
the value specified by AndData, and writes the result to the 32-bit PCI
configuration register specified by Address. The value written to the PCI
configuration register is returned. This function must guarantee that all PCI
read and write operations are serialized. Extra left bits in both AndData and
OrData are stripped.
If Address > 0x0FFFFFFF, then ASSERT().
If Address is not aligned on a 32-bit boundary, then ASSERT().
If StartBit is greater than 31, then ASSERT().
If EndBit is greater than 31, then ASSERT().
If EndBit is less than StartBit, then ASSERT().
@param Address PCI configuration register to write.
@param StartBit The ordinal of the least significant bit in the bit field.
Range 0..31.
@param EndBit The ordinal of the most significant bit in the bit field.
Range 0..31.
@param AndData The value to AND with the PCI configuration register.
@param OrData The value to OR with the result of the AND operation.
@return The value written back to the PCI configuration register.
**/
UINT32
EFIAPI
PciExpressBitFieldAndThenOr32 (
IN UINTN Address,
IN UINTN StartBit,
IN UINTN EndBit,
IN UINT32 AndData,
IN UINT32 OrData
)
{
ASSERT_INVALID_PCI_ADDRESS (Address);
return MmioBitFieldAndThenOr32 (
(UINTN) GetPciExpressBaseAddress () + Address,
StartBit,
EndBit,
AndData,
OrData
);
}
/**
Copies the data in a caller supplied buffer to a specified range of PCI
configuration space.
Writes the range of PCI configuration registers specified by StartAddress and
Size from the buffer specified by Buffer. This function only allows the PCI
configuration registers from a single PCI function to be written. Size is
returned. When possible 32-bit PCI configuration write cycles are used to
write from StartAdress to StartAddress + Size. Due to alignment restrictions,
8-bit and 16-bit PCI configuration write cycles may be used at the beginning
and the end of the range.
If StartAddress > 0x0FFFFFFF, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
@param StartAddress Starting address that encodes the PCI Bus, Device,
Function and Register.
@param Size Size in bytes of the transfer.
@param Buffer Pointer to a buffer containing the data to write.
@return Size
**/
UINTN
EFIAPI
PciExpressWriteBuffer (
IN UINTN StartAddress,
IN UINTN Size,
IN VOID *Buffer
)
{
UINTN ReturnValue;
ASSERT_INVALID_PCI_ADDRESS (StartAddress);
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
if (Size == 0) {
return 0;
}
ASSERT (Buffer != NULL);
//
// Save Size for return
//
ReturnValue = Size;
if ((StartAddress & 1) != 0) {
//
// Write a byte if StartAddress is byte aligned
//
PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
StartAddress += sizeof (UINT8);
Size -= sizeof (UINT8);
Buffer = (UINT8*)Buffer + 1;
}
if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
//
// Write a word if StartAddress is word aligned
//
PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);
StartAddress += sizeof (UINT16);
Size -= sizeof (UINT16);
Buffer = (UINT16*)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
//
// Write as many double words as possible
//
PciExpressWrite32 (StartAddress, *(UINT32*)Buffer);
StartAddress += sizeof (UINT32);
Size -= sizeof (UINT32);
Buffer = (UINT32*)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
//
// Write the last remaining word if exist
//
PciExpressWrite16 (StartAddress, *(UINT16*)Buffer);
StartAddress += sizeof (UINT16);
Size -= sizeof (UINT16);
Buffer = (UINT16*)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
//
// Write the last remaining byte if exist
//
PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);
}
return ReturnValue;
}
/**
Reads a range of PCI configuration registers into a caller supplied buffer.
Reads the range of PCI configuration registers specified by StartAddress and
Size into the buffer specified by Buffer. This function only allows the PCI
configuration registers from a single PCI function to be read. Size is
returned. When possible 32-bit PCI configuration read cycles are used to read
from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
and 16-bit PCI configuration read cycles may be used at the beginning and the
end of the range.
If StartAddress > 0x0FFFFFFF, then ASSERT().
If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
If Size > 0 and Buffer is NULL, then ASSERT().
@param StartAddress The starting address that encodes the PCI Bus, Device,
Function and Register.
@param Size The size in bytes of the transfer.
@param Buffer The pointer to a buffer receiving the data read.
@return Size
**/
UINTN
EFIAPI
PciReadBuffer (
IN UINTN StartAddress,
IN UINTN Size,
OUT VOID *Buffer
)
{
UINTN ReturnValue;
ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
if (Size == 0) {
return Size;
}
ASSERT (Buffer != NULL);
//
// Save Size for return
//
ReturnValue = Size;
if ((StartAddress & BIT0) != 0) {
//
// Read a byte if StartAddress is byte aligned
//
*(volatile UINT8 *)Buffer = PciRead8 (StartAddress);
StartAddress += sizeof (UINT8);
Size -= sizeof (UINT8);
Buffer = (UINT8*)Buffer + 1;
}
if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
//
// Read a word if StartAddress is word aligned
//
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));
StartAddress += sizeof (UINT16);
Size -= sizeof (UINT16);
Buffer = (UINT16*)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
//
// Read as many double words as possible
//
WriteUnaligned32 (Buffer, PciRead32 (StartAddress));
StartAddress += sizeof (UINT32);
Size -= sizeof (UINT32);
Buffer = (UINT32*)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
//
// Read the last remaining word if exist
//
WriteUnaligned16 (Buffer, PciRead16 (StartAddress));
StartAddress += sizeof (UINT16);
Size -= sizeof (UINT16);
Buffer = (UINT16*)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
//
// Read the last remaining byte if exist
//
*(volatile UINT8 *)Buffer = PciRead8 (StartAddress);
}
return ReturnValue;
}
