static int ek_special_hw_init(void)
{
/*
* For on the sam9m10g45ek board, the chip wm9711 stay in the test mode,
* so it need do some action to exit mode.
*/
const struct pio_desc wm9711_pins[] = {
{"AC97TX", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_OUTPUT},
{"AC97FS", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(wm9711_pins);
writel((1 << AT91C_ID_PIOD_E), PMC_PCER + AT91C_BASE_PMC);
/*
* Disable pull-up on:
* RXDV(PA15) => PHY normal mode (not Test mode)
* ERX0(PA12) => PHY ADDR0
* ERX1(PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel((0x01 << 12) | (0x01 << 13) | (0x01 << 15), AT91C_BASE_PIOA + PIO_PPUDR(0));
return 0;
}
void at91_spi0_hw_init(void)
{
#if defined(CONFIG_SPI_BUS0)
#if defined(CONFIG_SPI0_IOSET_1)
const struct pio_desc spi_pins[] = {
{"SPI0_SPCK", AT91C_PIN_PA(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPI0_MOSI", AT91C_PIN_PA(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPI0_MISO", AT91C_PIN_PA(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPI0_NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
#elif defined(CONFIG_SPI0_IOSET_2)
const struct pio_desc spi_pins[] = {
{"SPI0_SPCK", AT91C_PIN_PB(1), 0, PIO_DEFAULT, PIO_PERIPH_C},
{"SPI0_MOSI", AT91C_PIN_PB(0), 0, PIO_DEFAULT, PIO_PERIPH_C},
{"SPI0_MISO", AT91C_PIN_PA(31), 0, PIO_DEFAULT, PIO_PERIPH_C},
{"SPI0_NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
#else
#error "No SPI0 IOSET defined"
#endif
#elif defined(CONFIG_SPI_BUS1)
#if defined(CONFIG_SPI1_IOSET_1)
const struct pio_desc spi_pins[] = {
{"SPI1_SPCK", AT91C_PIN_PC(1), 0, PIO_DEFAULT, PIO_PERIPH_D},
{"SPI1_MOSI", AT91C_PIN_PC(2), 0, PIO_DEFAULT, PIO_PERIPH_D},
{"SPI1_MISO", AT91C_PIN_PC(3), 0, PIO_DEFAULT, PIO_PERIPH_D},
{"SPI1_NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
#elif defined(CONFIG_SPI1_IOSET_2)
const struct pio_desc spi_pins[] = {
{"SPI1_SPCK", AT91C_PIN_PA(22), 0, PIO_DEFAULT, PIO_PERIPH_D},
{"SPI1_MOSI", AT91C_PIN_PA(23), 0, PIO_DEFAULT, PIO_PERIPH_D},
{"SPI1_MISO", AT91C_PIN_PA(24), 0, PIO_DEFAULT, PIO_PERIPH_D},
{"SPI1_NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
#elif defined(CONFIG_SPI1_IOSET_3)
const struct pio_desc spi_pins[] = {
{"SPI1_SPCK", AT91C_PIN_PD(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPI1_MOSI", AT91C_PIN_PD(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPI1_MISO", AT91C_PIN_PD(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPI1_NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
#else
#error "No SPI1 IOSET defined"
#endif
#else
#error "No SPI Bus defined"
#endif
pio_configure(spi_pins);
pmc_sam9x5_enable_periph_clk(CONFIG_SYS_ID_SPI);
}
void at91_mci0_hw_init(void)
{
const struct pio_desc mci_pins[] = {
{"MCCK", AT91C_PIN_PD(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCCDA", AT91C_PIN_PD(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA0", AT91C_PIN_PD(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA1", AT91C_PIN_PD(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA2", AT91C_PIN_PD(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA3", AT91C_PIN_PD(4), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA4", AT91C_PIN_PD(5), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA5", AT91C_PIN_PD(6), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA6", AT91C_PIN_PD(7), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA7", AT91C_PIN_PD(8), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the PIO controller */
pmc_enable_periph_clock(AT91C_ID_HSMCI0);
pio_configure(mci_pins);
/* Enable the clock */
pmc_enable_periph_clock(AT91C_ID_HSMCI0);
/* Set of name function pointer */
sdcard_set_of_name = &sdcard_set_of_name_board;
}
static void at91_dbgu_hw_init(void)
{
const struct pio_desc dbgu_pins[] = {
{"URXD1", AT91C_PIN_PD(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"UTXD1", AT91C_PIN_PD(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(dbgu_pins);
pmc_sam9x5_enable_periph_clk(AT91C_ID_UART1);
}
void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure nand pins */
const struct pio_desc nand_pins_lo[] = {
{"NANDOE", AT91C_PIN_PD(0), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PD(1), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", AT91C_PIN_PD(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PD(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
reg &= ~AT91C_EBI_NFD0_ON_D16; /* nandflash connect to D0~D15 */
reg |= AT91C_EBI_DRV; /* according to IAR verification package */
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(3)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(5)
| AT91C_SMC_NRDPULSE_(4)
| AT91C_SMC_NCS_RDPULSE_(6)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(8)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_8
| AT91_SMC_TDF_(1)),
AT91C_BASE_SMC + SMC_CTRL3);
/* Configure the nand controller pins*/
writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
pio_configure(nand_pins_lo);
}
unsigned int at91_twi1_hw_init(void)
{
const struct pio_desc twi_pins[] = {
{"TWD1", AT91C_PIN_PD(4), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TWCK1", AT91C_PIN_PD(5), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(twi_pins);
pmc_sam9x5_enable_periph_clk(AT91C_ID_TWI1);
return AT91C_BASE_TWI1;
}
unsigned int at91_twi0_hw_init(void)
{
unsigned int base_addr = AT91C_BASE_TWI0;
const struct pio_desc twi_pins[] = {
{"TWD0", AT91C_PIN_PD(21), 0, PIO_DEFAULT, PIO_PERIPH_B},
{"TWCK0", AT91C_PIN_PD(22), 0, PIO_DEFAULT, PIO_PERIPH_B},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(twi_pins);
pmc_sam9x5_enable_periph_clk(AT91C_ID_TWI0);
return base_addr;
}
void at91_spi0_hw_init(void)
{
const struct pio_desc spi0_pins[] = {
{"MISO", AT91C_PIN_PD(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MOSI", AT91C_PIN_PD(11), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPCK", AT91C_PIN_PD(12), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_PIOD);
pio_configure(spi0_pins);
pmc_enable_periph_clock(AT91C_ID_SPI0);
}
static int ek_special_hw_init(void)
{
unsigned long rstc;
unsigned long rst_key = (0xA5 << 24);
/*
* For on the sam9m10g45ek board, the chip wm9711 stay in the test mode,
* so it need do some action to exit mode.
*/
const struct pio_desc wm9711_pins[] = {
{"AC97TX", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_OUTPUT},
{"AC97FS", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(wm9711_pins);
writel((1 << AT91C_ID_PIOD_E), PMC_PCER + AT91C_BASE_PMC);
/*
* Disable pull-up on:
* RXDV(PA15) => PHY normal mode (not Test mode)
* ERX0(PA12) => PHY ADDR0
* ERX1(PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel((0x01 << 12) | (0x01 << 13) | (0x01 << 15), AT91C_BASE_PIOA + PIO_PPUDR(0));
rstc = at91_sys_read(AT91C_BASE_RSTC + RSTC_RMR);
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91C_BASE_RSTC + RSTC_RMR, rst_key |
(AT91C_RSTC_ERSTL & (0x0D << 8)) |
AT91C_RSTC_URSTEN);
at91_sys_write(AT91C_BASE_RSTC + RSTC_RCR, rst_key | AT91C_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91C_BASE_RSTC + RSTC_RSR) & AT91C_RSTC_NRSTL));
/* Restore NRST value */
at91_sys_write(AT91C_BASE_RSTC + RSTC_RMR, rst_key |
(rstc) |
AT91C_RSTC_URSTEN);
return 0;
}
void at91_spi0_hw_init(void)
{
/* Configure PIN for SPI0 */
const struct pio_desc spi0_pins[] = {
{"MISO", AT91C_PIN_PD(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MOSI", AT91C_PIN_PD(11), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPCK", AT91C_PIN_PD(12), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the PIO controller */
writel((1 << AT91C_ID_PIOD), (PMC_PCER + AT91C_BASE_PMC));
pio_configure(spi0_pins);
/* Enable the clock */
writel((1 << AT91C_ID_SPI0), (PMC_PCER + AT91C_BASE_PMC));
}
void at91_mci0_hw_init(void)
{
const struct pio_desc mci_pins[] = {
{"MCCK", AT91C_PIN_PD(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCCDA", AT91C_PIN_PD(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA0", AT91C_PIN_PD(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA1", AT91C_PIN_PD(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA2", AT91C_PIN_PD(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA3", AT91C_PIN_PD(4), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA4", AT91C_PIN_PD(5), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA5", AT91C_PIN_PD(6), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA6", AT91C_PIN_PD(7), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA7", AT91C_PIN_PD(8), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_HSMCI0);
pio_configure(mci_pins);
pmc_enable_periph_clock(AT91C_ID_HSMCI0);
}
void at91_mci0_hw_init(void)
{
const struct pio_desc mci_pins[] = {
{"MCCK", AT91C_PIN_PD(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCCDA", AT91C_PIN_PD(0), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA0", AT91C_PIN_PD(1), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA1", AT91C_PIN_PD(2), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA2", AT91C_PIN_PD(3), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA3", AT91C_PIN_PD(4), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA4", AT91C_PIN_PD(5), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA5", AT91C_PIN_PD(6), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA6", AT91C_PIN_PD(7), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MCDA7", AT91C_PIN_PD(8), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the PIO controller */
writel((1 << AT91C_ID_PIOD), (PMC_PCER + AT91C_BASE_PMC));
pio_configure(mci_pins);
/* Enable the clock */
writel((1 << AT91C_ID_HSMCI0), (PMC_PCER + AT91C_BASE_PMC));
}
/*------------------------------------------------------------------------------*/
void nandflash_hw_init(void)
{
/*
* Configure PIOs
*/
const struct pio_desc nand_pio[] = {
{"NANDALE", AT91C_PIN_PB(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PB(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDOE", AT91C_PIN_PB(4), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PB(5), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", AT91C_PIN_PB(6), 0, PIO_PULLUP, PIO_OUTPUT},
{"RDY_BSY", AT91C_PIN_PD(17), 0, PIO_PULLUP, PIO_INPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/*
* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface
*/
writel(readl(AT91C_CCFG_EBICSA) | AT91C_EBI_CS3A_SM, AT91C_CCFG_EBICSA);
/*
* Configure SMC CS3
*/
writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP |
AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE |
AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS |
AT91C_SM_TDF), AT91C_BASE_SMC + SMC_CTRL3);
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOD), PMC_PCER + AT91C_BASE_PMC);
pio_setup(nand_pio);
}
void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure Nand PINs */
const struct pio_desc nand_pins_hi[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
const struct pio_desc nand_pins_lo[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
if (get_cm_rev() == 'A')
reg &= ~AT91C_EBI_NFD0_ON_D16;
else
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(2)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(5)
| AT91C_SMC_NRDPULSE_(4)
| AT91C_SMC_NCS_RDPULSE_(6)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(7)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_8
| AT91_SMC_TDF_(1)),
AT91C_BASE_SMC + SMC_CTRL3);
/* Configure the PIO controller */
if (get_cm_rev() == 'A')
pio_configure(nand_pins_lo);
else
pio_configure(nand_pins_hi);
pmc_enable_periph_clock(AT91C_ID_PIOC_D);
}
/*------------------------------------------------------------------------------*/
void nandflash_hw_init(void)
{
unsigned int reg;
/*
* Configure PIOs
*/
const struct pio_desc nand_pio_hi[] = {
{"NANDOE", AT91C_PIN_PD(0), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PD(1), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", AT91C_PIN_PD(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PD(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", AT91C_PIN_PD(4), 0, PIO_PULLUP, PIO_OUTPUT},
{"RDY_BSY", AT91C_PIN_PD(5), 0, PIO_PULLUP, PIO_INPUT},
{"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
const struct pio_desc nand_pio_lo[] = {
{"NANDOE", AT91C_PIN_PD(0), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", AT91C_PIN_PD(1), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", AT91C_PIN_PD(2), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", AT91C_PIN_PD(3), 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", AT91C_PIN_PD(4), 0, PIO_PULLUP, PIO_OUTPUT},
{"RDY_BSY", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_INPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
if (get_cm_rev() == 'A') {
reg &= ~AT91C_EBI_NFD0_ON_D16;
} else {
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
}
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/*
* Configure SMC CS3
*/
writel((AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | AT91C_SM_NRD_SETUP |
AT91C_SM_NCS_RD_SETUP), AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE |
AT91C_SM_NCS_RD_PULSE), AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE |
AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_EIGTH_BITS |
AT91C_SM_TDF), AT91C_BASE_SMC + SMC_CTRL3);
/*
* Configure the PIO controller
*/
writel((1 << AT91C_ID_PIOC_D), (PMC_PCER + AT91C_BASE_PMC));
if (get_cm_rev() == 'A')
pio_setup(nand_pio_lo);
else
pio_setup(nand_pio_hi);
nand_recovery();
}
static void sdramc_hw_init(void)
{
/* Configure sdramc pins */
const struct pio_desc sdramc_pins[] = {
{"D16", AT91C_PIN_PD(16), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D17", AT91C_PIN_PD(17), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D18", AT91C_PIN_PD(18), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D19", AT91C_PIN_PD(19), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D20", AT91C_PIN_PD(20), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D21", AT91C_PIN_PD(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D22", AT91C_PIN_PD(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D23", AT91C_PIN_PD(23), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D24", AT91C_PIN_PD(24), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D25", AT91C_PIN_PD(25), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D26", AT91C_PIN_PD(26), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D27", AT91C_PIN_PD(27), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D28", AT91C_PIN_PD(28), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D29", AT91C_PIN_PD(29), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D30", AT91C_PIN_PD(30), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"D31", AT91C_PIN_PD(31), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *) 0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the SDRAMC PINs */
pmc_enable_periph_clock(AT91C_ID_PIOCDE);
pio_configure(sdramc_pins);
}
