void RESET_TWI()
{
uint8 data = AT91C_BASE_TWI->TWI_RHR;
uint16 status = AT91C_BASE_TWI->TWI_SR;
// Configure TWI in master mode
AT91F_TWI_Configure (AT91C_BASE_TWI);
// Configure TWI PIOs
AT91F_TWI_CfgPIO();
AT91F_PIO_CfgOpendrain(AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA1_TWCK ) |
((unsigned int) AT91C_PA0_TWD ) );
// Configure PMC by enabling TWI clock
AT91F_TWI_CfgPMC ();
// AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1<<AT91C_ID_TWI ) ;
// Set TWI Clock Waveform Generator Register
AT91F_SetTwiClock();
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC,
AT91C_ID_TWI,
TWI_INTERRUPT_LEVEL,
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
( void (*)( void ) )AT91_TWI_ISR_ENTRY);
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TWI);
TWI_TransferStatus = FREE;
}
void TWI_RD_BYTE(void)
{
//Start?
if(AktPosRx == 0)
{
//Nur ein Byte lesen?
if(Len2Receive == 1)
{
//Start und Stopp senden
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START | AT91C_TWI_STOP | AT91C_TWI_MSEN;
}
else
{
//Start senden
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START | AT91C_TWI_MSEN;
}
//Interrupt freigeben
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_TWI, TWI_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, TWI_c_irq_handler);
AT91C_BASE_TWI->TWI_IDR = 0xFFFFFFFF;
AT91C_BASE_TWI->TWI_IER = AT91C_TWI_RXRDY;
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TWI);
}
//Stopp senden
if((AktPosRx == Len2Receive-1) && (Len2Receive > 1))
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP | AT91C_TWI_MSEN;
return;
}
void sysirq_init(void)
{
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SYS,
OPENPCD_IRQ_PRIO_SYS,
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
&sys_irq);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);
}
void tc0_tc1_interval_init(void)
{
/* Cfg PA28(TCLK1), and PA0 (TIOA0) as peripheral B */
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0,
AT91C_PA28_TCLK1|AT91C_PA0_TIOA0 );
/* Enable peripheral Clock for TC0 and TC1 */
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
((unsigned int) 1 << AT91C_ID_TC0));
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
((unsigned int) 1 << AT91C_ID_TC1));
/* Enable Clock for TC0 and TC1 */
tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN;
tcb->TCB_TC1.TC_CCR = AT91C_TC_CLKEN;
/* Connect TCLK1 to XC1, TIOA1 to XC0, so TC0 and 1 are chained */
tcb->TCB_BMR &= ~(AT91C_TCB_TC1XC1S | AT91C_TCB_TC0XC0S);
tcb->TCB_BMR |= (AT91C_TCB_TC1XC1S_TCLK1 | AT91C_TCB_TC0XC0S_TIOA1);
/*TC1 is set to waveform mode, 128 divider, 50% dutycycle waveform*/
//WAVSEL=10, RC=128,
tcb->TCB_TC1.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE | //runs from XC1, waveform mode
AT91C_TC_WAVESEL_UP_AUTO | //up counting and auto reset on RC compare
AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR | //RA compare sets TIOA1, RC compare clears TIOA
AT91C_TC_BEEVT_NONE | AT91C_TC_BCPB_NONE | //TIOB1 external event not used, RB compare not rounted out
AT91C_TC_EEVT_TIOB | AT91C_TC_ETRGEDG_NONE | //External event set to TIOB1, but not used (None edge)
AT91C_TC_BSWTRG_CLEAR | AT91C_TC_ASWTRG_CLEAR; //SW trigger resets TIOA, TIOB
tcb->TCB_TC1.TC_RC = 31;//128 divider,
tcb->TCB_TC1.TC_RA = 16;//50 duty cycle
tcb->TCB_TC1.TC_RB = 0xFFFF;//RB setting is useless since RB not used at all
/*TC0 is set to waveform mode, 65536 divider, 50% dutycycle waveform*/
tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC0 | AT91C_TC_WAVE | //runs from XC0, waveform mode
AT91C_TC_WAVESEL_UP | //up counting and auto reset on 0xFFFF compare
AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR | //RA compare sets TIOA0, RC compare clears TIOA0
AT91C_TC_BEEVT_NONE | AT91C_TC_BCPB_NONE | //TIOB1 external event not used, RB compare not rounted out
AT91C_TC_EEVT_TIOB | AT91C_TC_ETRGEDG_NONE | //External event set to TIOB1, but not used (None edge)
AT91C_TC_BSWTRG_CLEAR | AT91C_TC_ASWTRG_CLEAR; //SW trigger resets TIOA, TIOB
tcb->TCB_TC0.TC_RC = 0xFFFE;//no use at all
tcb->TCB_TC0.TC_RA = 32769;//50 duty cycle for RA compare
tcb->TCB_TC0.TC_RB = 0xFFFF;//RB setting is useless since RB not used at all
tcb->TCB_TC0.TC_IDR = 0xFF; //first disable all TC0 interrupts
tcb->TCB_TC0.TC_IER = AT91C_TC_COVFS;//Enable the counter overflow interrupt
tcb->TCB_BCR = 1;/* Reset to start timers */
/*register the interrupt handler*/
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_TC0,
OPENPCD_IRQ_PRIO_TC0,
AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE, &tc0_irq);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_TC0);
proc_status = IDLE;
params_to_proc = NULL;
}
void TWI_WR_BYTE(void)
{
//Start
if(AktPosTx == 0)
{
// AT91C_BASE_TWI->TWI_CR = 0;
//Startbedingung senden
if(AktPosTx == Len2Send-1)
//Start und Stopp senden
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START | AT91C_TWI_MSEN | AT91C_TWI_STOP;
else
//Start senden
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_START | AT91C_TWI_MSEN;
//Interrupt freigeben
AT91C_BASE_TWI->TWI_IDR = 0xFFFFFFFF;
AT91C_BASE_TWI->TWI_IER = AT91C_TWI_TXRDY;
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TWI);
}
//Stopp senden
if(AktPosTx >= (Len2Send-1))
{
AT91F_AIC_DisableIt(AT91C_BASE_AIC, AT91C_ID_TWI);
AT91C_BASE_TWI->TWI_CR = AT91C_TWI_STOP | AT91C_TWI_MSEN;
//Sendevorgang beendet
SendInProcess = false;
}
if(AktPosTx < Len2Send)
{
//Übertragung starten
//PrintfDBGU("TxByte: %d; Zaehler: %d; \n\r",*(Dat2Send+AktPosTx),AktPosTx);
AT91C_BASE_TWI->TWI_THR = *(Dat2Send+AktPosTx);
//Zähler+1
AktPosTx++;
//Clb aufrufen
if((SendInProcess == false) && (AktWRClbFunc != NULL))
{
AktWRClbFunc();
}
}
return;
}
//*----------------------------------------------------------------------------
//* Function Name : timer_init
//* Object : Init timer counter
//* Input Parameters : none
//* Output Parameters : TRUE
//*----------------------------------------------------------------------------
void timer_init (unsigned int time)
{
//* Open timer0
AT91F_TC_Open(AT91C_BASE_TC0,TC_CLKS_MCK8 | AT91C_TC_WAVESEL_UP_AUTO,AT91C_ID_TC0);
//* Open Timer 0 interrupt
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_TC0, TIMER0_INTERRUPT_LEVEL,AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, timer0_c_irq_handler);
AT91C_BASE_TC0->TC_IER = AT91C_TC_CPCS; // IRQ enable CPC
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TC0);
AT91C_BASE_TC0->TC_RC = (unsigned int)(AT91C_MASTER_CLOCK / 8 * time / 1000);
//* Start timer0
AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG ;
}
void GPIO_device_init_base(void)
{
// Enable the peripheral clock.
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, (1 << AT91C_ID_PIOA) | (1 << AT91C_ID_IRQ0));
portENTER_CRITICAL();
AT91PS_AIC pAic;
pAic = AT91C_BASE_AIC;
AT91F_PIO_InterruptEnable(AT91C_BASE_PIOA,PIO_PUSHBUTTON_SWITCH);
AT91F_AIC_ConfigureIt ( pAic, AT91C_ID_PIOA, PUSHBUTTON_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, gpio_irq_handler);
AT91F_AIC_EnableIt (pAic, AT91C_ID_PIOA);
portEXIT_CRITICAL();
}
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR )( void );
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
portENTER_CRITICAL();
{
/* Enable the USART clock. */
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 );
AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned long ) AT91C_PA5_RXD0 ) | ( ( unsigned long ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP );
/* Set the required protocol. */
AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD );
/* Enable Rx and Tx. */
serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
/* Enable the Rx interrupts. The Tx interrupts are not enabled
until there are characters to be transmitted. */
AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY );
/* Enable the interrupts in the AIC. */
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry );
AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 );
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return xReturn;
}
void Usart0_init ( long BaudRate )
{
US0_QUEUE = xQueueCreate( 10, sizeof( unsigned int ) );
US0_Error = ErrorCreate("US0_Error");
while( US0_QUEUE == 0 ) ; // Queue was not created and must not be used.
portENTER_CRITICAL();
{
AT91F_US0_CfgPIO() ; //* Define RXD and TXD as peripheral
AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1<<AT91C_ID_US0 ) ; // First, enable the clock of the PIOB
AT91F_US_Configure (COM0, MCK,AT91C_US_ASYNC_MODE, BaudRate , 0); // Usart Configure
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC,
AT91C_ID_US0,
USART_INTERRUPT_LEVEL,
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
( void (*)( void ) )AT91_US0_ISR_ENTRY);
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_US0);
}
portEXIT_CRITICAL();
}
/**
* Initialize SPI device
* @param spi_dev A SPI module hardware configuration struct
* @param spi_hw_index Hardware number (0 for SPI0, 1 for SPI1)
*/
int spi_init_dev(spi_dev_t * spi_dev) {
/* Reset the peripheral, twice */
SPI_CR = SPI_CR_SWRST_MASK;
SPI_CR = SPI_CR_SWRST_MASK;
/* Enable the SPI clock */
SPI_ECR = SPI_ECR_PIO_MASK | SPI_ECR_SPI_MASK;
/* Disable PIO on the SPI pins (enable SPI) */
SPI_PDR = SPI_PDSR_SPCK_MASK | SPI_PDSR_MISO_MASK | SPI_PDSR_MOSI_MASK
| SPI_PDSR_NPCS0_MASK | SPI_PDSR_NPCS1_MASK | SPI_PDSR_NPCS2_MASK
| SPI_PDSR_NPCS3_MASK;
/* Enable the SPI module */
SPI_CR = SPI_CR_SPIEN_MASK;
/* Configure for master mode */
SPI_MR = SPI_MR_MSTR_MASK | (spi_dev->pcs_decode << SPI_MR_PCSDEC_BIT) | (spi_dev->variable_ps << SPI_MR_PS_BIT);
/* Also, bind SPI ISR to AIC for DMA transfers */
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SPI, AT91C_AIC_PRIOR_HIGHEST, AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE, (void(*)(void)) spi_ISR);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SPI);
/* Create signalling semaphore for DMA transfers */
vSemaphoreCreateBinary(spi_sem_dma);
xSemaphoreTake(spi_sem_dma, 0);
/* Create device lock semaphore */
spi_dev->lock = NULL;
spi_dev->lock = xSemaphoreCreateMutex();
/* Configure PDC Lines for DMA transfers */
PDC_PRA6 = (uint32_t) & (SPI_RDR); // Pointer to data register RX
PDC_PRA7 = (uint32_t) & (SPI_TDR); // Pointer to data register TX
PDC_CR6 = 0; // Size = 8 bit, Direction = RX
PDC_CR7 = 1; // Size = 8 bit, Direction = TX
PDC_TCR6 = 0; // Disable PDC by setting size = 0
PDC_TCR7 = 0; // Disable PDC by setting size = 0
return 1;
}
static void prvSetupEMACInterrupt( void )
{
/* Create the semaphore used to trigger the EMAC task. */
vSemaphoreCreateBinary( xSemaphore );
if( xSemaphore )
{
/* We start by 'taking' the semaphore so the ISR can 'give' it when the
first interrupt occurs. */
xSemaphoreTake( xSemaphore, emacNO_DELAY );
portENTER_CRITICAL();
{
/* We want to interrupt on Rx events. */
AT91C_BASE_EMAC->EMAC_IER = AT91C_EMAC_RCOMP;
/* Enable the interrupts in the AIC. */
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_EMAC, emacINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, ( void (*)( void ) ) vEMACISREntry );
AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_EMAC );
}
portEXIT_CRITICAL();
}
}
//===============================================================================================
//*----------------------------------------------------------------------------
//* \fn AT91F_TWI_Open
//* \brief Initializes TWI device
//*----------------------------------------------------------------------------
void AT91F_TWI_Init(void)
{
TWI_QUEUE = xQueueCreate( 1, sizeof( unsigned int ) );
TWI_NACK_Error = ErrorCreate("TWI Nack");
TWI_TMO_Error = ErrorCreate("TWI TimeOut");
TWI_SEM_Error = ErrorCreate("TWI Access");
TWI_WriteData_Error = ErrorCreate("TWI Write");
TWI_OVRE_Error = ErrorCreate("TWI OVRE");
vSemaphoreCreateBinary( TWI_Semaphore );
while( TWI_QUEUE == 0 ) ; // Queue was not created and must not be used.
portENTER_CRITICAL();
{
// Configure TWI in master mode
AT91F_TWI_Configure (AT91C_BASE_TWI);
// Configure TWI PIOs
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, AT91C_PA1_TWCK );
AT91F_PIO_CfgOpendrain(AT91C_BASE_PIOA, // PIO controller base address
((unsigned int) AT91C_PA1_TWCK ) |
((unsigned int) AT91C_PA0_TWD ) );
AT91F_TWI_CfgPIO();
// Configure PMC by enabling TWI clock
AT91F_TWI_CfgPMC ();
// AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1<<AT91C_ID_TWI ) ;
// Set TWI Clock Waveform Generator Register
AT91F_SetTwiClock();
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC,
AT91C_ID_TWI,
TWI_INTERRUPT_LEVEL,
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
( void (*)( void ) )AT91_TWI_ISR_ENTRY);
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TWI);
TWI_TransferStatus = FREE;
}
portEXIT_CRITICAL();
}
/* Low level register access routines.
*/
static int dsp_init (SND_DEV *pDev)
{
int version;
AT91PS_SSC pSSC = (AT91PS_SSC ) pDev->port;
/* Initialization the DSP
*/
/* ============================= Init SSC1 in Output mode =============================*/
/* Configure SSC1 PIOs TF/TK/TD */
*AT91C_PIOB_PDR= ((unsigned int) AT91C_PB7_TK1 ) |
((unsigned int) AT91C_PB8_TD1 ) |
((unsigned int) AT91C_PB6_TF1 );
/* Configure PMC by enabling SSC1 clock */
AT91F_SSC1_CfgPMC();
/* Reset All the Peripheral */
pSSC->SSC_CR = AT91C_SSC_SWRST ;
/* Clear Transmit and Receive Counters*/
AT91F_PDC_Close((AT91PS_PDC) &(pSSC->SSC_RPR));
/* Define the Clock Mode Register at 2*16*44100 => 1.4112 MHz */
AT91F_SSC_SetBaudrate(pSSC, MCK, FILE_SAMPLING_FREQ*(BITS_BY_SLOT*SLOT_BY_FRAME));
/* Write the Transmit Frame Mode Register*/
pSSC->SSC_TFMR = I2S_ASY_TX_FRAME_SETTING(BITS_BY_SLOT, SLOT_BY_FRAME);
/* Configure AIC controller to handle SSC interrupts*/
/* AT91F_AIC_ConfigureIt (
AT91C_BASE_AIC,
AT91C_ID_SSC1,
IRQ_LEVEL_I2S,
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE,
AT91F_ASM_I2S_Handler );*/
/* Enable SSC interrupt in AIC*/
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SSC1);
return 0;
}
/*
* Setup the timer 0 to generate the tick interrupts at the required frequency.
*/
static void
prvSetupTimerInterrupt( void )
{
/* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
* on whether the preemptive or cooperative scheduler is being used.
*/
#if configUSE_PREEMPTION == 0
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST,
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
( void ( * )( void ) )vNonPreemptiveTick );
#else
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST,
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
( void ( * )( void ) )vPreemptiveTick );
#endif
/* Configure the PIT period. */
AT91F_PITInit( AT91C_BASE_PITC, portTICK_RATE_MS * 1000U, configCPU_CLOCK_HZ / 1000000U );
AT91F_PITEnableInt( AT91C_BASE_PITC );
AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
}
// функция инициализации таймеров-счетчиков
void timer_init ( void )
{
// разрешение timer 0
// AT91F_TC_Open(AT91C_BASE_TC0,TC_CLKS_MCK1024,AT91C_ID_TC0);
// разрешение прерываний от Timer 0
// AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_TC0,
// TIMER0_INTERRUPT_LEVEL,AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, timer0_c_irq_handler);
// AT91C_BASE_TC0->TC_IER = AT91C_TC_COVFS; // разрешение прерывания по переполнению
// AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TC0);
// разрешение timer 1
AT91F_TC_Open(AT91C_BASE_TC1,TC_CLKS_MCK2,AT91C_ID_TC1);
// разрешение прерываний от Timer 1
AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, AT91C_ID_TC1,
TIMER1_INTERRUPT_LEVEL,AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, timer1_c_irq_handler);
AT91C_BASE_TC1->TC_IER = AT91C_TC_CPCS; //разрешение прерывания при совпадении с RC
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_TC1);
AT91C_BASE_TC1->TC_RC = 0x1000 ; // задание значения RC (определяет период прерываний)
AT91C_BASE_TC1->TC_CMR = AT91C_TC_CPCTRG ; //задание триггера при совпадении с RC
// сброс и запуск timer0
// AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG ;
// сброс и запуск timer1
AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG ;
}
static void prvSetupTimerInterrupt( void )
{
AT91PS_PITC pxPIT = AT91C_BASE_PITC;
/* Setup the AIC for PIT interrupts. The interrupt routine chosen depends
on whether the preemptive or cooperative scheduler is being used. */
#if configUSE_PREEMPTION == 0
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick );
#else
extern void ( vPortPreemptiveTick )( void );
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );
#endif
/* Configure the PIT period. */
pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
/* Enable the interrupt. Global interrupts are disables at this point so
this is safe. */
AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
}
unsigned char canInit(unsigned int bitrate)
/******************************************************************************
Initialize the hardware to receive CAN messages and start the timer for the
CANopen stack.
INPUT
OUTPUT
******************************************************************************/
{
unsigned char i;
AT91S_CAN_MB *mb_ptr = AT91C_BASE_CAN_MB0;
// Enable CAN PIOs
AT91F_CAN_CfgPIO();
// Enable CAN Clock
AT91F_CAN_CfgPMC();
// Enable CAN Transceiver
AT91F_PIOA_CfgPMC();
// Init CAN Interrupt Source Level
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, // CAN base address
AT91C_ID_CAN, // CAN ID
AT91C_AIC_PRIOR_HIGHEST, // Max priority
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, // Level sensitive
can_irq_handler); // C Handler
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_CAN);
if (bitrate <= 500)
{
// CANopen 10..500 kbit with 16 tq, sample point is at 14 tq
// all values are added to 1 by hardware
// Resynchronisation jump width (SJW) = 1 tq
// Propagation Time Segment (PRS) = 5 tq
// Phase Segment 1 (PHS1) = 8 tq
// Phase Segment 2 (PHS2) = 2 tq
// Total = 16 tq
AT91F_CAN_CfgBaudrateReg(AT91C_BASE_CAN,
(AT91C_MASTER_CLOCK/16/1000/bitrate - 1) << 16 | 0x0471);
}
else
return 0;
// Enable CAN and Wait for WakeUp Interrupt
// AT91F_CAN_EnableIt(AT91C_BASE_CAN, AT91C_CAN_WAKEUP);
AT91F_CAN_CfgModeReg(AT91C_BASE_CAN, AT91C_CAN_CANEN);
// Reset all mailsboxes (MBs), filters are zero (accept all) by clear all MB
// Set the lower MBs as rx buffer
for (i = 0; i < NB_RX_MB; i++, mb_ptr++)
// Configure receive MBs as receive buffer, last as receive overwrite
AT91F_InitMailboxRegisters(mb_ptr,
((i < (NB_RX_MB - 1)) ? AT91C_CAN_MOT_RX : AT91C_CAN_MOT_RXOVERWRITE)
| AT91C_CAN_PRIOR, // Mailbox Mode Reg
0x00000000, // Mailbox Acceptance Mask Reg
0x00000000, // Mailbox ID Reg
0x00000000, // Mailbox Data Low Reg
0x00000000, // Mailbox Data High Reg
0x00000000); // Mailbox Control Reg
for ( ; i < NB_MB; i++, mb_ptr++)
// Configure transmit MBs
AT91F_InitMailboxRegisters(mb_ptr,
AT91C_CAN_MOT_TX
| AT91C_CAN_PRIOR, // Mailbox Mode Reg
0x00000000, // Mailbox Acceptance Mask Reg
0x00000000, // Mailbox ID Reg
0x00000000, // Mailbox Data Low Reg
0x00000000, // Mailbox Data High Reg
0x00000000); // Mailbox Control Reg
// Enable Reception on all receive Mailboxes
AT91F_CAN_InitTransferRequest(AT91C_BASE_CAN, RX_INT_MSK);
// Enable all receive interrupts
AT91F_CAN_EnableIt(AT91C_BASE_CAN, RX_INT_MSK);
return 1;
}
//===============================================================================================
void AT91F_USART_OPEN(AT91_USART_ID idPort, long BaudRate, int mode)
{
portENTER_CRITICAL();
{
switch (idPort)
{
case AT91_USART_COM0_ID:
COM0.id = idPort;
COM0.hPort = AT91C_BASE_US0;
COM0.hError = ErrorCreate("US0_Error");
COM0.hPDC = AT91C_BASE_PDC_US0;
AT91F_PDC_Open(COM0.hPDC);
// AT91F_US0_CfgPIO(); //* Define RXD and TXD as peripheral
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, // PIO controller base address
(((unsigned int) AT91C_PA5_RXD0)
| ((unsigned int) AT91C_PA6_TXD0)), // Peripheral A
0);
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, 1 << AT91C_ID_US0); // First, enable the clock of the PIOB
AT91F_US_Configure(COM0.hPort, MCK, mode, BaudRate, 0); // Usart Configure
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_US0,
USART_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
(void(*)(void)) AT91_US0_ISR_ENTRY);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_US0);
COM0.hRxQueue = xQueueCreate(1, sizeof(int));
while (COM0.hRxQueue == 0)
; // Queue was not created and must not be used.
COM0.hTxQueue = xQueueCreate(1, sizeof(int));
while (COM0.hTxQueue == 0)
; // Queue was not created and must not be used.
break;
case AT91_USART_COM1_ID:
COM1.id = idPort;
COM1.hPort = AT91C_BASE_US1;
COM1.hPDC = AT91C_BASE_PDC_US1;
COM1.hError = ErrorCreate("US1_Error");
AT91F_PDC_DisableTx(COM1.hPDC);
AT91F_PDC_DisableRx(COM1.hPDC);
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, // PIO controller base address
(((unsigned int) AT91C_PA21_RXD1)
| ((unsigned int) AT91C_PA22_TXD1)), // Peripheral A
0);
AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, 1 << AT91C_ID_US1); // First, enable the clock of the PIOB
AT91F_US_Configure(COM1.hPort, MCK, mode, BaudRate, 0); // Usart Configure
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_US1,
USART_INTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
(void(*)(void)) AT91_US1_ISR_ENTRY);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_US1);
COM1.hRxQueue = xQueueCreate(1, sizeof(int));
while (COM1.hRxQueue == 0)
; // Queue was not created and must not be used.
COM1.hTxQueue = xQueueCreate(1, sizeof(int));
while (COM1.hTxQueue == 0)
; // Queue was not created and must not be used.
break;
default:
while (1)
;// error port notfound;
}
}
portEXIT_CRITICAL();
}
void enableSysIRQ()
{
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_UDP);
}
char SPI_RFM12_Execute(char *Buffer_Tx, char *Buffer_Rx)
{
int Order= Buffer_Tx[0] | Buffer_Tx[1]<<8;
//Je�eli uk�ad RF12 w trakcie inicjalizacji pierwotnej---------------------
cztmp[0]=RF_SetFreqReg(0);
if (RF_Status.Init)
{
RF_Status.Ch=0;
if (Order==0x80E7)
{ if (RF_Status.EnRx) RF_Status.EnableRX(); else RF_Status.EnableTX(); } //Rozkaz: 0x80E7 - EL,EF,868band,12.0pF
if ((Order==0x8299) || (Order==0x8239) )
{ SPI_SendWord(0xA000 | RF_SetFreqReg(RF_Status.Ch),Cs_RF); } //Rozkaz: 0xA6xx Cz�stotliwo�� bazowa (Kana� 0) - oryginalnie by�o 0xA640 - 868,0Mhz
if (Order==(0xA000 | RF_SetFreqReg(RF_Status.Ch)))
{ SPI_SendWord(0xC607,Cs_RF); } //Rozkaz: 0xC607 Szybko�� transmisji 43kb/s - oryginalnie by�o 0xC647 - 4,8kb/s
if (Order==0xC607)
{ SPI_SendWord(0x94A0,Cs_RF); } //Rozkaz: 0x94A0 VDI,FAST,134kHz,0dBm,-103dBm
if (Order==0x94A0)
{ SPI_SendWord(0xC2AC,Cs_RF); } //Rozkaz: 0xC2AC AL,!ml,DIG,DQD4
if (Order==0xC2AC)
{ SPI_SendWord(0xCA81,Cs_RF); } //Rozkaz: 0xCA81 FIFO8,SYNC,!ff,DR
if ((Order==0xCA81) && (IntCA81Flag==0))
{ SPI_SendWord(0xCED4,Cs_RF); IntCA81Flag=1; Order=0xFFFF;} //Rozkaz: 0xCED4 ustawienie s�owa synchronizacyjnego na 0x2DD4
if (Order==0xCED4)
{ SPI_SendWord(0xC493,Cs_RF); } //Rozkaz: 0xC493 @PWR, AFC:-80+75Khz ,!st,!fi,OE,EN - oryginalnie 0xC483 @PWR,AFC - NO RSTRIC,!st,!fi,OE,EN
if (Order==0xC493)
{ SPI_SendWord(0x9850,Cs_RF); } //Rozkaz: 0x9850 !mp,dewiacja +-90kHz ,MAX OUT
if (Order==0x9850)
{ SPI_SendWord(0xCC17,Cs_RF); } //Rozkaz: 0xCC17 OB1�COB0, LPX,�Iddy�CDDIT�C
if (Order==0xCC17)
{ SPI_SendWord(0xE000,Cs_RF); } //Rozkaz: 0xE000
if (Order==0xE000)
{ SPI_SendWord(0xC800,Cs_RF); } //Rozkaz: 0xC800
if (Order==0xC800)
{ SPI_SendWord(0xC040,Cs_RF); } //Rozkaz: 0xC040 1.66MHz,2.2V
if (Order==0xC040)
{ SPI_SendWord(0xCA81,Cs_RF); } //Rozkaz: 0xCA81 Start fifo RX
if ((Order==0xCA81) && (IntCA81Flag==1))
{ SPI_SendWord(0xCA83,Cs_RF); } //Rozkaz: 0xCA83 Restart fifo RX
if (Order==0xCA83)
{
RF_Status.EnRx=1;
RF_Status.Init=0;
//ustawienie przerwania
ConfigureRFBus();
// Configure and enable the Vbus detection interrupt
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC,
ID_RfIntBUS,
RF_INT_PRIOR, //AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_PRIOR_HIGHEST
3,//AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL,
RF_Int);
AT91F_PIO_InterruptEnable(PIO_RfIntBUS, RfIntBUS);
AT91F_AIC_EnableIt(AT91C_BASE_AIC, ID_RfIntBUS);
}
}//Aktywny RX ---------------------------------------------------------------
else if ((RF_Status.EnRx) && (RF_Status.Init==0))
{
if ((Order==0x0000) && (Buffer_Rx[1]&0x80)) { SPI_SendWord(0xB000,Cs_RF); }
if (Order==0xCA81) { SPI_SendWord(0xCA83,Cs_RF); }
if (Order==0xCA83) { SPI_SendWord(0x0000,Cs_RF); }
if (Order==0xB000) { RF_ReciveByte(Buffer_Rx[0]); }
}//Aktywny TX ---------------------------------------------------------------
else if (RF_Status.EnTx)
{
/*
if ((RF_Status.Transmit==0) && (Order==0x0000))
{
RF_Status.Transmit=1;
RF_transmit();
}
*/
if ((RF_Status.Transmit==0) && (Order==0x0000))
{
//TRACE_INFO("Tx %X \n\r ", Buffer_Rx[1]);
if (Buffer_Rx[1]&0x20)
{
SPI_SendWord(0x0000,Cs_RF);
}
else
{
RF_Status.Transmit=1;
RF_transmit();
}
}
}
//W��czenie Odbiornika
else if ((RF_Status.EnRx==0) && (RF_Status.EnTx==0) && (Order==0x8299))
{
RF_Status.EnRx=1;
SPI_SendWord(0x0000,Cs_RF);
}
//W��czenie Nadajnika
else if ((RF_Status.EnRx==0) && (RF_Status.EnTx==0) && (Order==0x8239))
{
for (int aaa=0; aaa<0x5FF; aaa++) asm( "nop" ); //u�pienie ~200us - wymagany czas prze��czenia z odbiornika na nadajnik
RF_Status.EnTx=1;
if (RF_Tx.BytesToSend>0)
{
RF_transmit();
}
}
} _RF_Command *pRF_Command;
void spi_low_irq_start(void)
{
spi_low_tx_irq_enable();
AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_SPI);
}
