void poti_init(void)
{
AT91F_SPI_CfgPMC();
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA,
AT91C_PA13_MOSI | AT91C_PA14_SPCK, 0);
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPICC_PIO_SS2_DT_THRESH);
AT91F_PIO_SetOutput(AT91C_BASE_PIOA, OPENPICC_PIO_SS2_DT_THRESH);
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPICC_PIO_nSLAVE_RESET);
poti_reset();
#if 0
AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SPI,
OPENPCD_IRQ_PRIO_SPI,
AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &spi_irq);
AT91G_AIC_EnableIt(AT9C_BASE_AIC, AT91C_ID_SPI);
#endif
AT91F_SPI_CfgMode(spi, AT91C_SPI_MSTR |
AT91C_SPI_PS_FIXED | AT91C_SPI_MODFDIS);
/* CPOL = 0, NCPHA = 1, CSAAT = 0, BITS = 0000, SCBR = 13 (3.69MHz),
* DLYBS = 6 (125nS), DLYBCT = 0 */
AT91F_SPI_CfgCs(spi, 0, AT91C_SPI_BITS_8 | AT91C_SPI_NCPHA |
(13 << 8) | (6 << 16));
AT91F_SPI_Enable(spi);
}
void soundInit( void ) {
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, SPI_PERIPH, 0x0); //Sets the output lines required for the SPI.
AT91F_SPI_CfgPMC(); // Enables the SPI periphial clock.
AT91F_SPI_CfgMode (AT91C_BASE_SPI, SPI_MODE); //Sets the SPI's mode.
AT91F_SPI_CfgCs(AT91C_BASE_SPI, 0, CS_REG); // Sets the clients settings.
AT91F_SPI_Enable(AT91C_BASE_SPI); // Enables the SPI.
}
unsigned char nRFCMD_Init(void)
{
volatile int dummy;
const int SCBR = ((int)(MCK / 8e6) + 1)&0xFF;
nRFCMD_Macro=nRFCMD_MacroResult=NULL;
vSemaphoreCreateBinary(xnRF_SemaphoreDMA);
vSemaphoreCreateBinary(xnRF_SemaphoreACK);
if(!(xnRF_SemaphoreDMA && xnRF_SemaphoreACK))
return 1;
xSemaphoreTake(xnRF_SemaphoreDMA,0);
xSemaphoreTake(xnRF_SemaphoreACK,0);
AT91F_SPI_CfgPMC();
AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, NRF_SPI_PINS_PERIPHERAL_A, NRF_SPI_PINS_PERIPHERAL_B);
AT91F_PIO_CfgInput(AT91C_BASE_PIOA, IRQ_PIN);
AT91F_PIO_ClearOutput(AT91C_BASE_PIOA, CE_PIN);
AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, CE_PIN);
portENTER_CRITICAL();
/* CPOL = 0, NCPHA = 1, CSAAT = 0, BITS = 0000, SCBR = <8MHz,
* DLYBS = 0, DLYBCT = 0 */
AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_PS_FIXED;
AT91F_SPI_CfgCs(AT91C_BASE_SPI, 0, AT91C_SPI_BITS_8|AT91C_SPI_NCPHA|(SCBR<<8));
AT91F_SPI_Enable(AT91C_BASE_SPI);
AT91F_AIC_ConfigureIt(AT91C_ID_SPI, 4, AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE, nRFCMD_ISR_DMA );
AT91C_BASE_SPI->SPI_IER = AT91C_SPI_ENDTX;
/* Enable PIO interrupt for IRQ pin */
AT91F_AIC_ConfigureIt(AT91C_ID_PIOA, 3, AT91C_AIC_SRCTYPE_HIGH_LEVEL, nRFCMD_ISR_ACK );
/* reset IRQ status */
dummy = AT91C_BASE_PIOA->PIO_ISR;
AT91C_BASE_PIOA->PIO_IER = IRQ_PIN;
AT91C_BASE_AIC->AIC_IECR = (0x1 << AT91C_ID_SPI) | (0x1 << AT91C_ID_PIOA) ;
portEXIT_CRITICAL();
return 0;
}
