void sama5d3_xplained_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
at91_periph_clk_enable(ATMEL_ID_SMC);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
&smc->cs[3].cycle);
writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
}
static void sama5d3xek_nor_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
at91_periph_clk_enable(ATMEL_ID_SMC);
/* Configure SMC CS0 for NOR flash */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[0].setup);
writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
&smc->cs[0].pulse);
writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
&smc->cs[0].cycle);
writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) |
AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) |
AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)|
AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_16 |
AT91_SMC_MODE_TDF_CYCLE(1),
&smc->cs[0].mode);
/* Address pin (A1 ~ A23) configuration */
at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
/* CS0 pin configuration */
at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
}
static void sama5d4_xplained_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
at91_periph_clk_enable(ATMEL_ID_SMC);
/* Configure SMC CS3 for NAND */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(3),
&smc->cs[3].mode);
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
}
