/**Function*************************************************************
Synopsis [Computes the transition relation of the network.]
Description [Assumes that the global BDDs are computed.]
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Abc_NtkTransitionRelation( DdManager * dd, Abc_Ntk_t * pNtk, int fVerbose )
{
DdNode * bRel, * bTemp, * bProd, * bVar, * bInputs;
Abc_Obj_t * pNode;
int fReorder = 1;
int i;
// extand the BDD manager to represent NS variables
assert( dd->size == Abc_NtkCiNum(pNtk) );
Cudd_bddIthVar( dd, Abc_NtkCiNum(pNtk) + Abc_NtkLatchNum(pNtk) - 1 );
// enable reordering
if ( fReorder )
Cudd_AutodynEnable( dd, CUDD_REORDER_SYMM_SIFT );
else
Cudd_AutodynDisable( dd );
// compute the transition relation
bRel = b1; Cudd_Ref( bRel );
Abc_NtkForEachLatch( pNtk, pNode, i )
{
bVar = Cudd_bddIthVar( dd, Abc_NtkCiNum(pNtk) + i );
// bProd = Cudd_bddXnor( dd, bVar, pNtk->vFuncsGlob->pArray[i] ); Cudd_Ref( bProd );
bProd = Cudd_bddXnor( dd, bVar, Abc_ObjGlobalBdd(Abc_ObjFanin0(pNode)) ); Cudd_Ref( bProd );
bRel = Cudd_bddAnd( dd, bTemp = bRel, bProd ); Cudd_Ref( bRel );
Cudd_RecursiveDeref( dd, bTemp );
Cudd_RecursiveDeref( dd, bProd );
}
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sim_Man_t * Sim_ManStart( Abc_Ntk_t * pNtk, int fLightweight )
{
Sim_Man_t * p;
// start the manager
p = ALLOC( Sim_Man_t, 1 );
memset( p, 0, sizeof(Sim_Man_t) );
p->pNtk = pNtk;
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimBits = 2048;
p->nSimWords = SIM_NUM_WORDS(p->nSimBits);
p->vSim0 = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
p->fLightweight = fLightweight;
if (!p->fLightweight) {
p->vSim1 = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// support information
p->nSuppBits = Abc_NtkCiNum(pNtk);
p->nSuppWords = SIM_NUM_WORDS(p->nSuppBits);
p->vSuppStr = Sim_ComputeStrSupp( pNtk );
p->vSuppFun = Sim_UtilInfoAlloc( Abc_NtkCoNum(p->pNtk), p->nSuppWords, 1 );
// other data
p->pMmPat = Extra_MmFixedStart( sizeof(Sim_Pat_t) + p->nSuppWords * sizeof(unsigned) );
p->vFifo = Vec_PtrAlloc( 100 );
p->vDiffs = Vec_IntAlloc( 100 );
// allocate support targets (array of unresolved outputs for each input)
p->vSuppTargs = Vec_VecStart( p->nInputs );
}
return p;
}
/**Function*************************************************************
Synopsis [Finalizes the timing manager after setting arr/req times.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTimeInitialize( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkOld )
{
Abc_Obj_t * pObj;
Abc_Time_t ** ppTimes, * pTime;
int i;
assert( pNtkOld == NULL || pNtkOld->pManTime != NULL );
assert( pNtkOld == NULL || Abc_NtkCiNum(pNtk) == Abc_NtkCiNum(pNtkOld) );
assert( pNtkOld == NULL || Abc_NtkCoNum(pNtk) == Abc_NtkCoNum(pNtkOld) );
if ( pNtk->pManTime == NULL )
return;
Abc_ManTimeExpand( pNtk->pManTime, Abc_NtkObjNumMax(pNtk), 0 );
// set global defaults
if ( pNtkOld )
{
pNtk->pManTime->tArrDef = pNtkOld->pManTime->tArrDef;
pNtk->pManTime->tReqDef = pNtkOld->pManTime->tReqDef;
pNtk->AndGateDelay = pNtkOld->AndGateDelay;
}
// set the default timing
ppTimes = (Abc_Time_t **)pNtk->pManTime->vArrs->pArray;
Abc_NtkForEachCi( pNtk, pObj, i )
{
pTime = ppTimes[pObj->Id];
if ( Abc_MaxFloat(pTime->Fall, pTime->Rise) != -ABC_INFINITY )
continue;
*pTime = pNtkOld ? *Abc_NodeReadArrival(Abc_NtkCi(pNtkOld, i)) : pNtk->pManTime->tArrDef;
}
/**Function*************************************************************
Synopsis [Load the network into manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Map_Time_t * Abc_NtkMapCopyCiArrivalCon( Abc_Ntk_t * pNtk )
{
Map_Time_t * p; int i;
p = ABC_CALLOC( Map_Time_t, Abc_NtkCiNum(pNtk) );
for ( i = 0; i < Abc_NtkCiNum(pNtk); i++ )
p[i].Fall = p[i].Rise = p[i].Worst = Scl_Int2Flt( Scl_ConGetInArr(i) );
return p;
}
/**Function*************************************************************
Synopsis [Load the network into manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Map_Time_t * Abc_NtkMapCopyCiArrival( Abc_Ntk_t * pNtk, Abc_Time_t * ppTimes )
{
Map_Time_t * p;
int i;
p = ABC_CALLOC( Map_Time_t, Abc_NtkCiNum(pNtk) );
for ( i = 0; i < Abc_NtkCiNum(pNtk); i++ )
{
p[i].Fall = ppTimes[i].Fall;
p[i].Rise = ppTimes[i].Rise;
p[i].Worst = Abc_MaxFloat( p[i].Fall, p[i].Rise );
}
ABC_FREE( ppTimes );
return p;
}
Abc_Ntk_t * Abc_NtkFromMap( Map_Man_t * pMan, Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkNew;
Map_Node_t * pNodeMap;
Abc_Obj_t * pNode, * pNodeNew;
int i, nDupGates;
assert( Map_ManReadBufNum(pMan) == pNtk->nBarBufs );
// create the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_MAP );
// make the mapper point to the new network
Map_ManCleanData( pMan );
Abc_NtkForEachCi( pNtk, pNode, i )
{
if ( i >= Abc_NtkCiNum(pNtk) - pNtk->nBarBufs )
break;
Map_NodeSetData( Map_ManReadInputs(pMan)[i], 1, (char *)pNode->pCopy );
}
Abc_NtkForEachCi( pNtk, pNode, i )
{
if ( i < Abc_NtkCiNum(pNtk) - pNtk->nBarBufs )
continue;
Map_NodeSetData( Map_ManReadBufs(pMan)[i - (Abc_NtkCiNum(pNtk) - pNtk->nBarBufs)], 1, (char *)pNode->pCopy );
}
// assign the mapping of the required phase to the POs
Abc_NtkForEachCo( pNtk, pNode, i )
{
if ( i < Abc_NtkCoNum(pNtk) - pNtk->nBarBufs )
continue;
pNodeMap = Map_ManReadBufDriver( pMan, i - (Abc_NtkCoNum(pNtk) - pNtk->nBarBufs) );
pNodeNew = Abc_NodeFromMap_rec( pNtkNew, Map_Regular(pNodeMap), !Map_IsComplement(pNodeMap) );
assert( !Abc_ObjIsComplement(pNodeNew) );
Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
}
Abc_NtkForEachCo( pNtk, pNode, i )
{
if ( i >= Abc_NtkCoNum(pNtk) - pNtk->nBarBufs )
break;
pNodeMap = Map_ManReadOutputs(pMan)[i];
pNodeNew = Abc_NodeFromMap_rec( pNtkNew, Map_Regular(pNodeMap), !Map_IsComplement(pNodeMap) );
assert( !Abc_ObjIsComplement(pNodeNew) );
Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
}
// decouple the PO driver nodes to reduce the number of levels
nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
// if ( nDupGates && Map_ManReadVerbose(pMan) )
// printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
return pNtkNew;
}
/**Function*************************************************************
Synopsis [Derives GIA manager together with the hierachy manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Abc_NtkTestTimDeriveGia( Abc_Ntk_t * pNtk, int fVerbose )
{
Gia_Man_t * pTemp;
Gia_Man_t * pGia = NULL;
Gia_Man_t * pHoles = NULL;
Tim_Man_t * pTim = NULL;
Vec_Int_t * vGiaCoLits, * vGiaCoLits2;
Vec_Flt_t * vArrTimes, * vReqTimes;
Abc_Obj_t * pObj, * pFanin;
int i, k, Entry, curPi, curPo, BoxUniqueId;
int nBoxFaninMax = 0;
assert( Abc_NtkIsTopo(pNtk) );
Abc_NtkFillTemp( pNtk );
// create white boxes
curPi = Abc_NtkCiNum(pNtk);
curPo = Abc_NtkCoNum(pNtk);
Abc_NtkForEachNode( pNtk, pObj, i )
{
pObj->fMarkA = Abc_NodeIsWhiteBox( pObj );
if ( !pObj->fMarkA )
continue;
nBoxFaninMax = Abc_MaxInt( nBoxFaninMax, Abc_ObjFaninNum(pObj) );
curPi++;
curPo += Abc_ObjFaninNum(pObj);
if ( fVerbose )
printf( "Selecting node %6d as white boxes with %d inputs and %d output.\n", i, Abc_ObjFaninNum(pObj), 1 );
}
/**Function*************************************************************
Synopsis [Returns the array of CI IDs.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Int_t * Abc_NtkGetCiSatVarNums( Abc_Ntk_t * pNtk )
{
Vec_Int_t * vCiIds;
Abc_Obj_t * pObj;
int i;
vCiIds = Vec_IntAlloc( Abc_NtkCiNum(pNtk) );
Abc_NtkForEachCi( pNtk, pObj, i )
Vec_IntPush( vCiIds, (int)(ABC_PTRINT_T)pObj->pCopy );
return vCiIds;
}
/**Function*************************************************************
Synopsis [Sets the arrival time for an object.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTimeSetInputDrive( Abc_Ntk_t * pNtk, int PiNum, float Rise, float Fall )
{
Abc_Time_t * pTime;
assert( PiNum >= 0 && PiNum < Abc_NtkCiNum(pNtk) );
if ( pNtk->pManTime == NULL )
pNtk->pManTime = Abc_ManTimeStart();
if ( pNtk->pManTime->tInDriveDef.Rise == Rise && pNtk->pManTime->tInDriveDef.Fall == Fall )
return;
if ( pNtk->pManTime->tInDrive == NULL )
{
int i;
pNtk->pManTime->tInDrive = ABC_CALLOC( Abc_Time_t, Abc_NtkCiNum(pNtk) );
for ( i = 0; i < Abc_NtkCiNum(pNtk); i++ )
pNtk->pManTime->tInDrive[i] = pNtk->pManTime->tInDriveDef;
}
pTime = pNtk->pManTime->tInDrive + PiNum;
pTime->Rise = Rise;
pTime->Fall = Fall;
}
Vec_Ptr_t * Abc_NtkAssignIDs2( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj;
int i;
Abc_NtkCleanCopy( pNtk );
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->iTemp = i;
vNodes = Vec_PtrAlloc( Abc_NtkNodeNum(pNtk) );
Abc_NtkForEachNode( pNtk, pObj, i )
{
pObj->iTemp = Abc_NtkCiNum(pNtk) + Vec_PtrSize(vNodes);
Vec_PtrPush( vNodes, pObj );
}
/**Function*************************************************************
Synopsis [Starts a new network using existing network as a model.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkStartFrom( Abc_Ntk_t * pNtk, Abc_NtkType_t Type, Abc_NtkFunc_t Func )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj;
int fCopyNames, i;
if ( pNtk == NULL )
return NULL;
// decide whether to copy the names
fCopyNames = ( Type != ABC_NTK_NETLIST );
// start the network
pNtkNew = Abc_NtkAlloc( Type, Func, 1 );
// duplicate the name and the spec
pNtkNew->pName = Extra_UtilStrsav(pNtk->pName);
pNtkNew->pSpec = Extra_UtilStrsav(pNtk->pSpec);
// clean the node copy fields
Abc_NtkCleanCopy( pNtk );
// map the constant nodes
if ( Abc_NtkIsStrash(pNtk) && Abc_NtkIsStrash(pNtkNew) )
Abc_AigConst1(pNtk)->pCopy = Abc_AigConst1(pNtkNew);
// clone CIs/CIs/boxes
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, fCopyNames );
Abc_NtkForEachPo( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, fCopyNames );
Abc_NtkForEachAssert( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, fCopyNames );
Abc_NtkForEachBox( pNtk, pObj, i )
Abc_NtkDupBox( pNtkNew, pObj, fCopyNames );
// transfer the names
// Abc_NtkTrasferNames( pNtk, pNtkNew );
Abc_ManTimeDup( pNtk, pNtkNew );
// check that the CI/CO/latches are copied correctly
assert( Abc_NtkCiNum(pNtk) == Abc_NtkCiNum(pNtkNew) );
assert( Abc_NtkCoNum(pNtk) == Abc_NtkCoNum(pNtkNew) );
assert( Abc_NtkLatchNum(pNtk) == Abc_NtkLatchNum(pNtkNew) );
return pNtkNew;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Abc_NtkAssignIDs( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj;
int i;
vNodes = Abc_NtkDfs( pNtk, 0 );
Abc_NtkCleanCopy( pNtk );
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->iTemp = i;
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
pObj->iTemp = Abc_NtkCiNum(pNtk) + i;
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->iTemp = Abc_NtkCiNum(pNtk) + Vec_PtrSize(vNodes) + i;
return vNodes;
}
/**Function*************************************************************
Synopsis [Sets the default arrival time for the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTimeSetDefaultInputDrive( Abc_Ntk_t * pNtk, float Rise, float Fall )
{
if ( Rise == 0.0 && Fall == 0.0 )
return;
if ( pNtk->pManTime == NULL )
pNtk->pManTime = Abc_ManTimeStart();
pNtk->pManTime->tInDriveDef.Rise = Rise;
pNtk->pManTime->tInDriveDef.Fall = Fall;
if ( pNtk->pManTime->tInDrive != NULL )
{
int i;
for ( i = 0; i < Abc_NtkCiNum(pNtk); i++ )
if ( pNtk->pManTime->tInDrive[i].Rise == 0 && pNtk->pManTime->tInDrive[i].Fall == 0 )
pNtk->pManTime->tInDrive[i] = pNtk->pManTime->tInDriveDef;
}
}
void updateNewNetworkNameManager_kCS( Abc_Ntk_t *pNtk, Aig_Man_t *pAig, Vec_Ptr_t *vPiNames,
Vec_Ptr_t *vLoNames, Vec_Ptr_t *vPoNames, Vec_Ptr_t *vLiNames )
{
Aig_Obj_t *pObj;
Abc_Obj_t *pNode;
int i, ntkObjId;
pNtk->pManName = Nm_ManCreate( Abc_NtkCiNum( pNtk ) );
if( vPiNames )
{
Saig_ManForEachPi( pAig, pObj, i )
{
ntkObjId = Abc_NtkCi( pNtk, i )->Id;
Nm_ManStoreIdName( pNtk->pManName, ntkObjId, Aig_ObjType(pObj), (char *)Vec_PtrEntry(vPiNames, i), NULL );
}
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Computes the initial state and sets up the variable map.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Abc_NtkInitStateVarMap( DdManager * dd, Abc_Ntk_t * pNtk, int fVerbose )
{
DdNode ** pbVarsX, ** pbVarsY;
DdNode * bTemp, * bProd, * bVar;
Abc_Obj_t * pLatch;
int i;
// set the variable mapping for Cudd_bddVarMap()
pbVarsX = ABC_ALLOC( DdNode *, dd->size );
pbVarsY = ABC_ALLOC( DdNode *, dd->size );
bProd = b1; Cudd_Ref( bProd );
Abc_NtkForEachLatch( pNtk, pLatch, i )
{
pbVarsX[i] = dd->vars[ Abc_NtkPiNum(pNtk) + i ];
pbVarsY[i] = dd->vars[ Abc_NtkCiNum(pNtk) + i ];
// get the initial value of the latch
bVar = Cudd_NotCond( pbVarsX[i], !Abc_LatchIsInit1(pLatch) );
bProd = Cudd_bddAnd( dd, bTemp = bProd, bVar ); Cudd_Ref( bProd );
Cudd_RecursiveDeref( dd, bTemp );
}
/**Function*************************************************************
Synopsis [Solves the targets added by ABC_AddTarget().]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
enum CSAT_StatusT ABC_Solve( ABC_Manager mng )
{
Prove_Params_t * pParams = &mng->Params;
int RetValue, i;
// check if the target network is available
if ( mng->pTarget == NULL )
{ printf( "ABC_Solve: Target network is not derived by ABC_SolveInit().\n" ); return UNDETERMINED; }
// try to prove the miter using a number of techniques
if ( mng->mode )
RetValue = Abc_NtkMiterSat( mng->pTarget, (ABC_INT64_T)pParams->nMiteringLimitLast, (ABC_INT64_T)0, 0, NULL, NULL );
else
// RetValue = Abc_NtkMiterProve( &mng->pTarget, pParams ); // old CEC engine
RetValue = Abc_NtkIvyProve( &mng->pTarget, pParams ); // new CEC engine
// analyze the result
mng->pResult = ABC_TargetResAlloc( Abc_NtkCiNum(mng->pTarget) );
if ( RetValue == -1 )
mng->pResult->status = UNDETERMINED;
else if ( RetValue == 1 )
mng->pResult->status = UNSATISFIABLE;
else if ( RetValue == 0 )
{
mng->pResult->status = SATISFIABLE;
// create the array of PI names and values
for ( i = 0; i < mng->pResult->no_sig; i++ )
{
mng->pResult->names[i] = Extra_UtilStrsav( ABC_GetNodeName(mng, Abc_NtkCi(mng->pNtk, i)) );
mng->pResult->values[i] = mng->pTarget->pModel[i];
}
ABC_FREE( mng->pTarget->pModel );
}
else assert( 0 );
// delete the target
Abc_NtkDelete( mng->pTarget );
mng->pTarget = NULL;
// return the status
return mng->pResult->status;
}
/**Function*************************************************************
Synopsis [Derive BDD of the characteristic function.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Abc_ResBuildBdd( Abc_Ntk_t * pNtk, DdManager * dd )
{
Vec_Ptr_t * vNodes, * vBdds, * vLocals;
Abc_Obj_t * pObj, * pFanin;
DdNode * bFunc, * bPart, * bTemp, * bVar;
int i, k;
assert( Abc_NtkIsSopLogic(pNtk) );
assert( Abc_NtkCoNum(pNtk) <= 3 );
vBdds = Vec_PtrStart( Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachCi( pNtk, pObj, i )
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), Cudd_bddIthVar(dd, i) );
// create internal node BDDs
vNodes = Abc_NtkDfs( pNtk, 0 );
vLocals = Vec_PtrAlloc( 6 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
if ( Abc_ObjFaninNum(pObj) == 0 )
{
bFunc = Cudd_NotCond( Cudd_ReadOne(dd), Abc_SopIsConst0((char *)pObj->pData) ); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), bFunc );
continue;
}
Vec_PtrClear( vLocals );
Abc_ObjForEachFanin( pObj, pFanin, k )
Vec_PtrPush( vLocals, Vec_PtrEntry(vBdds, Abc_ObjId(pFanin)) );
bFunc = Abc_ConvertSopToBdd( dd, (char *)pObj->pData, (DdNode **)Vec_PtrArray(vLocals) ); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), bFunc );
}
Vec_PtrFree( vLocals );
// create char function
bFunc = Cudd_ReadOne( dd ); Cudd_Ref( bFunc );
Abc_NtkForEachCo( pNtk, pObj, i )
{
bVar = Cudd_bddIthVar( dd, i + Abc_NtkCiNum(pNtk) );
bTemp = (DdNode *)Vec_PtrEntry( vBdds, Abc_ObjFaninId0(pObj) );
bPart = Cudd_bddXnor( dd, bTemp, bVar ); Cudd_Ref( bPart );
bFunc = Cudd_bddAnd( dd, bTemp = bFunc, bPart ); Cudd_Ref( bFunc );
Cudd_RecursiveDeref( dd, bTemp );
Cudd_RecursiveDeref( dd, bPart );
}
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose )
{
Sym_Man_t * p;
int i, v;
// start the manager
p = ALLOC( Sym_Man_t, 1 );
memset( p, 0, sizeof(Sym_Man_t) );
p->pNtk = pNtk;
p->vNodes = Abc_NtkDfs( pNtk, 0 );
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimWords = SIM_NUM_WORDS(p->nInputs);
p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// symmetry info for each output
p->vMatrSymms = Vec_PtrStart( p->nOutputs );
p->vMatrNonSymms = Vec_PtrStart( p->nOutputs );
p->vPairsTotal = Vec_IntStart( p->nOutputs );
p->vPairsSym = Vec_IntStart( p->nOutputs );
p->vPairsNonSym = Vec_IntStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
{
p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
}
// temporary patterns
p->uPatRand = ALLOC( unsigned, p->nSimWords );
p->uPatCol = ALLOC( unsigned, p->nSimWords );
p->uPatRow = ALLOC( unsigned, p->nSimWords );
p->vVarsU = Vec_IntStart( 100 );
p->vVarsV = Vec_IntStart( 100 );
// compute supports
p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose );
p->vSupports = Vec_VecStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
for ( v = 0; v < p->nInputs; v++ )
if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) )
Vec_VecPush( p->vSupports, i, (void *)v );
return p;
}
/**Function*************************************************************
Synopsis [Creates miter for the sensitivity analysis.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkSensitivityMiter( Abc_Ntk_t * pNtk, int iVar )
{
Abc_Ntk_t * pMiter;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pNext, * pFanin, * pOutput, * pObjNew;
int i;
assert( Abc_NtkIsStrash(pNtk) );
assert( iVar < Abc_NtkCiNum(pNtk) );
// duplicate the network
pMiter = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 );
pMiter->pName = Extra_UtilStrsav(pNtk->pName);
pMiter->pSpec = Extra_UtilStrsav(pNtk->pSpec);
// assign the PIs
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = Abc_AigConst1(pMiter);
Abc_AigConst1(pNtk)->pData = Abc_AigConst1(pMiter);
Abc_NtkForEachCi( pNtk, pObj, i )
{
pObj->pCopy = Abc_NtkCreatePi( pMiter );
pObj->pData = pObj->pCopy;
}
/**Function*************************************************************
Synopsis [Computes structural supports.]
Description [Supports are returned as an array of bit strings, one
for each CO.]
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Sim_ComputeStrSupp( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vSuppStr;
Abc_Obj_t * pNode;
unsigned * pSimmNode, * pSimmNode1, * pSimmNode2;
int nSuppWords, i, k;
// allocate room for structural supports
nSuppWords = SIM_NUM_WORDS( Abc_NtkCiNum(pNtk) );
vSuppStr = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), nSuppWords, 1 );
// assign the structural support to the PIs
Abc_NtkForEachCi( pNtk, pNode, i )
Sim_SuppStrSetVar( vSuppStr, pNode, i );
// derive the structural supports of the internal nodes
Abc_NtkForEachNode( pNtk, pNode, i )
{
// if ( Abc_NodeIsConst(pNode) )
// continue;
pSimmNode = vSuppStr->pArray[ pNode->Id ];
pSimmNode1 = vSuppStr->pArray[ Abc_ObjFaninId0(pNode) ];
pSimmNode2 = vSuppStr->pArray[ Abc_ObjFaninId1(pNode) ];
for ( k = 0; k < nSuppWords; k++ )
pSimmNode[k] = pSimmNode1[k] | pSimmNode2[k];
}
/**Function*************************************************************
Synopsis [Computes symmetries for a single output function.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Sim_SymmsStructCompute( Abc_Ntk_t * pNtk, Vec_Ptr_t * vMatrs, Vec_Ptr_t * vSuppFun )
{
Vec_Ptr_t * vNodes;
Abc_Obj_t * pTemp;
int * pMap, i;
assert( Abc_NtkCiNum(pNtk) + 10 < (1<<16) );
// get the structural support
pNtk->vSupps = Sim_ComputeStrSupp( pNtk );
// set elementary info for the CIs
Abc_NtkForEachCi( pNtk, pTemp, i )
SIM_SET_SYMMS( pTemp, Vec_IntAlloc(0) );
// create the map of CI ids into their numbers
pMap = Sim_SymmsCreateMap( pNtk );
// collect the nodes in the TFI cone of this output
vNodes = Abc_NtkDfs( pNtk, 0 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pTemp, i )
{
// if ( Abc_NodeIsConst(pTemp) )
// continue;
Sim_SymmsStructComputeOne( pNtk, pTemp, pMap );
}
/**Function*************************************************************
Synopsis [Load the network into FPGA manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Fpga_Man_t * Abc_NtkToFpga( Abc_Ntk_t * pNtk, int fRecovery, float * pSwitching, int fLatchPaths, int fVerbose )
{
Fpga_Man_t * pMan;
ProgressBar * pProgress;
Fpga_Node_t * pNodeFpga;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNode, * pFanin, * pPrev;
float * pfArrivals;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Fpga_ManCreate( Abc_NtkCiNum(pNtk), Abc_NtkCoNum(pNtk), fVerbose );
if ( pMan == NULL )
return NULL;
Fpga_ManSetAreaRecovery( pMan, fRecovery );
Fpga_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
pfArrivals = Abc_NtkGetCiArrivalFloats(pNtk);
if ( fLatchPaths )
{
for ( i = 0; i < Abc_NtkPiNum(pNtk); i++ )
pfArrivals[i] = -FPGA_FLOAT_LARGE;
}
Fpga_ManSetInputArrivals( pMan, pfArrivals );
// create PIs and remember them in the old nodes
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Fpga_ManReadConst1(pMan);
Abc_NtkForEachCi( pNtk, pNode, i )
{
pNodeFpga = Fpga_ManReadInputs(pMan)[i];
pNode->pCopy = (Abc_Obj_t *)pNodeFpga;
if ( pSwitching )
Fpga_NodeSetSwitching( pNodeFpga, pSwitching[pNode->Id] );
}
/**Function*************************************************************
Synopsis [Checks the integrity of the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkDoCheck( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj, * pNet, * pNode;
int i;
// check network types
if ( !Abc_NtkIsNetlist(pNtk) && !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown network type.\n" );
return 0;
}
if ( !Abc_NtkHasSop(pNtk) && !Abc_NtkHasBdd(pNtk) && !Abc_NtkHasAig(pNtk) && !Abc_NtkHasMapping(pNtk) && !Abc_NtkHasBlifMv(pNtk) && !Abc_NtkHasBlackbox(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown functionality type.\n" );
return 0;
}
if ( Abc_NtkHasMapping(pNtk) )
{
if ( pNtk->pManFunc != Abc_FrameReadLibGen() )
{
fprintf( stdout, "NetworkCheck: The library of the mapped network is not the global library.\n" );
return 0;
}
}
if ( Abc_NtkHasOnlyLatchBoxes(pNtk) )
{
// check CI/CO numbers
if ( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCiNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of CIs does not match number of PIs and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
if ( Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCoNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of COs does not match number of POs, asserts, and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
}
// check the names
if ( !Abc_NtkCheckNames( pNtk ) )
return 0;
// check PIs and POs
Abc_NtkCleanCopy( pNtk );
if ( !Abc_NtkCheckPis( pNtk ) )
return 0;
if ( !Abc_NtkCheckPos( pNtk ) )
return 0;
if ( Abc_NtkHasBlackbox(pNtk) )
return 1;
// check the connectivity of objects
Abc_NtkForEachObj( pNtk, pObj, i )
if ( !Abc_NtkCheckObj( pNtk, pObj ) )
return 0;
// if it is a netlist change nets and latches
if ( Abc_NtkIsNetlist(pNtk) )
{
if ( Abc_NtkNetNum(pNtk) == 0 )
fprintf( stdout, "NetworkCheck: Warning! Netlist has no nets.\n" );
// check the nets
Abc_NtkForEachNet( pNtk, pNet, i )
if ( !Abc_NtkCheckNet( pNtk, pNet ) )
return 0;
}
else
{
if ( Abc_NtkNetNum(pNtk) != 0 )
/**Function*************************************************************
Synopsis [Attempts to solve the miter using a number of tricks.]
Description [Returns -1 if timed out; 0 if SAT; 1 if UNSAT. Returns
a simplified version of the original network (or a constant 0 network).
In case the network is not a constant zero and a SAT assignment is found,
pNtk->pModel contains a satisfying assignment.]
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkMiterProve( Abc_Ntk_t ** ppNtk, void * pPars )
{
Prove_Params_t * pParams = pPars;
Abc_Ntk_t * pNtk, * pNtkTemp;
int RetValue, nIter, nSatFails, Counter, clk, timeStart = clock();
sint64 nSatConfs, nSatInspects, nInspectLimit;
// get the starting network
pNtk = *ppNtk;
assert( Abc_NtkIsStrash(pNtk) );
assert( Abc_NtkPoNum(pNtk) == 1 );
if ( pParams->fVerbose )
{
printf( "RESOURCE LIMITS: Iterations = %d. Rewriting = %s. Fraiging = %s.\n",
pParams->nItersMax, pParams->fUseRewriting? "yes":"no", pParams->fUseFraiging? "yes":"no" );
printf( "Mitering = %d (%3.1f). Rewriting = %d (%3.1f). Fraiging = %d (%3.1f).\n",
pParams->nMiteringLimitStart, pParams->nMiteringLimitMulti,
pParams->nRewritingLimitStart, pParams->nRewritingLimitMulti,
pParams->nFraigingLimitStart, pParams->nFraigingLimitMulti );
printf( "Mitering last = %d.\n",
pParams->nMiteringLimitLast );
}
// if SAT only, solve without iteration
if ( !pParams->fUseRewriting && !pParams->fUseFraiging )
{
clk = clock();
RetValue = Abc_NtkMiterSat( pNtk, (sint64)pParams->nMiteringLimitLast, (sint64)0, 0, NULL, NULL );
Abc_NtkMiterPrint( pNtk, "SAT solving", clk, pParams->fVerbose );
*ppNtk = pNtk;
return RetValue;
}
// check the current resource limits
for ( nIter = 0; nIter < pParams->nItersMax; nIter++ )
{
if ( pParams->fVerbose )
{
printf( "ITERATION %2d : Confs = %6d. FraigBTL = %3d. \n", nIter+1,
(int)(pParams->nMiteringLimitStart * pow(pParams->nMiteringLimitMulti,nIter)),
(int)(pParams->nFraigingLimitStart * pow(pParams->nFraigingLimitMulti,nIter)) );
fflush( stdout );
}
// try brute-force SAT
clk = clock();
nInspectLimit = pParams->nTotalInspectLimit? pParams->nTotalInspectLimit - pParams->nTotalInspectsMade : 0;
RetValue = Abc_NtkMiterSat( pNtk, (sint64)(pParams->nMiteringLimitStart * pow(pParams->nMiteringLimitMulti,nIter)), (sint64)nInspectLimit, 0, &nSatConfs, &nSatInspects );
Abc_NtkMiterPrint( pNtk, "SAT solving", clk, pParams->fVerbose );
if ( RetValue >= 0 )
break;
// add to the number of backtracks and inspects
pParams->nTotalBacktracksMade += nSatConfs;
pParams->nTotalInspectsMade += nSatInspects;
// check if global resource limit is reached
if ( (pParams->nTotalBacktrackLimit && pParams->nTotalBacktracksMade >= pParams->nTotalBacktrackLimit) ||
(pParams->nTotalInspectLimit && pParams->nTotalInspectsMade >= pParams->nTotalInspectLimit) )
{
printf( "Reached global limit on conflicts/inspects. Quitting.\n" );
*ppNtk = pNtk;
return -1;
}
// try rewriting
if ( pParams->fUseRewriting )
{
clk = clock();
Counter = (int)(pParams->nRewritingLimitStart * pow(pParams->nRewritingLimitMulti,nIter));
// Counter = 1;
while ( 1 )
{
/*
extern Abc_Ntk_t * Abc_NtkIvyResyn( Abc_Ntk_t * pNtk, int fUpdateLevel, int fVerbose );
pNtk = Abc_NtkIvyResyn( pNtkTemp = pNtk, 0, 0 ); Abc_NtkDelete( pNtkTemp );
if ( (RetValue = Abc_NtkMiterIsConstant(pNtk)) >= 0 )
break;
if ( --Counter == 0 )
break;
*/
/*
Abc_NtkRewrite( pNtk, 0, 0, 0, 0, 0 );
if ( (RetValue = Abc_NtkMiterIsConstant(pNtk)) >= 0 )
break;
if ( --Counter == 0 )
break;
*/
Abc_NtkRewrite( pNtk, 0, 0, 0, 0, 0 );
if ( (RetValue = Abc_NtkMiterIsConstant(pNtk)) >= 0 )
break;
if ( --Counter == 0 )
break;
Abc_NtkRefactor( pNtk, 10, 16, 0, 0, 0, 0 );
if ( (RetValue = Abc_NtkMiterIsConstant(pNtk)) >= 0 )
break;
if ( --Counter == 0 )
break;
pNtk = Abc_NtkBalance( pNtkTemp = pNtk, 0, 0, 0 ); Abc_NtkDelete( pNtkTemp );
if ( (RetValue = Abc_NtkMiterIsConstant(pNtk)) >= 0 )
break;
if ( --Counter == 0 )
break;
}
Abc_NtkMiterPrint( pNtk, "Rewriting ", clk, pParams->fVerbose );
}
if ( pParams->fUseFraiging )
{
// try FRAIGing
clk = clock();
nInspectLimit = pParams->nTotalInspectLimit? pParams->nTotalInspectLimit - pParams->nTotalInspectsMade : 0;
pNtk = Abc_NtkMiterFraig( pNtkTemp = pNtk, (int)(pParams->nFraigingLimitStart * pow(pParams->nFraigingLimitMulti,nIter)), nInspectLimit, &RetValue, &nSatFails, &nSatConfs, &nSatInspects ); Abc_NtkDelete( pNtkTemp );
Abc_NtkMiterPrint( pNtk, "FRAIGing ", clk, pParams->fVerbose );
// printf( "NumFails = %d\n", nSatFails );
if ( RetValue >= 0 )
break;
// add to the number of backtracks and inspects
pParams->nTotalBacktracksMade += nSatConfs;
pParams->nTotalInspectsMade += nSatInspects;
// check if global resource limit is reached
if ( (pParams->nTotalBacktrackLimit && pParams->nTotalBacktracksMade >= pParams->nTotalBacktrackLimit) ||
(pParams->nTotalInspectLimit && pParams->nTotalInspectsMade >= pParams->nTotalInspectLimit) )
{
printf( "Reached global limit on conflicts/inspects. Quitting.\n" );
*ppNtk = pNtk;
return -1;
}
}
}
// try to prove it using brute force SAT
if ( RetValue < 0 && pParams->fUseBdds )
{
if ( pParams->fVerbose )
{
printf( "Attempting BDDs with node limit %d ...\n", pParams->nBddSizeLimit );
fflush( stdout );
}
clk = clock();
pNtk = Abc_NtkCollapse( pNtkTemp = pNtk, pParams->nBddSizeLimit, 0, pParams->fBddReorder, 0 );
if ( pNtk )
{
Abc_NtkDelete( pNtkTemp );
RetValue = ( (Abc_NtkNodeNum(pNtk) == 1) && (Abc_ObjFanin0(Abc_NtkPo(pNtk,0))->pData == Cudd_ReadLogicZero(pNtk->pManFunc)) );
}
else
pNtk = pNtkTemp;
Abc_NtkMiterPrint( pNtk, "BDD building", clk, pParams->fVerbose );
}
if ( RetValue < 0 )
{
if ( pParams->fVerbose )
{
printf( "Attempting SAT with conflict limit %d ...\n", pParams->nMiteringLimitLast );
fflush( stdout );
}
clk = clock();
nInspectLimit = pParams->nTotalInspectLimit? pParams->nTotalInspectLimit - pParams->nTotalInspectsMade : 0;
RetValue = Abc_NtkMiterSat( pNtk, (sint64)pParams->nMiteringLimitLast, (sint64)nInspectLimit, 0, NULL, NULL );
Abc_NtkMiterPrint( pNtk, "SAT solving", clk, pParams->fVerbose );
}
// assign the model if it was proved by rewriting (const 1 miter)
if ( RetValue == 0 && pNtk->pModel == NULL )
{
pNtk->pModel = ALLOC( int, Abc_NtkCiNum(pNtk) );
memset( pNtk->pModel, 0, sizeof(int) * Abc_NtkCiNum(pNtk) );
}
{
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj;
int i;
Abc_NtkCleanCopy( pNtk );
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->iTemp = i;
vNodes = Vec_PtrAlloc( Abc_NtkNodeNum(pNtk) );
Abc_NtkForEachNode( pNtk, pObj, i )
{
pObj->iTemp = Abc_NtkCiNum(pNtk) + Vec_PtrSize(vNodes);
Vec_PtrPush( vNodes, pObj );
}
assert( Vec_PtrSize(vNodes) == Abc_NtkNodeNum(pNtk) );
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->iTemp = Abc_NtkCiNum(pNtk) + Vec_PtrSize(vNodes) + i;
return vNodes;
}
/**Function*************************************************************
Synopsis [Extracts information about the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sfm_Ntk_t * Abc_NtkExtractMfs( Abc_Ntk_t * pNtk, int nFirstFixed )
/**Function*************************************************************
Synopsis [Load the network into manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Map_Man_t * Abc_NtkToMap( Abc_Ntk_t * pNtk, double DelayTarget, int fRecovery, float * pSwitching, int fVerbose )
{
Map_Man_t * pMan;
Map_Node_t * pNodeMap;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNode, * pFanin, * pPrev;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Map_ManCreate( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) - pNtk->nBarBufs, Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk) - pNtk->nBarBufs, fVerbose );
if ( pMan == NULL )
return NULL;
Map_ManSetAreaRecovery( pMan, fRecovery );
Map_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
Map_ManSetDelayTarget( pMan, (float)DelayTarget );
Map_ManSetInputArrivals( pMan, Abc_NtkMapCopyCiArrival(pNtk, Abc_NtkGetCiArrivalTimes(pNtk)) );
Map_ManSetOutputRequireds( pMan, Abc_NtkMapCopyCoRequired(pNtk, Abc_NtkGetCoRequiredTimes(pNtk)) );
// create PIs and remember them in the old nodes
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Map_ManReadConst1(pMan);
Abc_NtkForEachCi( pNtk, pNode, i )
{
if ( i == Abc_NtkCiNum(pNtk) - pNtk->nBarBufs )
break;
pNodeMap = Map_ManReadInputs(pMan)[i];
pNode->pCopy = (Abc_Obj_t *)pNodeMap;
if ( pSwitching )
Map_NodeSetSwitching( pNodeMap, pSwitching[pNode->Id] );
}
// load the AIG into the mapper
vNodes = Abc_AigDfsMap( pNtk );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNode, i )
{
if ( Abc_ObjIsLatch(pNode) )
{
pFanin = Abc_ObjFanin0(pNode);
pNodeMap = Map_NodeBuf( pMan, Map_NotCond( Abc_ObjFanin0(pFanin)->pCopy, (int)Abc_ObjFaninC0(pFanin) ) );
Abc_ObjFanout0(pNode)->pCopy = (Abc_Obj_t *)pNodeMap;
continue;
}
assert( Abc_ObjIsNode(pNode) );
// add the node to the mapper
pNodeMap = Map_NodeAnd( pMan,
Map_NotCond( Abc_ObjFanin0(pNode)->pCopy, (int)Abc_ObjFaninC0(pNode) ),
Map_NotCond( Abc_ObjFanin1(pNode)->pCopy, (int)Abc_ObjFaninC1(pNode) ) );
assert( pNode->pCopy == NULL );
// remember the node
pNode->pCopy = (Abc_Obj_t *)pNodeMap;
if ( pSwitching )
Map_NodeSetSwitching( pNodeMap, pSwitching[pNode->Id] );
// set up the choice node
if ( Abc_AigNodeIsChoice( pNode ) )
for ( pPrev = pNode, pFanin = (Abc_Obj_t *)pNode->pData; pFanin; pPrev = pFanin, pFanin = (Abc_Obj_t *)pFanin->pData )
{
Map_NodeSetNextE( (Map_Node_t *)pPrev->pCopy, (Map_Node_t *)pFanin->pCopy );
Map_NodeSetRepr( (Map_Node_t *)pFanin->pCopy, (Map_Node_t *)pNode->pCopy );
}
}
assert( Map_ManReadBufNum(pMan) == pNtk->nBarBufs );
Vec_PtrFree( vNodes );
// set the primary outputs in the required phase
Abc_NtkForEachCo( pNtk, pNode, i )
{
if ( i == Abc_NtkCoNum(pNtk) - pNtk->nBarBufs )
break;
Map_ManReadOutputs(pMan)[i] = Map_NotCond( (Map_Node_t *)Abc_ObjFanin0(pNode)->pCopy, (int)Abc_ObjFaninC0(pNode) );
}
return pMan;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose )
{
Sym_Man_t * p;
int i, v;
// start the manager
p = ABC_ALLOC( Sym_Man_t, 1 );
memset( p, 0, sizeof(Sym_Man_t) );
p->pNtk = pNtk;
p->vNodes = Abc_NtkDfs( pNtk, 0 );
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimWords = SIM_NUM_WORDS(p->nInputs);
p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// symmetry info for each output
p->vMatrSymms = Vec_PtrStart( p->nOutputs );
p->vMatrNonSymms = Vec_PtrStart( p->nOutputs );
p->vPairsTotal = Vec_IntStart( p->nOutputs );
p->vPairsSym = Vec_IntStart( p->nOutputs );
p->vPairsNonSym = Vec_IntStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
{
p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
}
// temporary patterns
p->uPatRand = ABC_ALLOC( unsigned, p->nSimWords );
p->uPatCol = ABC_ALLOC( unsigned, p->nSimWords );
p->uPatRow = ABC_ALLOC( unsigned, p->nSimWords );
p->vVarsU = Vec_IntStart( 100 );
p->vVarsV = Vec_IntStart( 100 );
// compute supports
p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose );
p->vSupports = Vec_VecStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
for ( v = 0; v < p->nInputs; v++ )
if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) )
Vec_VecPush( p->vSupports, i, (void *)(ABC_PTRUINT_T)v );
return p;
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkMfs( Abc_Ntk_t * pNtk, Mfs_Par_t * pPars )
{
extern Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fExors, int fRegisters );
Bdc_Par_t Pars = {0}, * pDecPars = &Pars;
ProgressBar * pProgress;
Mfs_Man_t * p;
Abc_Obj_t * pObj;
Vec_Vec_t * vLevels;
Vec_Ptr_t * vNodes;
int i, k, nNodes, nFaninMax;
abctime clk = Abc_Clock(), clk2;
int nTotalNodesBeg = Abc_NtkNodeNum(pNtk);
int nTotalEdgesBeg = Abc_NtkGetTotalFanins(pNtk);
assert( Abc_NtkIsLogic(pNtk) );
nFaninMax = Abc_NtkGetFaninMax(pNtk);
if ( pPars->fResub )
{
if ( nFaninMax > 8 )
{
printf( "Nodes with more than %d fanins will not be processed.\n", 8 );
nFaninMax = 8;
}
}
else
{
if ( nFaninMax > MFS_FANIN_MAX )
{
printf( "Nodes with more than %d fanins will not be processed.\n", MFS_FANIN_MAX );
nFaninMax = MFS_FANIN_MAX;
}
}
// perform the network sweep
// Abc_NtkSweep( pNtk, 0 );
// convert into the AIG
if ( !Abc_NtkToAig(pNtk) )
{
fprintf( stdout, "Converting to AIGs has failed.\n" );
return 0;
}
assert( Abc_NtkHasAig(pNtk) );
// start the manager
p = Mfs_ManAlloc( pPars );
p->pNtk = pNtk;
p->nFaninMax = nFaninMax;
// precomputer power-aware metrics
if ( pPars->fPower )
{
extern Vec_Int_t * Abc_NtkPowerEstimate( Abc_Ntk_t * pNtk, int fProbOne );
if ( pPars->fResub )
p->vProbs = Abc_NtkPowerEstimate( pNtk, 0 );
else
p->vProbs = Abc_NtkPowerEstimate( pNtk, 1 );
#if 0
printf( "Total switching before = %7.2f.\n", Abc_NtkMfsTotalSwitching(pNtk) );
#else
p->TotalSwitchingBeg = Abc_NtkMfsTotalSwitching(pNtk);
#endif
}
if ( pNtk->pExcare )
{
Abc_Ntk_t * pTemp;
if ( Abc_NtkPiNum((Abc_Ntk_t *)pNtk->pExcare) != Abc_NtkCiNum(pNtk) )
printf( "The PI count of careset (%d) and logic network (%d) differ. Careset is not used.\n",
Abc_NtkPiNum((Abc_Ntk_t *)pNtk->pExcare), Abc_NtkCiNum(pNtk) );
else
{
pTemp = Abc_NtkStrash( (Abc_Ntk_t *)pNtk->pExcare, 0, 0, 0 );
p->pCare = Abc_NtkToDar( pTemp, 0, 0 );
Abc_NtkDelete( pTemp );
p->vSuppsInv = Aig_ManSupportsInverse( p->pCare );
}
}
if ( p->pCare != NULL )
printf( "Performing optimization with %d external care clauses.\n", Aig_ManCoNum(p->pCare) );
// prepare the BDC manager
if ( !pPars->fResub )
{
pDecPars->nVarsMax = (nFaninMax < 3) ? 3 : nFaninMax;
pDecPars->fVerbose = pPars->fVerbose;
p->vTruth = Vec_IntAlloc( 0 );
p->pManDec = Bdc_ManAlloc( pDecPars );
}
// label the register outputs
if ( p->pCare )
{
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pData = (void *)(ABC_PTRUINT_T)i;
}
// compute levels
Abc_NtkLevel( pNtk );
Abc_NtkStartReverseLevels( pNtk, pPars->nGrowthLevel );
// compute don't-cares for each node
nNodes = 0;
p->nTotalNodesBeg = nTotalNodesBeg;
p->nTotalEdgesBeg = nTotalEdgesBeg;
if ( pPars->fResub )
{
#if 0
printf( "TotalSwitching (%7.2f --> ", Abc_NtkMfsTotalSwitching(pNtk) );
#endif
if (pPars->fPower)
{
Abc_NtkMfsPowerResub( p, pPars);
} else
{
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachNode( pNtk, pObj, i )
{
if ( p->pPars->nDepthMax && (int)pObj->Level > p->pPars->nDepthMax )
continue;
if ( Abc_ObjFaninNum(pObj) < 2 || Abc_ObjFaninNum(pObj) > nFaninMax )
continue;
if ( !p->pPars->fVeryVerbose )
Extra_ProgressBarUpdate( pProgress, i, NULL );
if ( pPars->fResub )
Abc_NtkMfsResub( p, pObj );
else
Abc_NtkMfsNode( p, pObj );
}
Extra_ProgressBarStop( pProgress );
#if 0
printf( " %7.2f )\n", Abc_NtkMfsTotalSwitching(pNtk) );
#endif
}
} else
