/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTestPinGia( Abc_Ntk_t * pNtk, int fWhiteBoxOnly, int fVerbose )
{
Gia_Man_t * pGia;
char * pFileName = "testpin.aig";
pGia = Abc_NtkTestPinDeriveGia( pNtk, fWhiteBoxOnly, fVerbose );
Gia_AigerWrite( pGia, pFileName, 0, 0 );
Gia_ManStop( pGia );
printf( "AIG with pins derived from mapped network \"%s\" was written into file \"%s\".\n",
Abc_NtkName(pNtk), pFileName );
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
//extern Abc_Des_t * Ver_ParseFile( char * pFileName, Abc_Des_t * pGateLib, int fCheck, int fUseMemMan );
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Reads hierarchical design from the Verilog file.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
{
Abc_Ntk_t * pNtk, * pTemp;
Abc_Des_t * pDesign;
int i, RetValue;
// parse the verilog file
pDesign = Ver_ParseFile( pFileName, NULL, fCheck, 1 );
if ( pDesign == NULL )
return NULL;
// detect top-level model
RetValue = Abc_DesFindTopLevelModels( pDesign );
pNtk = (Abc_Ntk_t *)Vec_PtrEntry( pDesign->vTops, 0 );
if ( RetValue > 1 )
{
printf( "Warning: The design has %d root-level modules: ", Vec_PtrSize(pDesign->vTops) );
Vec_PtrForEachEntry( Abc_Ntk_t *, pDesign->vTops, pTemp, i )
printf( " %s", Abc_NtkName(pTemp) );
printf( "\n" );
printf( "The first one (%s) will be used.\n", pNtk->pName );
}
ABC_NAMESPACE_IMPL_START
// For description of Binary BLIF format, refer to "abc/src/aig/bbl/bblif.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Fnction*************************************************************
Synopsis [Construct manager from the ABC network.]
Description [In the ABC network each object has a unique integer ID.
This ID is used when we construct objects of the BBLIF manager
corresponding to each object of the ABC network. The objects can be
added to the manager in any order (although below they are added in the
topological order), but by the time fanin/fanout connections are created,
corresponding objects are already constructed. In the end the checking
procedure is called.]
SideEffects []
SeeAlso []
***********************************************************************/
Bbl_Man_t * Bbl_ManFromAbc( Abc_Ntk_t * pNtk )
{
Bbl_Man_t * p;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pFanin;
int i, k;
assert( Abc_NtkIsSopLogic(pNtk) );
// start the data manager
p = Bbl_ManStart( Abc_NtkName(pNtk) );
// collect internal nodes to be added
vNodes = Abc_NtkDfs( pNtk, 0 );
// create combinational inputs
Abc_NtkForEachCi( pNtk, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_CI, Abc_ObjId(pObj), 0, NULL );
// create internal nodes
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_NODE, Abc_ObjId(pObj), Abc_ObjFaninNum(pObj), (char *)pObj->pData );
// create combinational outputs
Abc_NtkForEachCo( pNtk, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_CO, Abc_ObjId(pObj), 1, NULL );
// create fanin/fanout connections for internal nodes
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
Bbl_ManAddFanin( p, Abc_ObjId(pObj), Abc_ObjId(pFanin) );
// create fanin/fanout connections for combinational outputs
Abc_NtkForEachCo( pNtk, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
Bbl_ManAddFanin( p, Abc_ObjId(pObj), Abc_ObjId(pFanin) );
Vec_PtrFree( vNodes );
// sanity check
Bbl_ManCheck( p );
return p;
}
