static void
AeHardwareInterfaces (
void)
{
ACPI_STATUS Status;
UINT32 Value;
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, 1);
AE_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_GLOBAL_LOCK_ENABLE, 1);
AE_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_SLEEP_ENABLE, 1);
AE_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 1);
AE_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &Value);
AE_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_GLOBAL_LOCK_ENABLE, &Value);
AE_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_SLEEP_ENABLE, &Value);
AE_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_ARB_DISABLE, &Value);
AE_CHECK_OK (AcpiReadBitRegister, Status);
}
ACPI_STATUS
AcpiGetEventStatus (
UINT32 Event,
ACPI_EVENT_STATUS *EventStatus)
{
ACPI_STATUS Status = AE_OK;
ACPI_FUNCTION_TRACE (AcpiGetEventStatus);
if (!EventStatus)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/* Decode the Fixed Event */
if (Event > ACPI_EVENT_MAX)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/* Get the status of the requested fixed event */
Status = AcpiReadBitRegister (
AcpiGbl_FixedEventInfo[Event].StatusRegisterId, EventStatus);
return_ACPI_STATUS (Status);
}
UINT32
AcpiHwGetMode (
void)
{
ACPI_STATUS Status;
UINT32 Value;
ACPI_FUNCTION_TRACE (HwGetMode);
/*
* ACPI 2.0 clarified that if SMI_CMD in FADT is zero,
* system does not support mode transition.
*/
if (!AcpiGbl_FADT.SmiCommand)
{
return_UINT32 (ACPI_SYS_MODE_ACPI);
}
Status = AcpiReadBitRegister (ACPI_BITREG_SCI_ENABLE, &Value);
if (ACPI_FAILURE (Status))
{
return_UINT32 (ACPI_SYS_MODE_LEGACY);
}
if (Value)
{
return_UINT32 (ACPI_SYS_MODE_ACPI);
}
else
{
return_UINT32 (ACPI_SYS_MODE_LEGACY);
}
}
ACPI_STATUS
AcpiEnterSleepStateS4bios (
void)
{
UINT32 InValue;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (AcpiEnterSleepStateS4bios);
/* Clear the wake status bit (PM1) */
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
Status = AcpiHwClearAcpiStatus ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/*
* 1) Disable/Clear all GPEs
* 2) Enable all wakeup GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
Status = AcpiHwEnableAllWakeupGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
ACPI_FLUSH_CPU_CACHE ();
Status = AcpiHwWritePort (AcpiGbl_FADT.SmiCommand,
(UINT32) AcpiGbl_FADT.S4BiosRequest, 8);
do {
AcpiOsStall (ACPI_USEC_PER_MSEC);
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &InValue);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
} while (!InValue);
return_ACPI_STATUS (AE_OK);
}
static void
AeHardwareInterfaces (
void)
{
#if (!ACPI_REDUCED_HARDWARE)
ACPI_STATUS Status;
UINT32 Value;
/* If Hardware Reduced flag is set, we are all done */
if (AcpiGbl_ReducedHardware)
{
return;
}
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, 1);
ACPI_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_GLOBAL_LOCK_ENABLE, 1);
ACPI_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_SLEEP_ENABLE, 1);
ACPI_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 1);
ACPI_CHECK_OK (AcpiWriteBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &Value);
ACPI_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_GLOBAL_LOCK_ENABLE, &Value);
ACPI_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_SLEEP_ENABLE, &Value);
ACPI_CHECK_OK (AcpiReadBitRegister, Status);
Status = AcpiReadBitRegister (ACPI_BITREG_ARB_DISABLE, &Value);
ACPI_CHECK_OK (AcpiReadBitRegister, Status);
#endif /* !ACPI_REDUCED_HARDWARE */
}
ACPI_STATUS
AcpiEnableEvent (
UINT32 Event,
UINT32 Flags)
{
ACPI_STATUS Status = AE_OK;
UINT32 Value;
ACPI_FUNCTION_TRACE (AcpiEnableEvent);
/* If Hardware Reduced flag is set, there are no fixed events */
if (AcpiGbl_ReducedHardware)
{
return_ACPI_STATUS (AE_OK);
}
/* Decode the Fixed Event */
if (Event > ACPI_EVENT_MAX)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/*
* Enable the requested fixed event (by writing a one to the enable
* register bit)
*/
Status = AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId,
ACPI_ENABLE_EVENT);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Make sure that the hardware responded */
Status = AcpiReadBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId, &Value);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (Value != 1)
{
ACPI_ERROR ((AE_INFO,
"Could not enable %s event", AcpiUtGetEventName (Event)));
return_ACPI_STATUS (AE_NO_HARDWARE_RESPONSE);
}
return_ACPI_STATUS (Status);
}
static bool
acpicpu_cstate_bm_check(void)
{
uint32_t val = 0;
ACPI_STATUS rv;
rv = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &val);
if (ACPI_FAILURE(rv) || val == 0)
return false;
(void)AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
return true;
}
ACPI_STATUS
AcpiDisableEvent (
UINT32 Event,
UINT32 Flags)
{
ACPI_STATUS Status = AE_OK;
UINT32 Value;
ACPI_FUNCTION_TRACE (AcpiDisableEvent);
/* Decode the Fixed Event */
if (Event > ACPI_EVENT_MAX)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/*
* Disable the requested fixed event (by writing a zero to the enable
* register bit)
*/
Status = AcpiWriteBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId,
ACPI_DISABLE_EVENT);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
Status = AcpiReadBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId, &Value);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (Value != 0)
{
ACPI_ERROR ((AE_INFO,
"Could not disable %s events", AcpiUtGetEventName (Event)));
return_ACPI_STATUS (AE_NO_HARDWARE_RESPONSE);
}
return_ACPI_STATUS (Status);
}
ACPI_STATUS
AcpiHwLegacySleep (
UINT8 SleepState)
{
ACPI_BIT_REGISTER_INFO *SleepTypeRegInfo;
ACPI_BIT_REGISTER_INFO *SleepEnableRegInfo;
UINT32 Pm1aControl;
UINT32 Pm1bControl;
UINT32 InValue;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (HwLegacySleep);
SleepTypeRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_TYPE);
SleepEnableRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_ENABLE);
/* Clear wake status */
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Clear all fixed and general purpose status bits */
Status = AcpiHwClearAcpiStatus ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/*
* 1) Disable/Clear all GPEs
* 2) Enable all wakeup GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
Status = AcpiHwEnableAllWakeupGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Get current value of PM1A control */
Status = AcpiHwRegisterRead (ACPI_REGISTER_PM1_CONTROL,
&Pm1aControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
ACPI_DEBUG_PRINT ((ACPI_DB_INIT,
"Entering sleep state [S%u]\n", SleepState));
/* Clear the SLP_EN and SLP_TYP fields */
Pm1aControl &= ~(SleepTypeRegInfo->AccessBitMask |
SleepEnableRegInfo->AccessBitMask);
Pm1bControl = Pm1aControl;
/* Insert the SLP_TYP bits */
Pm1aControl |= (AcpiGbl_SleepTypeA << SleepTypeRegInfo->BitPosition);
Pm1bControl |= (AcpiGbl_SleepTypeB << SleepTypeRegInfo->BitPosition);
/*
* We split the writes of SLP_TYP and SLP_EN to workaround
* poorly implemented hardware.
*/
/* Write #1: write the SLP_TYP data to the PM1 Control registers */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Insert the sleep enable (SLP_EN) bit */
Pm1aControl |= SleepEnableRegInfo->AccessBitMask;
Pm1bControl |= SleepEnableRegInfo->AccessBitMask;
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE ();
/* Write #2: Write both SLP_TYP + SLP_EN */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState > ACPI_STATE_S3)
{
/*
* We wanted to sleep > S3, but it didn't happen (by virtue of the
* fact that we are still executing!)
*
* Wait ten seconds, then try again. This is to get S4/S5 to work on
* all machines.
*
* We wait so long to allow chipsets that poll this reg very slowly
* to still read the right value. Ideally, this block would go
* away entirely.
*/
AcpiOsStall (10 * ACPI_USEC_PER_SEC);
Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_CONTROL,
SleepEnableRegInfo->AccessBitMask);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
}
/* Wait for transition back to Working State */
do
{
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &InValue);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
} while (!InValue);
return_ACPI_STATUS (AE_OK);
}
ACPI_STATUS
AcpiEnterSleepState (
UINT8 SleepState)
{
UINT32 Pm1aControl;
UINT32 Pm1bControl;
ACPI_BIT_REGISTER_INFO *SleepTypeRegInfo;
ACPI_BIT_REGISTER_INFO *SleepEnableRegInfo;
UINT32 InValue;
ACPI_OBJECT_LIST ArgList;
ACPI_OBJECT Arg;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (AcpiEnterSleepState);
if ((AcpiGbl_SleepTypeA > ACPI_SLEEP_TYPE_MAX) ||
(AcpiGbl_SleepTypeB > ACPI_SLEEP_TYPE_MAX))
{
ACPI_ERROR ((AE_INFO, "Sleep values out of range: A=%X B=%X",
AcpiGbl_SleepTypeA, AcpiGbl_SleepTypeB));
return_ACPI_STATUS (AE_AML_OPERAND_VALUE);
}
SleepTypeRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_TYPE);
SleepEnableRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_ENABLE);
/* Clear wake status */
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Clear all fixed and general purpose status bits */
Status = AcpiHwClearAcpiStatus ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState != ACPI_STATE_S5)
{
/*
* Disable BM arbitration. This feature is contained within an
* optional register (PM2 Control), so ignore a BAD_ADDRESS
* exception.
*/
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 1);
if (ACPI_FAILURE (Status) && (Status != AE_BAD_ADDRESS))
{
return_ACPI_STATUS (Status);
}
}
/*
* 1) Disable/Clear all GPEs
* 2) Enable all wakeup GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
Status = AcpiHwEnableAllWakeupGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Execute the _GTS method (Going To Sleep) */
ArgList.Count = 1;
ArgList.Pointer = &Arg;
Arg.Type = ACPI_TYPE_INTEGER;
Arg.Integer.Value = SleepState;
Status = AcpiEvaluateObject (NULL, METHOD_NAME__GTS, &ArgList, NULL);
if (ACPI_FAILURE (Status) && Status != AE_NOT_FOUND)
{
return_ACPI_STATUS (Status);
}
/* Get current value of PM1A control */
Status = AcpiHwRegisterRead (ACPI_REGISTER_PM1_CONTROL,
&Pm1aControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
ACPI_DEBUG_PRINT ((ACPI_DB_INIT,
"Entering sleep state [S%d]\n", SleepState));
/* Clear the SLP_EN and SLP_TYP fields */
Pm1aControl &= ~(SleepTypeRegInfo->AccessBitMask |
SleepEnableRegInfo->AccessBitMask);
Pm1bControl = Pm1aControl;
/* Insert the SLP_TYP bits */
Pm1aControl |= (AcpiGbl_SleepTypeA << SleepTypeRegInfo->BitPosition);
Pm1bControl |= (AcpiGbl_SleepTypeB << SleepTypeRegInfo->BitPosition);
/*
* We split the writes of SLP_TYP and SLP_EN to workaround
* poorly implemented hardware.
*/
/* Write #1: write the SLP_TYP data to the PM1 Control registers */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Insert the sleep enable (SLP_EN) bit */
Pm1aControl |= SleepEnableRegInfo->AccessBitMask;
Pm1bControl |= SleepEnableRegInfo->AccessBitMask;
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE ();
/* Write #2: Write both SLP_TYP + SLP_EN */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState > ACPI_STATE_S3)
{
/*
* We wanted to sleep > S3, but it didn't happen (by virtue of the
* fact that we are still executing!)
*
* Wait ten seconds, then try again. This is to get S4/S5 to work on
* all machines.
*
* We wait so long to allow chipsets that poll this reg very slowly
* to still read the right value. Ideally, this block would go
* away entirely.
*/
AcpiOsStall (10000000);
Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_CONTROL,
SleepEnableRegInfo->AccessBitMask);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
}
/* Wait until we enter sleep state */
do
{
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &InValue);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Spin until we wake */
} while (!InValue);
return_ACPI_STATUS (AE_OK);
}
static int
acpi_cpu_quirks(void)
{
device_t acpi_dev;
uint32_t val;
ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
/*
* Bus mastering arbitration control is needed to keep caches coherent
* while sleeping in C3. If it's not present but a working flush cache
* instruction is present, flush the caches before entering C3 instead.
* Otherwise, just disable C3 completely.
*/
if (AcpiGbl_FADT.Pm2ControlBlock == 0 ||
AcpiGbl_FADT.Pm2ControlLength == 0) {
if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) &&
(AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) {
cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: no BM control, using flush cache method\n"));
} else {
cpu_quirks |= CPU_QUIRK_NO_C3;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: no BM control, C3 not available\n"));
}
}
/*
* If we are using generic Cx mode, C3 on multiple CPUs requires using
* the expensive flush cache instruction.
*/
if (cpu_cx_generic && mp_ncpus > 1) {
cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: SMP, using flush cache mode for C3\n"));
}
/* Look for various quirks of the PIIX4 part. */
acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3);
if (acpi_dev != NULL) {
switch (pci_get_revid(acpi_dev)) {
/*
* Disable C3 support for all PIIX4 chipsets. Some of these parts
* do not report the BMIDE status to the BM status register and
* others have a livelock bug if Type-F DMA is enabled. Linux
* works around the BMIDE bug by reading the BM status directly
* but we take the simpler approach of disabling C3 for these
* parts.
*
* See erratum #18 ("C3 Power State/BMIDE and Type-F DMA
* Livelock") from the January 2002 PIIX4 specification update.
* Applies to all PIIX4 models.
*
* Also, make sure that all interrupts cause a "Stop Break"
* event to exit from C2 state.
* Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
* should be set to zero, otherwise it causes C2 to short-sleep.
* PIIX4 doesn't properly support C3 and bus master activity
* need not break out of C2.
*/
case PCI_REVISION_A_STEP:
case PCI_REVISION_B_STEP:
case PCI_REVISION_4E:
case PCI_REVISION_4M:
cpu_quirks |= CPU_QUIRK_NO_C3;
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: working around PIIX4 bug, disabling C3\n"));
val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
val |= PIIX4_STOP_BREAK_MASK;
pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
}
AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
if (val) {
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
"acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
}
break;
default:
break;
}
}
return (0);
}
/*
* Idle the CPU in the lowest state possible. This function is called with
* interrupts disabled. Note that once it re-enables interrupts, a task
* switch can occur so do not access shared data (i.e. the softc) after
* interrupts are re-enabled.
*/
static void
acpi_cpu_idle()
{
struct acpi_cpu_softc *sc;
struct acpi_cx *cx_next;
uint32_t start_time, end_time;
int bm_active, cx_next_idx, i;
/* If disabled, return immediately. */
if (cpu_disable_idle) {
ACPI_ENABLE_IRQS();
return;
}
/*
* Look up our CPU id to get our softc. If it's NULL, we'll use C1
* since there is no ACPI processor object for this CPU. This occurs
* for logical CPUs in the HTT case.
*/
sc = cpu_softc[PCPU_GET(cpuid)];
if (sc == NULL) {
acpi_cpu_c1();
return;
}
/* Find the lowest state that has small enough latency. */
cx_next_idx = 0;
for (i = sc->cpu_cx_lowest; i >= 0; i--) {
if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) {
cx_next_idx = i;
break;
}
}
/*
* Check for bus master activity. If there was activity, clear
* the bit and use the lowest non-C3 state. Note that the USB
* driver polling for new devices keeps this bit set all the
* time if USB is loaded.
*/
if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
if (bm_active != 0) {
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
cx_next_idx = min(cx_next_idx, sc->cpu_non_c3);
}
}
/* Select the next state and update statistics. */
cx_next = &sc->cpu_cx_states[cx_next_idx];
sc->cpu_cx_stats[cx_next_idx]++;
KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));
/*
* Execute HLT (or equivalent) and wait for an interrupt. We can't
* calculate the time spent in C1 since the place we wake up is an
* ISR. Assume we slept half of quantum and return.
*/
if (cx_next->type == ACPI_STATE_C1) {
sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + 500000 / hz) / 4;
acpi_cpu_c1();
return;
}
/*
* For C3, disable bus master arbitration and enable bus master wake
* if BM control is available, otherwise flush the CPU cache.
*/
if (cx_next->type == ACPI_STATE_C3) {
if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
} else
ACPI_FLUSH_CPU_CACHE();
}
/*
* Read from P_LVLx to enter C2(+), checking time spent asleep.
* Use the ACPI timer for measuring sleep time. Since we need to
* get the time very close to the CPU start/stop clock logic, this
* is the only reliable time source.
*/
AcpiRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock);
CPU_GET_REG(cx_next->p_lvlx, 1);
/*
* Read the end time twice. Since it may take an arbitrary time
* to enter the idle state, the first read may be executed before
* the processor has stopped. Doing it again provides enough
* margin that we are certain to have a correct value.
*/
AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
AcpiRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
/* Enable bus master arbitration and disable bus master wakeup. */
if (cx_next->type == ACPI_STATE_C3 &&
(cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
}
ACPI_ENABLE_IRQS();
/* Find the actual time asleep in microseconds. */
end_time = acpi_TimerDelta(end_time, start_time);
sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4;
}
ACPI_STATUS
AcpiHwLegacySleep (
UINT8 SleepState,
UINT8 Flags)
{
ACPI_BIT_REGISTER_INFO *SleepTypeRegInfo;
ACPI_BIT_REGISTER_INFO *SleepEnableRegInfo;
UINT32 Pm1aControl;
UINT32 Pm1bControl;
UINT32 InValue;
UINT32 Retry;
ACPI_STATUS Status;
ACPI_FUNCTION_TRACE (HwLegacySleep);
SleepTypeRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_TYPE);
SleepEnableRegInfo = AcpiHwGetBitRegisterInfo (ACPI_BITREG_SLEEP_ENABLE);
/* Clear wake status */
Status = AcpiWriteBitRegister (ACPI_BITREG_WAKE_STATUS, ACPI_CLEAR_STATUS);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Clear all fixed and general purpose status bits */
Status = AcpiHwClearAcpiStatus ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState != ACPI_STATE_S5)
{
/*
* Disable BM arbitration. This feature is contained within an
* optional register (PM2 Control), so ignore a BAD_ADDRESS
* exception.
*/
Status = AcpiWriteBitRegister (ACPI_BITREG_ARB_DISABLE, 1);
if (ACPI_FAILURE (Status) && (Status != AE_BAD_ADDRESS))
{
return_ACPI_STATUS (Status);
}
}
/*
* 1) Disable/Clear all GPEs
* 2) Enable all wakeup GPEs
*/
Status = AcpiHwDisableAllGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
AcpiGbl_SystemAwakeAndRunning = FALSE;
Status = AcpiHwEnableAllWakeupGpes ();
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Optionally execute _GTS (Going To Sleep) */
if (Flags & ACPI_EXECUTE_GTS)
{
AcpiHwExecuteSleepMethod (METHOD_PATHNAME__GTS, SleepState);
}
/* Get current value of PM1A control */
Status = AcpiHwRegisterRead (ACPI_REGISTER_PM1_CONTROL,
&Pm1aControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
ACPI_DEBUG_PRINT ((ACPI_DB_INIT,
"Entering sleep state [S%u]\n", SleepState));
/* Clear the SLP_EN and SLP_TYP fields */
Pm1aControl &= ~(SleepTypeRegInfo->AccessBitMask |
SleepEnableRegInfo->AccessBitMask);
Pm1bControl = Pm1aControl;
/* Insert the SLP_TYP bits */
Pm1aControl |= (AcpiGbl_SleepTypeA << SleepTypeRegInfo->BitPosition);
Pm1bControl |= (AcpiGbl_SleepTypeB << SleepTypeRegInfo->BitPosition);
/*
* We split the writes of SLP_TYP and SLP_EN to workaround
* poorly implemented hardware.
*/
/* Write #1: write the SLP_TYP data to the PM1 Control registers */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
/* Insert the sleep enable (SLP_EN) bit */
Pm1aControl |= SleepEnableRegInfo->AccessBitMask;
Pm1bControl |= SleepEnableRegInfo->AccessBitMask;
/* Flush caches, as per ACPI specification */
ACPI_FLUSH_CPU_CACHE ();
/* Write #2: Write both SLP_TYP + SLP_EN */
Status = AcpiHwWritePm1Control (Pm1aControl, Pm1bControl);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (SleepState > ACPI_STATE_S3)
{
/*
* We wanted to sleep > S3, but it didn't happen (by virtue of the
* fact that we are still executing!)
*
* Wait ten seconds, then try again. This is to get S4/S5 to work on
* all machines.
*
* We wait so long to allow chipsets that poll this reg very slowly
* to still read the right value. Ideally, this block would go
* away entirely.
*/
AcpiOsStall (10000000);
Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_CONTROL,
SleepEnableRegInfo->AccessBitMask);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
}
/* Wait for transition back to Working State */
Retry = 1000;
do
{
Status = AcpiReadBitRegister (ACPI_BITREG_WAKE_STATUS, &InValue);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (AcpiGbl_EnableInterpreterSlack)
{
/*
* Some BIOSs don't set WAK_STS at all. Give up waiting after
* 1000 retries if it still isn't set.
*/
if (Retry-- == 0)
{
break;
}
}
} while (!InValue);
return_ACPI_STATUS (AE_OK);
}
ACPI_STATUS
AcpiGetEventStatus (
UINT32 Event,
ACPI_EVENT_STATUS *EventStatus)
{
ACPI_STATUS Status;
ACPI_EVENT_STATUS LocalEventStatus = 0;
UINT32 InByte;
ACPI_FUNCTION_TRACE (AcpiGetEventStatus);
if (!EventStatus)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/* Decode the Fixed Event */
if (Event > ACPI_EVENT_MAX)
{
return_ACPI_STATUS (AE_BAD_PARAMETER);
}
/* Fixed event currently can be dispatched? */
if (AcpiGbl_FixedEventHandlers[Event].Handler)
{
LocalEventStatus |= ACPI_EVENT_FLAG_HAS_HANDLER;
}
/* Fixed event currently enabled? */
Status = AcpiReadBitRegister (
AcpiGbl_FixedEventInfo[Event].EnableRegisterId, &InByte);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (InByte)
{
LocalEventStatus |=
(ACPI_EVENT_FLAG_ENABLED | ACPI_EVENT_FLAG_ENABLE_SET);
}
/* Fixed event currently active? */
Status = AcpiReadBitRegister (
AcpiGbl_FixedEventInfo[Event].StatusRegisterId, &InByte);
if (ACPI_FAILURE (Status))
{
return_ACPI_STATUS (Status);
}
if (InByte)
{
LocalEventStatus |= ACPI_EVENT_FLAG_STATUS_SET;
}
(*EventStatus) = LocalEventStatus;
return_ACPI_STATUS (AE_OK);
}
status_t
read_bit_register(uint32 regid, uint32 *val)
{
return AcpiReadBitRegister(regid, (UINT32 *)val);
}
/*
* Idle the CPU in the lowest state possible. This function is called with
* interrupts disabled. Note that once it re-enables interrupts, a task
* switch can occur so do not access shared data (i.e. the softc) after
* interrupts are re-enabled.
*/
static void
acpi_cst_idle(void)
{
struct acpi_cst_softc *sc;
struct acpi_cst_cx *cx_next;
union microtime_pcpu start, end;
int cx_next_idx, i, tdiff, bm_arb_disabled = 0;
/* If disabled, return immediately. */
if (acpi_cst_disable_idle) {
ACPI_ENABLE_IRQS();
return;
}
/*
* Look up our CPU id to get our softc. If it's NULL, we'll use C1
* since there is no Cx state for this processor.
*/
sc = acpi_cst_softc[mdcpu->mi.gd_cpuid];
if (sc == NULL) {
acpi_cst_c1_halt();
return;
}
/* Still probing; use C1 */
if (sc->cst_flags & ACPI_CST_FLAG_PROBING) {
acpi_cst_c1_halt();
return;
}
/* Find the lowest state that has small enough latency. */
cx_next_idx = 0;
for (i = sc->cst_cx_lowest; i >= 0; i--) {
if (sc->cst_cx_states[i].trans_lat * 3 <= sc->cst_prev_sleep) {
cx_next_idx = i;
break;
}
}
/*
* Check for bus master activity if needed for the selected state.
* If there was activity, clear the bit and use the lowest non-C3 state.
*/
cx_next = &sc->cst_cx_states[cx_next_idx];
if (cx_next->flags & ACPI_CST_CX_FLAG_BM_STS) {
int bm_active;
AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
if (bm_active != 0) {
AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
cx_next_idx = sc->cst_non_c3;
}
}
/* Select the next state and update statistics. */
cx_next = &sc->cst_cx_states[cx_next_idx];
sc->cst_cx_stats[cx_next_idx]++;
KASSERT(cx_next->type != ACPI_STATE_C0, ("C0 sleep"));
/*
* Execute HLT (or equivalent) and wait for an interrupt. We can't
* calculate the time spent in C1 since the place we wake up is an
* ISR. Assume we slept half of quantum and return.
*/
if (cx_next->type == ACPI_STATE_C1) {
sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + 500000 / hz) / 4;
cx_next->enter(cx_next);
return;
}
/* Execute the proper preamble before enter the selected state. */
if (cx_next->preamble == ACPI_CST_CX_PREAMBLE_BM_ARB) {
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
bm_arb_disabled = 1;
} else if (cx_next->preamble == ACPI_CST_CX_PREAMBLE_WBINVD) {
ACPI_FLUSH_CPU_CACHE();
}
/*
* Enter the selected state and check time spent asleep.
*/
microtime_pcpu_get(&start);
cpu_mfence();
cx_next->enter(cx_next);
cpu_mfence();
microtime_pcpu_get(&end);
/* Enable bus master arbitration, if it was disabled. */
if (bm_arb_disabled)
AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
ACPI_ENABLE_IRQS();
/* Find the actual time asleep in microseconds. */
tdiff = microtime_pcpu_diff(&start, &end);
sc->cst_prev_sleep = (sc->cst_prev_sleep * 3 + tdiff) / 4;
}
