/**
Flush CPU data cache. If the instruction cache is fully coherent
with all DMA operations then function can just return EFI_SUCCESS.
@param This Protocol instance structure
@param Start Physical address to start flushing from.
@param Length Number of bytes to flush. Round up to chipset
granularity.
@param FlushType Specifies the type of flush operation to perform.
@retval EFI_SUCCESS If cache was flushed
@retval EFI_UNSUPPORTED If flush type is not supported.
@retval EFI_DEVICE_ERROR If requested range could not be flushed.
**/
EFI_STATUS
EFIAPI
CpuFlushCpuDataCache (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS Start,
IN UINT64 Length,
IN EFI_CPU_FLUSH_TYPE FlushType
)
{
if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
AsmWbinvd ();
return EFI_SUCCESS;
} else if (FlushType == EfiCpuFlushTypeInvalidate) {
AsmInvd ();
return EFI_SUCCESS;
} else {
return EFI_UNSUPPORTED;
}
}
EFI_STATUS
EFIAPI
CpuFlushCpuDataCache (
IN EFI_CPU_ARCH_PROTOCOL *This,
IN EFI_PHYSICAL_ADDRESS Start,
IN UINT64 Length,
IN EFI_CPU_FLUSH_TYPE FlushType
)
/*++
Routine Description:
Flush CPU data cache. If the instruction cache is fully coherent
with all DMA operations then function can just return EFI_SUCCESS.
Arguments:
This - Protocol instance structure
Start - Physical address to start flushing from.
Length - Number of bytes to flush. Round up to chipset
granularity.
FlushType - Specifies the type of flush operation to perform.
Returns:
EFI_SUCCESS - If cache was flushed
EFI_UNSUPPORTED - If flush type is not supported.
EFI_DEVICE_ERROR - If requested range could not be flushed.
--*/
{
if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {
AsmWbinvd ();
return EFI_SUCCESS;
} else if (FlushType == EfiCpuFlushTypeInvalidate) {
AsmInvd ();
return EFI_SUCCESS;
} else {
return EFI_UNSUPPORTED;
}
}
/**
This function will be called when MRC is done.
@param PeiServices General purpose services available to every PEIM.
@param NotifyDescriptor Information about the notify event..
@param Ppi The notify context.
@retval EFI_SUCCESS If the function completed successfully.
**/
EFI_STATUS
EFIAPI
MemoryDiscoveredPpiNotifyCallback (
IN EFI_PEI_SERVICES **PeiServices,
IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
IN VOID *Ppi
)
{
EFI_STATUS Status;
EFI_BOOT_MODE BootMode;
UINT64 MemoryLength;
UINT64 MemoryLengthUc;
UINT64 MaxMemoryLength;
UINT64 MemOverflow;
EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
UINTN NumSmramRegions;
UINT64 EnlargedMemoryLength;
UINT32 RmuMainBaseAddress;
UINTN Index;
MTRR_SETTINGS MtrrSetting;
UINT32 RegData32;
EFI_PHYSICAL_ADDRESS NewBuffer;
UINT8 CpuAddressWidth;
EFI_CPUID_REGISTER FeatureInfo;
DEBUG ((EFI_D_INFO, "Platform PEIM Memory Callback\n"));
NumSmramRegions = 0;
SmramDescriptor = NULL;
RmuMainBaseAddress = 0;
PERF_START (NULL, "SetCache", NULL, 0);
InfoPostInstallMemory (&RmuMainBaseAddress, &SmramDescriptor, &NumSmramRegions);
ASSERT (SmramDescriptor != NULL);
ASSERT (RmuMainBaseAddress != 0);
MemoryLength = ((UINT64) RmuMainBaseAddress) + 0x10000;
EnlargedMemoryLength = MemoryLength;
if (NumSmramRegions > 0) {
//
// Find the TSEG
//
for (Index = 0; Index < NumSmramRegions; Index ++) {
if ((SmramDescriptor[Index].PhysicalStart) == EnlargedMemoryLength) {
if (SmramDescriptor[Index].RegionState & EFI_CACHEABLE) {
//
// Enlarge memory length to include TSEG size
//
EnlargedMemoryLength += (SmramDescriptor[Index].PhysicalSize);
}
}
}
}
//
// Check if a UC region is present
//
MaxMemoryLength = EnlargedMemoryLength;
// Round up to nearest 256MB
MemOverflow = (MemoryLength & 0x0fffffff);
if (MemOverflow != 0) {
MaxMemoryLength = MemoryLength + (0x10000000 - MemOverflow);
}
Status = PeiServicesGetBootMode (&BootMode);
ASSERT_EFI_ERROR (Status);
ZeroMem (&MtrrSetting, sizeof(MTRR_SETTINGS));
(**PeiServices).CopyMem ((VOID *)&MtrrSetting.Fixed,(VOID *)&mFixedMtrrTable, sizeof(MTRR_FIXED_SETTINGS) );
//
// Cache the flash area to improve the boot performance in PEI phase
//
MtrrSetting.Variables.Mtrr[0].Base = (QUARK_BOOTROM_BASE_ADDRESS | CacheWriteBack);
MtrrSetting.Variables.Mtrr[0].Mask = (((~(QUARK_BOOTROM_SIZE_BYTES - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED);
MtrrSetting.Variables.Mtrr[1].Base = CacheWriteBack;
MtrrSetting.Variables.Mtrr[1].Mask = ((~(MaxMemoryLength - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
Index = 2;
while (MaxMemoryLength != MemoryLength) {
MemoryLengthUc = GetPowerOfTwo64 (MaxMemoryLength - MemoryLength);
//Status = MtrrSetMemoryAttribute (MaxMemoryLength - MemoryLengthUc, MemoryLengthUc, CacheUncacheable);
//ASSERT_EFI_ERROR (Status);
MtrrSetting.Variables.Mtrr[Index].Base = ((MaxMemoryLength - MemoryLengthUc) & MTRR_LIB_CACHE_VALID_ADDRESS) | CacheUncacheable;
MtrrSetting.Variables.Mtrr[Index].Mask= ((~(MemoryLengthUc - 1)) & MTRR_LIB_CACHE_VALID_ADDRESS) | MTRR_LIB_CACHE_MTRR_ENABLED;
MaxMemoryLength -= MemoryLengthUc;
Index++;
}
AsmInvd ();
MtrrSetting.MtrrDefType = MTRR_LIB_CACHE_MTRR_ENABLED | MTRR_LIB_CACHE_FIXED_MTRR_ENABLED;
MtrrSetAllMtrrs(&MtrrSetting);
PERF_END (NULL, "SetCache", NULL, 0);
//
// Install PeiReset for PeiResetSystem service
//
Status = PeiServicesInstallPpi (&mPpiList[0]);
ASSERT_EFI_ERROR (Status);
//
// Do QNC initialization after MRC
//
PeiQNCPostMemInit ();
Status = PeiServicesInstallPpi (&mPpiStall[0]);
ASSERT_EFI_ERROR (Status);
//
// Set E000/F000 Routing
//
RegData32 = QNCPortRead (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC);
RegData32 |= (BIT2|BIT1);
QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QNC_MSG_FSBIC_REG_HMISC, RegData32);
if (BootMode == BOOT_IN_RECOVERY_MODE) {
PeiServicesInstallFvInfoPpi (
NULL,
(VOID *) (UINTN) PcdGet32 (PcdFlashFvRecovery2Base),
PcdGet32 (PcdFlashFvRecovery2Size),
NULL,
NULL
);
Status = PeimInitializeRecovery (PeiServices);
ASSERT_EFI_ERROR (Status);
} else if (BootMode == BOOT_ON_S3_RESUME) {
return EFI_SUCCESS;
} else {
//
// Allocate the memory so that it gets preserved into DXE
//
Status = PeiServicesAllocatePages (
EfiBootServicesData,
EFI_SIZE_TO_PAGES (PcdGet32 (PcdFvSecurityHeaderSize) + PcdGet32 (PcdFlashFvMainSize)),
&NewBuffer
);
//
// Copy the compressed main Firmware Volume to memory for faster processing later
//
CopyMem ((VOID *) (UINTN) NewBuffer, (VOID *) (UINTN) (PcdGet32 (PcdFlashFvMainBase) - PcdGet32 (PcdFvSecurityHeaderSize)), (PcdGet32 (PcdFvSecurityHeaderSize) +PcdGet32 (PcdFlashFvMainSize)));
PeiServicesInstallFvInfoPpi (
NULL,
(VOID *) (UINTN) (NewBuffer + PcdGet32 (PcdFvSecurityHeaderSize)),
PcdGet32 (PcdFlashFvMainSize),
NULL,
NULL
);
}
//
// Build flash HOB, it's going to be used by GCD and E820 building
// Map full SPI flash decode range (regardless of smaller SPI flash parts installed)
//
BuildResourceDescriptorHob (
EFI_RESOURCE_FIRMWARE_DEVICE,
(EFI_RESOURCE_ATTRIBUTE_PRESENT |
EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
(SIZE_4GB - SIZE_8MB),
SIZE_8MB
);
//
// Create a CPU hand-off information
//
CpuAddressWidth = 32;
AsmCpuid (EFI_CPUID_EXTENDED_FUNCTION, &FeatureInfo.RegEax, NULL, NULL, NULL);
if (FeatureInfo.RegEax >= EFI_CPUID_VIR_PHY_ADDRESS_SIZE) {
AsmCpuid (EFI_CPUID_VIR_PHY_ADDRESS_SIZE, &FeatureInfo.RegEax, NULL, NULL, NULL);
CpuAddressWidth = (UINT8) (FeatureInfo.RegEax & 0xFF);
}
DEBUG ((EFI_D_INFO, "CpuAddressWidth: %d\n", CpuAddressWidth));
BuildCpuHob (CpuAddressWidth, 16);
ASSERT_EFI_ERROR (Status);
return Status;
}
