void ScalarBitSetTraits<ELFYAML::ELF_PF>::bitset(IO &IO,
ELFYAML::ELF_PF &Value) {
#define BCase(X) IO.bitSetCase(Value, #X, ELF::X)
BCase(PF_X);
BCase(PF_W);
BCase(PF_R);
}
void ScalarBitSetTraits<ELFYAML::ELF_STO>::bitset(IO &IO,
ELFYAML::ELF_STO &Value) {
const auto *Object = static_cast<ELFYAML::Object *>(IO.getContext());
assert(Object && "The IO context is not initialized");
#define BCase(X) IO.bitSetCase(Value, #X, ELF::X)
switch (Object->Header.Machine) {
case ELF::EM_MIPS:
BCase(STO_MIPS_OPTIONAL);
BCase(STO_MIPS_PLT);
BCase(STO_MIPS_PIC);
BCase(STO_MIPS_MICROMIPS);
break;
default:
break; // Nothing to do
}
#undef BCase
#undef BCaseMask
}
void ScalarBitSetTraits<WasmYAML::LimitFlags>::bitset(
IO &IO, WasmYAML::LimitFlags &Value) {
#define BCase(X) IO.bitSetCase(Value, #X, wasm::WASM_LIMITS_FLAG_##X)
BCase(HAS_MAX);
#undef BCase
}
void ScalarBitSetTraits<ELFYAML::MIPS_AFL_FLAGS1>::bitset(
IO &IO, ELFYAML::MIPS_AFL_FLAGS1 &Value) {
#define BCase(X) IO.bitSetCase(Value, #X, Mips::AFL_FLAGS1_##X)
BCase(ODDSPREG);
#undef BCase
}
void ScalarBitSetTraits<ELFYAML::MIPS_AFL_ASE>::bitset(
IO &IO, ELFYAML::MIPS_AFL_ASE &Value) {
#define BCase(X) IO.bitSetCase(Value, #X, Mips::AFL_ASE_##X)
BCase(DSP);
BCase(DSPR2);
BCase(EVA);
BCase(MCU);
BCase(MDMX);
BCase(MIPS3D);
BCase(MT);
BCase(SMARTMIPS);
BCase(VIRT);
BCase(MSA);
BCase(MIPS16);
BCase(MICROMIPS);
BCase(XPA);
#undef BCase
}
void ScalarBitSetTraits<ELFYAML::ELF_SHF>::bitset(IO &IO,
ELFYAML::ELF_SHF &Value) {
const auto *Object = static_cast<ELFYAML::Object *>(IO.getContext());
#define BCase(X) IO.bitSetCase(Value, #X, ELF::X)
BCase(SHF_WRITE);
BCase(SHF_ALLOC);
BCase(SHF_EXCLUDE);
BCase(SHF_EXECINSTR);
BCase(SHF_MERGE);
BCase(SHF_STRINGS);
BCase(SHF_INFO_LINK);
BCase(SHF_LINK_ORDER);
BCase(SHF_OS_NONCONFORMING);
BCase(SHF_GROUP);
BCase(SHF_TLS);
BCase(SHF_COMPRESSED);
switch (Object->Header.Machine) {
case ELF::EM_ARM:
BCase(SHF_ARM_PURECODE);
break;
case ELF::EM_HEXAGON:
BCase(SHF_HEX_GPREL);
break;
case ELF::EM_MIPS:
BCase(SHF_MIPS_NODUPES);
BCase(SHF_MIPS_NAMES);
BCase(SHF_MIPS_LOCAL);
BCase(SHF_MIPS_NOSTRIP);
BCase(SHF_MIPS_GPREL);
BCase(SHF_MIPS_MERGE);
BCase(SHF_MIPS_ADDR);
BCase(SHF_MIPS_STRING);
break;
case ELF::EM_X86_64:
BCase(SHF_X86_64_LARGE);
break;
default:
// Nothing to do.
break;
}
#undef BCase
}
void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
ELFYAML::ELF_EF &Value) {
const auto *Object = static_cast<ELFYAML::Object *>(IO.getContext());
assert(Object && "The IO context is not initialized");
#define BCase(X) IO.bitSetCase(Value, #X, ELF::X)
#define BCaseMask(X, M) IO.maskedBitSetCase(Value, #X, ELF::X, ELF::M)
switch (Object->Header.Machine) {
case ELF::EM_ARM:
BCase(EF_ARM_SOFT_FLOAT);
BCase(EF_ARM_VFP_FLOAT);
BCaseMask(EF_ARM_EABI_UNKNOWN, EF_ARM_EABIMASK);
BCaseMask(EF_ARM_EABI_VER1, EF_ARM_EABIMASK);
BCaseMask(EF_ARM_EABI_VER2, EF_ARM_EABIMASK);
BCaseMask(EF_ARM_EABI_VER3, EF_ARM_EABIMASK);
BCaseMask(EF_ARM_EABI_VER4, EF_ARM_EABIMASK);
BCaseMask(EF_ARM_EABI_VER5, EF_ARM_EABIMASK);
break;
case ELF::EM_MIPS:
BCase(EF_MIPS_NOREORDER);
BCase(EF_MIPS_PIC);
BCase(EF_MIPS_CPIC);
BCase(EF_MIPS_ABI2);
BCase(EF_MIPS_32BITMODE);
BCase(EF_MIPS_FP64);
BCase(EF_MIPS_NAN2008);
BCase(EF_MIPS_MICROMIPS);
BCase(EF_MIPS_ARCH_ASE_M16);
BCase(EF_MIPS_ARCH_ASE_MDMX);
BCaseMask(EF_MIPS_ABI_O32, EF_MIPS_ABI);
BCaseMask(EF_MIPS_ABI_O64, EF_MIPS_ABI);
BCaseMask(EF_MIPS_ABI_EABI32, EF_MIPS_ABI);
BCaseMask(EF_MIPS_ABI_EABI64, EF_MIPS_ABI);
BCaseMask(EF_MIPS_MACH_3900, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_4010, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_4100, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_4650, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_4120, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_4111, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_SB1, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_OCTEON, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_XLR, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_OCTEON2, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_OCTEON3, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_5400, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_5900, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_5500, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_9000, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_LS2E, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_LS2F, EF_MIPS_MACH);
BCaseMask(EF_MIPS_MACH_LS3A, EF_MIPS_MACH);
BCaseMask(EF_MIPS_ARCH_1, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_2, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_3, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_4, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_5, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_32, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_64, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_32R2, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_64R2, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_32R6, EF_MIPS_ARCH);
BCaseMask(EF_MIPS_ARCH_64R6, EF_MIPS_ARCH);
break;
case ELF::EM_HEXAGON:
BCase(EF_HEXAGON_MACH_V2);
BCase(EF_HEXAGON_MACH_V3);
BCase(EF_HEXAGON_MACH_V4);
BCase(EF_HEXAGON_MACH_V5);
BCase(EF_HEXAGON_ISA_V2);
BCase(EF_HEXAGON_ISA_V3);
BCase(EF_HEXAGON_ISA_V4);
BCase(EF_HEXAGON_ISA_V5);
break;
case ELF::EM_AVR:
BCase(EF_AVR_ARCH_AVR1);
BCase(EF_AVR_ARCH_AVR2);
BCase(EF_AVR_ARCH_AVR25);
BCase(EF_AVR_ARCH_AVR3);
BCase(EF_AVR_ARCH_AVR31);
BCase(EF_AVR_ARCH_AVR35);
BCase(EF_AVR_ARCH_AVR4);
BCase(EF_AVR_ARCH_AVR51);
BCase(EF_AVR_ARCH_AVR6);
BCase(EF_AVR_ARCH_AVRTINY);
BCase(EF_AVR_ARCH_XMEGA1);
BCase(EF_AVR_ARCH_XMEGA2);
BCase(EF_AVR_ARCH_XMEGA3);
BCase(EF_AVR_ARCH_XMEGA4);
BCase(EF_AVR_ARCH_XMEGA5);
BCase(EF_AVR_ARCH_XMEGA6);
BCase(EF_AVR_ARCH_XMEGA7);
break;
case ELF::EM_RISCV:
BCase(EF_RISCV_RVC);
BCaseMask(EF_RISCV_FLOAT_ABI_SOFT, EF_RISCV_FLOAT_ABI);
BCaseMask(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI);
BCaseMask(EF_RISCV_FLOAT_ABI_DOUBLE, EF_RISCV_FLOAT_ABI);
BCaseMask(EF_RISCV_FLOAT_ABI_QUAD, EF_RISCV_FLOAT_ABI);
BCase(EF_RISCV_RVE);
break;
case ELF::EM_AMDGPU:
BCaseMask(EF_AMDGPU_ARCH_R600, EF_AMDGPU_ARCH);
BCaseMask(EF_AMDGPU_ARCH_GCN, EF_AMDGPU_ARCH);
break;
case ELF::EM_X86_64:
break;
default:
llvm_unreachable("Unsupported architecture");
}
#undef BCase
#undef BCaseMask
}
