/*
* delay:
*
* Delay for at least N microseconds.
*/
void
delay(u_int n)
{
uint32_t cur, last, delta, usecs;
/*
* This works by polling the timer and counting the
* number of microseconds that go by.
*/
last = BECC_CSR_READ(BECC_TCVRA);
delta = usecs = 0;
while (n > usecs) {
cur = BECC_CSR_READ(BECC_TCVRA);
/* Check to see if the timer has wrapped around. */
if (last < cur)
delta += (last + (counts_per_hz - cur));
else
delta += (last - cur);
last = cur;
if (delta >= COUNTS_PER_USEC) {
usecs += delta / COUNTS_PER_USEC;
delta %= COUNTS_PER_USEC;
}
}
}
static int
becc_pci_conf_cleanup(struct becc_softc *sc)
{
uint32_t reg;
int err=0;
BECC_CSR_WRITE(BECC_POCR, 0);
reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);
if (reg & 0xf9000000) {
DPRINTF((" ** pci status error: %08x (%08x) **\n",
reg, reg & 0xf9000000));
err = 1;
becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG,
reg & 0xf900ffff);
reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);
DPRINTF((" ** pci status after clearing: %08x (%08x) **\n",
reg, reg & 0xf9000000));
}
reg = BECC_CSR_READ(BECC_PMISR);
if (reg & 0x000f000d) {
DPRINTF((" ** pci master isr: %08x (%08x) **\n",
reg, reg & 0x000f000d));
err = 1;
BECC_CSR_WRITE(BECC_PMISR, reg & 0x000f000d);
reg = BECC_CSR_READ(BECC_PMISR);
DPRINTF((" ** pci master isr after clearing: %08x (%08x) **\n",
reg, reg & 0x000f000d));
}
reg = BECC_CSR_READ(BECC_PSISR);
if (reg & 0x000f0210) {
DPRINTF((" ** pci slave isr: %08x (%08x) **\n",
reg, reg & 0x000f0210));
err = 1;
BECC_CSR_WRITE(BECC_PSISR, reg & 0x000f0210);
reg = BECC_CSR_READ(BECC_PSISR);
DPRINTF((" ** pci slave isr after clearing: %08x (%08x) **\n",
reg, reg & 0x000f0210));
}
return err;
}
static u_int
becc_get_timecount(struct timecounter *tc)
{
uint32_t counter, base;
u_int oldirqstate;
oldirqstate = disable_interrupts(I32_bit);
counter = BECC_CSR_READ(BECC_TCVRA);
base = becc_base;
restore_interrupts(oldirqstate);
return base - counter;
}
