Exemplo n.º 1
0
void
evgMxc::setPolarity(bool polarity) {
    if(polarity)
        BITSET32(m_pReg, MuxControl(m_id), MuxControl_Pol);
    else
        BITCLR32(m_pReg, MuxControl(m_id), MuxControl_Pol);
}
Exemplo n.º 2
0
void
evgEvtClk::setSource (bool clkSrc) {
    if(clkSrc)
        BITSET32 (m_pReg, ClockControl, ClockControl_EXTRF);
    else 
        BITCLR32 (m_pReg, ClockControl, ClockControl_EXTRF);
}
Exemplo n.º 3
0
void
evgSeqRam::setRunMode(SeqRunMode mode) {
    switch (mode) {
        case(Normal):
            BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE);
            BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_RECYCLE);
            break;
        case(Auto):
            BITCLR32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE);
            BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_RECYCLE);
            break;	
        case(Single):
            BITSET32(m_pReg, SeqControl(m_id), EVG_SEQ_RAM_SINGLE);
            break;	
        default:
            throw std::runtime_error("Unknown SeqRam RunMode");
    }
}
Exemplo n.º 4
0
static bool
disableIRQ(mrf::Object* obj, void*)
{
    evgMrm *evg=dynamic_cast<evgMrm*>(obj);
    if(!evg)
        return true;

    BITCLR32(evg->getRegAddr(), IrqEnable, EVG_IRQ_ENABLE);
    return true;
}
Exemplo n.º 5
0
void
evgMxc::setTrigEvtMap(epicsUInt16 trigEvt, bool ena) {
    if(trigEvt > 7)
        throw std::runtime_error("EVG Mxc Trig Event ID too large. Max: 7");

    epicsUInt32    mask = 1 << (trigEvt+MuxControl_TrigMap_SHIFT);
    if(ena)
        BITSET32(m_pReg, MuxControl(m_id), mask);
    else
        BITCLR32(m_pReg, MuxControl(m_id), mask);
}
Exemplo n.º 6
0
void
evgMrm::enable(bool ena) {
    if(ena)
        BITSET32(m_pReg, Control, EVG_MASTER_ENA);
    else
        BITCLR32(m_pReg, Control, EVG_MASTER_ENA);

    BITSET32(m_pReg, Control, EVG_DIS_EVT_REC);
    BITSET32(m_pReg, Control, EVG_REV_PWD_DOWN);
    BITSET32(m_pReg, Control, EVG_MXC_RESET);
}
Exemplo n.º 7
0
void gic_Int_cfg(u16 irq, u16 prio, u16 pol)
{
    u32  reg;  

    reg  =  (u32)&GIC_INT_REG_ICDIPR;        /* Configure interrupt priority. */
	reg +=  (irq / 4u *4);

	*(u32 *) reg &=~(0xFF<<((irq%4)*8));
	*(u32 *) reg |= prio<<((irq%4)*8);
	 
    reg  =  (u32)&GIC_INT_REG_ICDICFR;                   
    reg +=  (irq / 16u);
	
	if (pol == GIC_INT_POL_LEVEL_HIGH || pol == GIC_INT_POL_LEVEL_LOW) { 
	    BITCLR32((*(u32 *)reg), (1u << (((irq % 16u) * 2u) + 1u)));
	} else {
	    BITSET32((*(u32 *)reg), (1u << (((irq % 16u) * 2u) + 1u))); 
	}
}
Exemplo n.º 8
0
void  pvt_stop (void)
{
	BITCLR32(PVT_TMR_CONTROL, BIT0);
}
Exemplo n.º 9
0
void  gic_Int_init (void)
{
    u32     reg;
    u32     core_msk;
	u8     i;
    u16     irq;
    gic_irq_vect_t  *pvect;
	u32 flags;
	struct bm_gic_chip_data *gic_data = (struct bm_gic_chip_data *)(AMPPHY_START + AMP_GIC_DATA_OFFSET);
	void *base = (void *)GIC_INT_DIST_BASE;
	u32 gic_irqs;
	
    BITCLR32(GIC_INT_REG_ICDDCR, BIT0);    /* Disable the Global Interrupt Controller.             */
	//uartprintf("********####gic_irqs\r\n");
	gic_irqs = readl(base + 4) & 0x1f;
	gic_irqs = (gic_irqs + 1) * 32;
	//uartprintf("++gic_irqs = %d\r\n", gic_irqs);
	if (gic_irqs > 1020)
		gic_irqs = 1020;
	gic_data->gic_irqs = gic_irqs;

	
	for (i = 0u; i < (gic_irqs / 32u); i++) {        /* Disable all the GIC irq sources.                     */
	    reg  = (u32)&GIC_INT_REG_ICDICER;
 	    reg += (4u + (i * 4u));

        (*(u32 *)reg) = 0xFFFFFFFF;
	  
 	    reg  = (u32)&GIC_INT_REG_ICDICPR;
 	    reg +=  i * 4u;

        //(*(u32 *)reg) = 0xa0a0a0a0;
		(*(u32 *)reg) = 0xFFFFFFFF;
	}

	for (i = 32; i < (gic_irqs / 16); i += 16)
		writel(0, (void *)GIC_INT_DIST_BASE + 0xc00 + i * 4 / 16);
		 
	core_msk = (BIT0 | BIT8 | BIT16 | BIT24); /* bit0~7 for cpu0~cpu8  */
	//core_msk = (BIT1 | BIT9 | BIT17 | BIT25); 

    for (i = 0u; i < ((gic_irqs - 32u) / 4u); i++) {
		reg  = (u32)&GIC_INT_REG_ICDIPTR;    //target
 		reg += (((32u / 4u) + i) * 4u);

        (*(u32 *)reg) = core_msk;	

	  	reg  = (u32)&GIC_INT_REG_ICDIPR;     //priority
 	    reg += (((32u / 4u) + i) * 4u);

        (*(u32 *)reg) = 0xa0a0a0a0;	
	}

	gic_Int_cfg_target(GIC_DMA0);
	gic_Int_cfg_target(GIC_PFGA0);


	gic_Int_cfg(GIC_PFGA0, 0x80, GIC_INT_POL_EDGE_RISING);
                                                                /* Initialize the vector table. */
    for (irq = 0u; irq < MAX_IRQ_NR; irq++) {
        pvect = &gic_vect_tbl[irq];

        flags = cpu_local_irq_save();
        gic_Int_vect_clr(pvect);                             /* Initialize main vector table entry. */
        cpu_local_irq_restore(flags);
    }
	
    BITCLR32(GIC_INT_REG_ICCPMR, 0xffff);	 
    BITSET32(GIC_INT_REG_ICCPMR, BIT4|BIT5|BIT6|BIT7);    /* Set priority mask. */  
    BITSET32(GIC_INT_REG_ICCICR, BIT0);    /* Enable CPU interface.  */
	BITSET32(GIC_INT_REG_ICDDCR, BIT0);    /* Enable the Global Interrupt Controller.  */ 
}
Exemplo n.º 10
0
void  gic_Int_dis_all (void)
{
    BITCLR32(GIC_INT_REG_ICDDCR, BIT0);
}