/* Image offset setting */
void VIOC_VIN_SetImageOffset(VIOC_VIN *pVIN, unsigned int offs_width, unsigned int offs_height, unsigned int offs_height_intl)
{
//pVIN->uVIN_OFFS.bVIN_OFFS.offs_width = offs_width;
//pVIN->uVIN_OFFS.bVIN_OFFS.offs_height = offs_height;
//pVIN->uVIN_OFFS_INTL.bVIN_OFFS.offs_height = offs_height_intl;
BITCSET(pVIN->uVIN_OFFS.nREG, 0xFFFFFFFF, (offs_height << 16) | (offs_width) );
BITCSET(pVIN->uVIN_OFFS_INTL.nREG, 0xFFFF0000, (offs_height_intl << 16) );
}
/*------------------------------------------------------------------
Gre2d_src_ctrl
graphic engine sorce control
-------------------------------------------------------------------*/
void Gre2d_src_ctrl(G2D_SRC_CTRL reg)
{
unsigned int sf_ctrl_reg = 0, sa_ctrl_reg = 0,ctrl_reg = 0;
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
#if defined(CONFIG_ARCH_TCC892X)
// source YUV to RGB converter enable sf_ctrl
sf_ctrl_reg |= (((reg.src0_y2r.src_y2r <<24) & Hw2D_SFCTRL_S0_Y2REN) |
((reg.src1_y2r.src_y2r <<25) & Hw2D_SFCTRL_S1_Y2REN) | ((reg.src2_y2r.src_y2r <<26) & Hw2D_SFCTRL_S2_Y2REN));
// source YUV to RGB coverter type sf_ctrl
sf_ctrl_reg |= (((reg.src0_y2r.src_y2r_type<<16) & Hw2D_SFCTRL_S0_Y2RMODE) |
((reg.src1_y2r.src_y2r_type <<18) & Hw2D_SFCTRL_S1_Y2RMODE) | ((reg.src2_y2r.src_y2r_type <<20) & Hw2D_SFCTRL_S2_Y2RMODE));
// source select sf_ctrl
sf_ctrl_reg |= ((reg.src_sel_0) & Hw2D_SFCTRL_S0_SEL) |((reg.src_sel_1<<2) & Hw2D_SFCTRL_S1_SEL)
| ((reg.src_sel_2<<4) & Hw2D_SFCTRL_S2_SEL) | ((reg.src_sel_3<<6) & Hw2D_SFCTRL_S3_SEL) ;
// source arithmetic mode sa_ctrl
sa_ctrl_reg |= (((reg.src0_arith ) & Hw2D_SACTRL_S0_ARITHMODE) |
((reg.src1_arith<<4) & Hw2D_SACTRL_S1_ARITHMODE) | ((reg.src2_arith<<8) & Hw2D_SACTRL_S2_ARITHMODE));
// source chroma key enable : for arithmetic sa_ctrl
sa_ctrl_reg |= (((reg.src0_chroma_en<<16) & Hw2D_SACTRL_S0_CHROMAEN) |
((reg.src1_chroma_en<<17) & Hw2D_SACTRL_S1_CHROMAEN) | ((reg.src2_chroma_en<<18) & Hw2D_SACTRL_S2_CHROMAEN));
BITCSET(pHwOVERLAYMIXER->SF_CTRL.nREG, 0x0FFFFFFF, sf_ctrl_reg);
BITCSET(pHwOVERLAYMIXER->SA_CTRL.nREG, 0x0FFFFFFF, sa_ctrl_reg);
#else
// source arithmetic mode
ctrl_reg |= (((reg.src0_arith<<19) & Hw2D_SCTRL_S0_ARITHMODE) |
((reg.src1_arith<<22) & Hw2D_SCTRL_S1_ARITHMODE) | ((reg.src2_arith<<25) & Hw2D_SCTRL_S2_ARITHMODE));
// source YUV to RGB converter enable
ctrl_reg |= (((reg.src0_y2r.src_y2r <<16) & Hw2D_SCTRL_S0_Y2REN) |
((reg.src1_y2r.src_y2r <<17) & Hw2D_SCTRL_S1_Y2REN) | ((reg.src2_y2r.src_y2r <<18) & Hw2D_SCTRL_S2_Y2REN));
// source YUV to RGB coverter type
ctrl_reg |= (((reg.src0_y2r.src_y2r_type<<9) & Hw2D_SCTRL_S0_Y2RMODE) |
((reg.src1_y2r.src_y2r_type <<11) & Hw2D_SCTRL_S1_Y2RMODE) | ((reg.src2_y2r.src_y2r_type <<13) & Hw2D_SCTRL_S2_Y2RMODE));
// source chroma key enable : for arithmetic
ctrl_reg |= (((reg.src0_chroma_en<<6) & Hw2D_SCTRL_S0_CHROMAEN) |
((reg.src1_chroma_en<<7) & Hw2D_SCTRL_S1_CHROMAEN) | ((reg.src2_chroma_en<<8) & Hw2D_SCTRL_S2_CHROMAEN));
// source select
ctrl_reg |= (((reg.src_sel_0) & Hw2D_SCTRL_S0_SEL) |
((reg.src_sel_1<<2) & Hw2D_SCTRL_S1_SEL) | ((reg.src_sel_2<<4) & Hw2D_SCTRL_S2_SEL));
BITCSET(pHwOVERLAYMIXER->S_CTRL, 0x0FFFFFFF, ctrl_reg);
#endif
}
void VIOC_DISP_SetTimingParam (VIOC_DISP *pDISP, stLTIMING *pTimeParam)
{
/*
pDISP->uLHTIME1.bREG.LPC = pTimeParam->lpc - 1;
pDISP->uLHTIME1.bREG.LPW = pTimeParam->lpw;
pDISP->uLHTIME2.bREG.LEWC = pTimeParam->lewc -1;
pDISP->uLHTIME2.bREG.LSWC = pTimeParam->lswc -1;
pDISP->uLVTIME1.bREG.FLC = pTimeParam->flc;
pDISP->uLVTIME1.bREG.FPW = pTimeParam->fpw;
pDISP->uLVTIME2.bREG.FEWC = pTimeParam->fewc;
pDISP->uLVTIME2.bREG.FSWC = pTimeParam->fswc;
pDISP->uLVTIME3.bREG.FLC = pTimeParam->flc2;
pDISP->uLVTIME3.bREG.FPW = pTimeParam->fpw2;
pDISP->uLVTIME4.bREG.FEWC = pTimeParam->fewc2;
pDISP->uLVTIME4.bREG.FSWC = pTimeParam->fswc2;
*/
// Horizon
BITCSET(pDISP->uLHTIME1.nREG, 0x00003FFF, (pTimeParam->lpc - 1) );
BITCSET(pDISP->uLHTIME1.nREG, 0x01FF0000, pTimeParam->lpw << 16 );
BITCSET(pDISP->uLHTIME2.nREG, 0x01FF01FF, ((pTimeParam->lswc-1) << 16) | (pTimeParam->lewc -1));
// Vertical timing
BITCSET(pDISP->uLVTIME1.nREG, 0x00003FFF, pTimeParam->flc);
BITCSET(pDISP->uLVTIME1.nREG, 0x3F << 16 , pTimeParam->fpw << 16);
BITCSET(pDISP->uLVTIME2.nREG, 0x01FF01FF, (pTimeParam->fswc << 16) | pTimeParam->fewc);
BITCSET(pDISP->uLVTIME3.nREG, 0x00003FFF, pTimeParam->flc2);
BITCSET(pDISP->uLVTIME3.nREG, 0x3F << 16 , pTimeParam->fpw2 << 16);
BITCSET(pDISP->uLVTIME4.nREG, 0x01FF01FF, (pTimeParam->fswc2<< 16) | pTimeParam->fewc2);
}
void VIOC_RDMA_SetImageEnable(VIOC_RDMA *pRDMA )
{
/*
pRDMA->uCTRL.bREG.IEN = 1;
pRDMA->uCTRL.bREG.UPD = 1;
*/
BITCSET(pRDMA->uCTRL.nREG, 1<<28, 1<<28 );
BITCSET(pRDMA->uCTRL.nREG, 1<<16, 1<<16 );
}
/*------------------------------------------------------------------
Gre2d_Grp_enable
graphic engine channel enable control
-------------------------------------------------------------------*/
void Gre2d_Grp_enable(G2D_EN grp_enalbe, unsigned char int_en)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
#if defined(CONFIG_ARCH_TCC892X)
BITCSET( pHwOVERLAYMIXER->OM_CTRL.nREG, (HwGE_GE_CTRL_EN|HwGE_GE_INT_EN), ((int_en<<16)|grp_enalbe));
#else
BITCSET( pHwOVERLAYMIXER->OM_CTRL, (HwGE_GE_CTRL_EN|HwGE_GE_INT_EN), ((int_en<<16)|grp_enalbe));
#endif
}
void edi_init()
{
#ifdef TNFTL_V8_INCLUDE
PEDI pEDI = (PEDI)HwEDI_BASE;
BITCSET(pEDI->EDI_RDYCFG.nREG, 0x000FFFFF, 0x00000001 );
BITCSET(pEDI->EDI_CSNCFG0.nREG, 0x0000FFFF, 0x00008765 );
BITCSET(pEDI->EDI_OENCFG.nREG, 0x0000000F, 0x00000001 );
BITCSET(pEDI->EDI_WENCFG.nREG, 0x0000000F, 0x00000001 );
#endif
}
/*------------------------------------------------------------------
Gre2d_Grp_int_en
graphic engine interrupt enable
-------------------------------------------------------------------*/
void Gre2d_Grp_int_en(unsigned int int_en)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
#if defined(CONFIG_ARCH_TCC892X)
BITCSET( pHwOVERLAYMIXER->OM_IREQ.nREG, 0xFFFFFFFF, int_en);
#else
BITCSET( pHwOVERLAYMIXER->OM_IREQ, 0xFFFFFFFF, int_en);
#endif
}
void VIOC_WDMA_SetImageBase(VIOC_WDMA *pWDMA, unsigned int nBase0, unsigned int nBase1, unsigned int nBase2)
{
/*
pWDMA->uBASE0 = nBase0;
pWDMA->uBASE1 = nBase1;
pWDMA->uBASE2 = nBase2;
*/
BITCSET(pWDMA->uBASE0, 0xFFFFFFFF, nBase0);
BITCSET(pWDMA->uBASE1, 0xFFFFFFFF, nBase1);
BITCSET(pWDMA->uBASE2, 0xFFFFFFFF, nBase2);
}
/* set 1 : IREQ Masked( interrupt disable), set 0 : IREQ UnMasked( interrput enable) */
void VIOC_RDMA_SetIreqMask(VIOC_RDMA * pRDMA, unsigned int mask, unsigned int set)
{
if( set == 0 ) /* Interrupt Enable*/
{
//pRDMA->uIRQMSK.nREG &= ~mask;
BITCSET(pRDMA->uIRQMSK.nREG, 0x0000001F, ~mask);
}
else/* Interrupt Diable*/
{
//pRDMA->uIRQMSK.nREG |= mask;
BITCSET(pRDMA->uIRQMSK.nREG, 0x0000001F, mask);
}
}
void VIOC_WDMA_SetIreqMask(VIOC_WDMA * pWDMA, unsigned int mask, unsigned int set)
{ /* set 1 : IREQ Masked(interrupt disable), set 0 : IREQ UnMasked(interrput enable) */
if(set == 0) /* Interrupt Enable*/
{
//pWDMA->uIRQMSK.nREG &= ~mask;
BITCSET(pWDMA->uIRQMSK.nREG, 0x0000001F, ~mask);
}
else/* Interrupt Diable*/
{
//pWDMA->uIRQMSK.nREG |= mask;
BITCSET(pWDMA->uIRQMSK.nREG, 0x0000001F, mask);
}
}
void VIOC_DISP_SetClipping(VIOC_DISP *pDISP, unsigned int uiUpperLimitY, unsigned int uiLowerLimitY, unsigned int uiUpperLimitUV, unsigned int uiLowerLimitUV)
{
/*
pDISP->uCLIPY.bREG.CLPH = uiUpperLimitY;
pDISP->uCLIPY.bREG.CLPL = uiLowerLimitY;
pDISP->uCLIPC.bREG.CLPH = uiUpperLimitUV;
pDISP->uCLIPC.bREG.CLPL = uiLowerLimitUV;
*/
BITCSET(pDISP->uCLIPY.nREG, 0x00FF00FF, uiUpperLimitY << 16 | uiLowerLimitY );
BITCSET(pDISP->uCLIPC.nREG, 0x00FF00FF, uiUpperLimitUV<< 16 | uiLowerLimitUV);
}
static void goodix_wakeup_init(void)
{
BITCSET(TS_WAKEUP_PORT_EN, TS_WAKEUP_PIN, TS_WAKEUP_PIN); //output mode
BITCSET(TS_WAKEUP_PORT_DAT, TS_WAKEUP_PIN, TS_WAKEUP_PIN);//HIGH to enter sleep mode
mdelay(100);
BITCSET(TS_WAKEUP_PORT_DAT, TS_WAKEUP_PIN, 0);//set low to wakeup goodix device
mdelay(100);
/*if(TS_WAKEUP_ENABLE == mode){
BITCSET(TS_WAKEUP_PORT_DAT, TS_WAKEUP_PIN, 0);//set low to wakeup goodix device
}
else{//(TS_WAKEUP_DISABLE == mode)
BITCSET(TS_WAKEUP_PORT_DAT, TS_WAKEUP_PIN, TS_WAKEUP_PIN);//HIGH to enter sleep mode
}*/
}
/* Interlace mode setting */
void VIOC_VIN_SetInterlaceMode(VIOC_VIN *pVIN, unsigned int intl_en, unsigned int intpl_en)
{
//pVIN->uVIN_CTRL.bVIN_CTRL.intl_en = intl_en;
//pVIN->uVIN_CTRL.bVIN_CTRL.intpl_en = intpl_en;
BITCSET(pVIN->uVIN_CTRL.nREG, 0x0000000C, (intl_en<<2) | (intpl_en<<3));
}
/* Image size setting */
void VIOC_VIN_SetImageSize(VIOC_VIN *pVIN, unsigned int width, unsigned int height)
{ /* pkjin20 : Chip Bug... To Prevent Read Operation */
//pVIN->uVIN_SIZE.bVIN_SIZE.width = width; //(height << 16) | width;
//pVIN->uVIN_SIZE.bVIN_SIZE.height = height;
BITCSET(pVIN->uVIN_SIZE.nREG, 0xFFFFFFFF, (height << 16) | width);
}
/*------------------------------------------------------------------
Gre2d_SetBCh_position
graphic engine BACK END channel position settig
frameps_x, frameps_y : frame pixsel size
poffset_x, poffset_y : pixsel offset
-------------------------------------------------------------------*/
void Gre2d_SetBCh_position(G2D_CHANNEL ch, unsigned int frameps_x, unsigned int frameps_y, unsigned int poffset_x, unsigned int poffset_y)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
if(ch == DEST_CH)
{
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->BCH_DFSIZE.nREG, 0x0FFF0FFF, ((frameps_y<<16) | frameps_x)); // pHwOVERLAYMIXER->BCH_DFSIZE
BITCSET(pHwOVERLAYMIXER->BCH_DOFF.nREG, 0x0FFF0FFF, ((poffset_y<<16) | poffset_x)); // pHwOVERLAYMIXER->BCH_DOFF
#else
BITCSET(pHwOVERLAYMIXER->BCH_DFSIZE, 0x0FFF0FFF, ((frameps_y<<16) | frameps_x)); // pHwOVERLAYMIXER->BCH_DFSIZE
BITCSET(pHwOVERLAYMIXER->BCH_DOFF, 0x0FFF0FFF, ((poffset_y<<16) | poffset_x)); // pHwOVERLAYMIXER->BCH_DOFF
#endif
}
}
void VIOC_RDMA_SetImageAlpha(VIOC_RDMA *pRDMA, unsigned int nAlpha0, unsigned int nAlpha1)
{
//pRDMA->uALPHA.bREG.ALPHA0 = nAlpha0;
//pRDMA->uALPHA.bREG.ALPHA1 = nAlpha1;
BITCSET(pRDMA->uALPHA.nREG, 0x00FF00FF, ( nAlpha1 << 16 ) | nAlpha0 );
}
void VIOC_DISP_SetSize(VIOC_DISP *pDISP, unsigned int nWidth, unsigned int nHeight)
{
//pDISP->uLSIZE.bREG.HSIZE = nWidth;
//pDISP->uLSIZE.bREG.VSIZE = nHeight;
BITCSET(pDISP->uLSIZE.nREG, 0xFFFFFFFF, (nHeight << 16) | (nWidth) );
}
/* LUT Enable/Disable */
void VIOC_VIN_SetLUTEnable(VIOC_VIN *pVIN, unsigned int lut0_en, unsigned int lut1_en, unsigned int lut2_en)
{
//pVIN->uVIN_MISC1.bVIN_MISC1.lut0_en = lut0_en; /* Color Y (or R) */
//pVIN->uVIN_MISC1.bVIN_MISC1.lut1_en = lut1_en; /* Color Cb (or G) */
//pVIN->uVIN_MISC1.bVIN_MISC1.lut2_en = lut2_en; /* Color Cr (or B) */
BITCSET(pVIN->uVIN_MISC1.nREG, 0x00000007, (lut2_en << 2) | (lut1_en << 1) | (lut0_en));
}
void VIOC_WDMA_SetImageSize(VIOC_WDMA *pWDMA, unsigned int sw, unsigned int sh)
{
//pWDMA->uSIZE.bREG.WIDTH = sw;
//pWDMA->uSIZE.bREG.HEIGHT = sh;
BITCSET(pWDMA->uSIZE.nREG, 0xFFFFFFFF, (sh << 16) | (sw) );
}
void VIOC_DISP_SetPosition(VIOC_DISP *pDISP, unsigned int startX, unsigned int startY )
{
//pDISP->uLPOS.bREG.XPOS = startX;
//pDISP->uLPOS.bREG.YPOS = startY;
BITCSET(pDISP->uLPOS.nREG, 0x1FFF1FFF, startY << 16 | startX);
}
void Gre2d_operator_ctrl(G2D_ASEL_TYPE ASEL1, G2D_OP1_CHROMA CSEL1, GE_ROP_TYPE op1, G2D_ASEL_TYPE ASEL0, G2D_OP0_CHROMA CSEL0, GE_ROP_TYPE op0)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
BITCSET(pHwOVERLAYMIXER->OP_CTRL, 0x01FF01FF, (((ASEL1<<23)&HwGE_OP_CTRL_ASEL1)| ((CSEL1<<21)&HwGE_OP_CTRL_CSEL1) | ((op1<<16) & HwGE_OP_CTRL_OP1_MODE)
|((ASEL0<<7)&HwGE_OP_CTRL_ASEL0)| ((CSEL0<<5)&HwGE_OP_CTRL_CSEL0) | (op0 & HwGE_OP_CTRL_OP0_MODE)));
}
void tchal_irq_setup(void)
{
#ifdef __USE_TC_CPU__
#if defined(__USE_DXB1_IRQ__)
BITCLR(RGPIO->GPAFN1, Hw16 - Hw12); /* DXB1_IRQ Set GPIO mode*/
BITCLR(RGPIO->GPAEN, Hw11); /* DXB1_IRQ input mode*/
BITCSET(RGPIO->EINTSEL0, Hw32 - Hw24, 11<<24); /*GPIO_A11*/
#elif defined(__USE_DXB0_IRQ__)
BITCLR(RGPIO->GPDFN1, Hw8 - Hw4); /* DXB0_IRQ Set GPIO mode*/
BITCLR(RGPIO->GPDEN, Hw9); /* DXB0_IRQ input mode*/
BITCSET(RGPIO->EINTSEL0, Hw32 - Hw24, 20<<24); /*GPIO_D9*/
#endif /*__USE_DXB1_IRQ__*/
BITSET(RPIC->POL0, 1<<IRQ_TC317X);
#endif
}
void VIOC_WDMA_SetImageDither(VIOC_WDMA *pWDMA, unsigned int nDithEn, unsigned int nDithSel, unsigned char mat[4][4])
{
#if 0
pWDMA->uDMAT.bREG.DITH00 = mat[0][0];
pWDMA->uDMAT.bREG.DITH01 = mat[0][1];
pWDMA->uDMAT.bREG.DITH02 = mat[0][2];
pWDMA->uDMAT.bREG.DITH03 = mat[0][3];
pWDMA->uDMAT.bREG.DITH10 = mat[1][0];
pWDMA->uDMAT.bREG.DITH11 = mat[1][1];
pWDMA->uDMAT.bREG.DITH12 = mat[1][2];
pWDMA->uDMAT.bREG.DITH13 = mat[1][3];
pWDMA->uDMAT.bREG.DITH20 = mat[2][0];
pWDMA->uDMAT.bREG.DITH21 = mat[2][1];
pWDMA->uDMAT.bREG.DITH22 = mat[2][2];
pWDMA->uDMAT.bREG.DITH23 = mat[2][3];
pWDMA->uDMAT.bREG.DITH30 = mat[3][0];
pWDMA->uDMAT.bREG.DITH31 = mat[3][1];
pWDMA->uDMAT.bREG.DITH32 = mat[3][2];
pWDMA->uDMAT.bREG.DITH33 = mat[3][3];
pWDMA->uCTRL.bREG.DITHEN = nDithEn; /* Dither Enable*/
pWDMA->uCTRL.bREG.DITHSEL = nDithSel; /*Dither Mode 0: LSB Toggle mode, 1: Adder Mode */
#endif
BITCSET(pWDMA->uDMAT.nREG[0], 0x00007777, mat[0][3] << 12 | mat[0][2] << 8 | mat[0][1] << 4 | mat[0][0] );
BITCSET(pWDMA->uDMAT.nREG[0], 0x77770000, mat[1][3] << 28 | mat[1][2] << 24 | mat[1][1] << 18 | mat[1][0] << 16 );
BITCSET(pWDMA->uDMAT.nREG[1], 0x00007777, mat[2][3] << 12 | mat[2][2] << 8 | mat[2][1] << 4 | mat[2][0] );
BITCSET(pWDMA->uDMAT.nREG[1], 0x77770000, mat[3][3] << 28 | mat[3][2] << 24 | mat[3][1] << 18 | mat[3][0] << 16 );
BITCSET(pWDMA->uCTRL.nREG, 1<<27 | 1<<24, nDithEn << 24 | nDithSel << 27 );
#if 0
pWDMA->uCTRL.bREG.DITHEN = nDithEn;
pWDMA->uCTRL.bREG.DITHSEL = nDithSel;
pWDMA->uDMAT.bREG.MAT0 = nDithMatrix[0];
pWDMA->uDMAT.bREG.MAT1 = nDithMatrix[1];
pWDMA->uDMAT.bREG.MAT2 = nDithMatrix[2];
pWDMA->uDMAT.bREG.MAT3 = nDithMatrix[3];
#endif
}
void VIOC_WDMA_SetImageRateControl(VIOC_WDMA *pWDMA, unsigned int enable, unsigned int rate)
{
if ( enable == TRUE)
{
//pWDMA->uRATE.bREG.REN = 1;
//pWDMA->uRATE.bREG.MAXRATE = rate;/* 0 ~~ 255*/
BITCSET(pWDMA->uRATE.nREG, 0x80FF0000, 1<<31 | rate << 16 );
}
else
{
//pWDMA->uRATE.bREG.REN = 0;
BITCSET(pWDMA->uRATE.nREG, 1<<31, 0<<31);
}
//pWDMA->uCTRL.bREG.UPD = 1;
BITCSET(pWDMA->uCTRL.nREG, 1<<16, 1<<16);
}
/*****************************************************************************
* Function Name : static void Init_IR_Port(void);
* Description : IR port register init
* Arguments :
******************************************************************************/
static void Init_IR_Port(void)
{
#if defined(CONFIG_ARCH_TCC892X)
tcc_gpio_config(TCC_GPG(17), GPIO_FN7|GPIO_OUTPUT|GPIO_LOW);
#else
PGPIO pGpioA = (volatile PGPIO)tcc_p2v(HwGPIOA_BASE);
BITCSET(pGpioA->GPAFN0, (Hw20 | Hw21 | Hw22 | Hw23), Hw20); //GPIO_A5
#endif
}
/*------------------------------------------------------------------
Gre2d_SetBCh_address
graphic engine BACK End channel address 0,1,2 setting
-------------------------------------------------------------------*/
void Gre2d_SetBCh_address(G2D_CHANNEL ch, unsigned int add0, unsigned int add1, unsigned int add2)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
if(ch == DEST_CH)
{
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->BCH_DADDR0.nREG, 0xFFFFFFFF, add0); // pHwOVERLAYMIXER->BCH_DADDR0
BITCSET(pHwOVERLAYMIXER->BCH_DADDR1.nREG, 0xFFFFFFFF, add1); // pHwOVERLAYMIXER->BCH_DADDR0
BITCSET(pHwOVERLAYMIXER->BCH_DADDR2.nREG, 0xFFFFFFFF, add2); // pHwOVERLAYMIXER->BCH_DADDR0
#else
pHwOVERLAYMIXER->BCH_DADDR0 = (unsigned int)add0; // pHwOVERLAYMIXER->BCH_DADDR0
pHwOVERLAYMIXER->BCH_DADDR1 = (unsigned int)add1;
pHwOVERLAYMIXER->BCH_DADDR2 = (unsigned int)add2;
#endif
}
}
void VIOC_VIN_SetDemuxPort(VIOC_VIN_DEMUX *pVINDEMUX, unsigned int p0, unsigned int p1, unsigned int p2, unsigned int p3)
{
//pVINDEMUX->uVIN_DEMUX_CTRL.bVIN_DEMUX_CTRL.sel0 = p0;
//pVINDEMUX->uVIN_DEMUX_CTRL.bVIN_DEMUX_CTRL.sel1 = p1;
//pVINDEMUX->uVIN_DEMUX_CTRL.bVIN_DEMUX_CTRL.sel2 = p2;
//pVINDEMUX->uVIN_DEMUX_CTRL.bVIN_DEMUX_CTRL.sel3 = p3;
BITCSET(pVINDEMUX->uVIN_DEMUX_CTRL.nREG, 0x77770000, (p0 << 16) | (p1 << 20) | (p2 << 24) | (p3 << 28));
}
/*------------------------------------------------------------------
Gre2d_SetFCh_address
graphic engine Front End channel address 0,1,2 setting
-------------------------------------------------------------------*/
void Gre2d_SetFCh_address(G2D_CHANNEL ch, unsigned int add0, unsigned int add1, unsigned int add2)
{
POVERLAYMIXER pHwOVERLAYMIXER;
pHwOVERLAYMIXER = (volatile POVERLAYMIXER)tcc_p2v(HwOVERLAYMIXER_BASE);
switch(ch)
{
case FCH0_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->FCH0_SADDR0.nREG, 0xFFFFFFFF, add0);
BITCSET(pHwOVERLAYMIXER->FCH0_SADDR1.nREG, 0xFFFFFFFF, add1);
BITCSET(pHwOVERLAYMIXER->FCH0_SADDR2.nREG, 0xFFFFFFFF, add2);
#else
pHwOVERLAYMIXER->FCH0_SADDR0 = (unsigned int)add0; // pHwOVERLAYMIXER->FCH0_SADDR0
pHwOVERLAYMIXER->FCH0_SADDR1 = (unsigned int)add1;
pHwOVERLAYMIXER->FCH0_SADDR2 = (unsigned int)add2;
#endif
break;
case FCH1_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->FCH1_SADDR0.nREG, 0xFFFFFFFF, add0);
BITCSET(pHwOVERLAYMIXER->FCH1_SADDR1.nREG, 0xFFFFFFFF, add1);
BITCSET(pHwOVERLAYMIXER->FCH1_SADDR2.nREG, 0xFFFFFFFF, add2);
#else
pHwOVERLAYMIXER->FCH1_SADDR0 = (unsigned int)add0;
pHwOVERLAYMIXER->FCH1_SADDR1 = (unsigned int)add1;
pHwOVERLAYMIXER->FCH1_SADDR2 = (unsigned int)add2;
#endif
break;
case FCH2_CH:
#if defined(CONFIG_ARCH_TCC892X)
BITCSET(pHwOVERLAYMIXER->FCH2_SADDR0.nREG, 0xFFFFFFFF, add0);
BITCSET(pHwOVERLAYMIXER->FCH2_SADDR1.nREG, 0xFFFFFFFF, add1);
BITCSET(pHwOVERLAYMIXER->FCH2_SADDR2.nREG, 0xFFFFFFFF, add2);
#else
pHwOVERLAYMIXER->FCH2_SADDR0 = (unsigned int)add0;
pHwOVERLAYMIXER->FCH2_SADDR1 = (unsigned int)add1;
pHwOVERLAYMIXER->FCH2_SADDR2 = (unsigned int)add2;
#endif
break;
default:
break;
}
}
static int tm070rdh11_set_power(struct lcd_panel *panel, int on)
{
struct lcd_platform_data *pdata = &(panel->dev);
printf("%s : %d ~ \n", __func__, on);
if (on) {
tcclcd_gpio_set_value(pdata->reset, 1);
lcd_delay_us(1000);
tcclcd_gpio_set_value(pdata->power_on, 1);
lcd_delay_us(1000);
tcclcd_gpio_set_value(pdata->reset, 0);
lcd_delay_us(1000);
tcclcd_gpio_set_value(pdata->reset, 1);
mdelay(10);
lcdc_initialize(pdata->lcdc_num, panel);
LCDC_IO_Set(pdata->lcdc_num, panel->bus_width);
// lcd port current
BITCSET(HwGPIOC->GPCD0,0xFFFFFFFF, 0xAAAAAAAA);
BITCSET(HwGPIOC->GPCD1,0x00FFFFFF, 0x00FFAAAA);
BITCSET(HwGPIOC->GPFN3, HwPORTCFG_GPFN0_MASK , HwPORTCFG_GPFN0(0));
BITCSET(HwGPIOC->GPEN, Hw24 ,Hw24);
BITCSET(HwGPIOC->GPDAT, Hw24 ,0);
mdelay(16);
}
else
{
tcclcd_gpio_set_value(pdata->display_on, 0);
mdelay(10);
tcclcd_gpio_set_value(pdata->reset, 0);
tcclcd_gpio_set_value(pdata->power_on, 0);
LCDC_IO_Disable(pdata->lcdc_num, panel->bus_width);
}
return 0;
}
void VIOC_DISP_SetColorEnhancement(VIOC_DISP *pDISP, signed char contrast, signed char brightness, signed char hue )
{
/*
pDISP->uLENH.bREG.CONRAST = contrast;
pDISP->uLENH.bREG.BRIGHTNESS = brightness;
pDISP->uLENH.bREG.HUE = hue;
*/
BITCSET(pDISP->uLENH.nREG, 0x00FFFFFF, hue << 16 | brightness << 8 | contrast );
}
