/* The port lock is not held. */ static void ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port; unsigned long flags; int baud, brg; baud = uart_get_baud_rate(port, termios, old, 1200, 76800); spin_lock_irqsave(&up->port.lock, flags); brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); if (UART_ENABLE_MS(&up->port, termios->c_cflag)) up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; else up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); uart_update_timeout(port, termios->c_cflag, baud); spin_unlock_irqrestore(&up->port.lock, flags); }
static void __init ip22zilog_init_hw(void) { int i; for (i = 0; i < NUM_CHANNELS; i++) { struct uart_ip22zilog_port *up = &ip22zilog_port_table[i]; struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(&up->port); unsigned long flags; int baud, brg; spin_lock_irqsave(&up->port.lock, flags); if (ZS_IS_CHANNEL_A(up)) { write_zsreg(channel, R9, FHWRES); ZSDELAY_LONG(); (void) read_zsreg(channel, R0); } /* Normal serial TTY. */ up->parity_mask = 0xff; up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; up->curregs[R4] = PAR_EVEN | X16CLK | SB1; up->curregs[R3] = RxENAB | Rx8; up->curregs[R5] = TxENAB | Tx8; up->curregs[R9] = NV | MIE; up->curregs[R10] = NRZ; up->curregs[R11] = TCBR | RCBR; baud = 9600; brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); up->curregs[R12] = (brg & 0xff); up->curregs[R13] = (brg >> 8) & 0xff; up->curregs[R14] = BRENAB; __load_zsregs(channel, up->curregs); /* set master interrupt enable */ write_zsreg(channel, R9, up->curregs[R9]); spin_unlock_irqrestore(&up->port.lock, flags); } }
static int __init ip22zilog_console_setup(struct console *con, char *options) { struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; unsigned long flags; int baud, brg; printk("Console: ttyS%d (IP22-Zilog)\n", con->index); /* Get firmware console settings. */ ip22serial_console_termios(con, options); /* Firmware console speed is limited to 150-->38400 baud so * this hackish cflag thing is OK. */ switch (con->cflag & CBAUD) { case B150: baud = 150; break; case B300: baud = 300; break; case B600: baud = 600; break; case B1200: baud = 1200; break; case B2400: baud = 2400; break; case B4800: baud = 4800; break; default: case B9600: baud = 9600; break; case B19200: baud = 19200; break; case B38400: baud = 38400; break; }; brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); spin_lock_irqsave(&up->port.lock, flags); up->curregs[R15] = BRKIE; ip22zilog_convert_to_zs(up, con->cflag, 0, brg); __ip22zilog_startup(up); spin_unlock_irqrestore(&up->port.lock, flags); return 0; }
static void __init ip22zilog_prepare(void) { struct uart_ip22zilog_port *up; struct zilog_layout *rp; int channel, chip; /* * Temporary fix. */ for (channel = 0; channel < NUM_CHANNELS; channel++) spin_lock_init(&ip22zilog_port_table[channel].port.lock); ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; up = &ip22zilog_port_table[0]; for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) up[channel].next = &up[channel - 1]; up[channel].next = NULL; for (chip = 0; chip < NUM_IP22ZILOG; chip++) { if (!ip22zilog_chip_regs[chip]) { ip22zilog_chip_regs[chip] = rp = get_zs(chip); up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; /* In theory mapbase is the physical address ... */ up[(chip * 2) + 0].port.mapbase = (unsigned long) ioremap((unsigned long) &rp->channelB, 8); up[(chip * 2) + 1].port.mapbase = (unsigned long) ioremap((unsigned long) &rp->channelA, 8); } /* Channel A */ up[(chip * 2) + 0].port.iotype = UPIO_MEM; up[(chip * 2) + 0].port.irq = zilog_irq; up[(chip * 2) + 0].port.uartclk = ZS_CLOCK; up[(chip * 2) + 0].port.fifosize = 1; up[(chip * 2) + 0].port.ops = &ip22zilog_pops; up[(chip * 2) + 0].port.type = PORT_IP22ZILOG; up[(chip * 2) + 0].port.flags = 0; up[(chip * 2) + 0].port.line = (chip * 2) + 0; up[(chip * 2) + 0].flags = 0; /* Channel B */ up[(chip * 2) + 1].port.iotype = UPIO_MEM; up[(chip * 2) + 1].port.irq = zilog_irq; up[(chip * 2) + 1].port.uartclk = ZS_CLOCK; up[(chip * 2) + 1].port.fifosize = 1; up[(chip * 2) + 1].port.ops = &ip22zilog_pops; up[(chip * 2) + 1].port.type = PORT_IP22ZILOG; up[(chip * 2) + 1].port.line = (chip * 2) + 1; up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A; } for (channel = 0; channel < NUM_CHANNELS; channel++) { struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel]; int brg; /* Normal serial TTY. */ up->parity_mask = 0xff; up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; up->curregs[R4] = PAR_EVEN | X16CLK | SB1; up->curregs[R3] = RxENAB | Rx8; up->curregs[R5] = TxENAB | Tx8; up->curregs[R9] = NV | MIE; up->curregs[R10] = NRZ; up->curregs[R11] = TCBR | RCBR; brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR); up->curregs[R12] = (brg & 0xff); up->curregs[R13] = (brg >> 8) & 0xff; up->curregs[R14] = BRENAB; } }
/* Shared by TTY driver and serial console setup. The port lock is held * and local interrupts are disabled. */ static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, unsigned int iflag, unsigned long baud) { int brg; /* Switch to external clocking for IrDA high clock rates. That * code could be re-used for Midi interfaces with different * multipliers */ if (baud >= 115200 && ZS_IS_IRDA(uap)) { uap->curregs[R4] = X1CLK; uap->curregs[R11] = RCTRxCP | TCTRxCP; uap->curregs[R14] = 0; /* BRG off */ uap->curregs[R12] = 0; uap->curregs[R13] = 0; uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; } else { switch (baud) { case ZS_CLOCK/16: /* 230400 */ uap->curregs[R4] = X16CLK; uap->curregs[R11] = 0; uap->curregs[R14] = 0; break; case ZS_CLOCK/32: /* 115200 */ uap->curregs[R4] = X32CLK; uap->curregs[R11] = 0; uap->curregs[R14] = 0; break; default: uap->curregs[R4] = X16CLK; uap->curregs[R11] = TCBR | RCBR; brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); uap->curregs[R12] = (brg & 255); uap->curregs[R13] = ((brg >> 8) & 255); uap->curregs[R14] = BRENAB; } uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; } /* Character size, stop bits, and parity. */ uap->curregs[3] &= ~RxN_MASK; uap->curregs[5] &= ~TxN_MASK; switch (cflag & CSIZE) { case CS5: uap->curregs[3] |= Rx5; uap->curregs[5] |= Tx5; uap->parity_mask = 0x1f; break; case CS6: uap->curregs[3] |= Rx6; uap->curregs[5] |= Tx6; uap->parity_mask = 0x3f; break; case CS7: uap->curregs[3] |= Rx7; uap->curregs[5] |= Tx7; uap->parity_mask = 0x7f; break; case CS8: default: uap->curregs[3] |= Rx8; uap->curregs[5] |= Tx8; uap->parity_mask = 0xff; break; }; uap->curregs[4] &= ~(SB_MASK); if (cflag & CSTOPB) uap->curregs[4] |= SB2; else uap->curregs[4] |= SB1; if (cflag & PARENB) uap->curregs[4] |= PAR_ENAB; else uap->curregs[4] &= ~PAR_ENAB; if (!(cflag & PARODD)) uap->curregs[4] |= PAR_EVEN; else uap->curregs[4] &= ~PAR_EVEN; uap->port.read_status_mask = Rx_OVR; if (iflag & INPCK) uap->port.read_status_mask |= CRC_ERR | PAR_ERR; if (iflag & (BRKINT | PARMRK)) uap->port.read_status_mask |= BRK_ABRT; uap->port.ignore_status_mask = 0; if (iflag & IGNPAR) uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; if (iflag & IGNBRK) { uap->port.ignore_status_mask |= BRK_ABRT; if (iflag & IGNPAR) uap->port.ignore_status_mask |= Rx_OVR; } if ((cflag & CREAD) == 0) uap->port.ignore_status_mask = 0xff; }