//-------------------------------------------------------------------------------
// Set Center freq
// khz - offset from beginning of band in KHz (band 860480 - 879510 KHz)
void MRF_freq868_set(uint8_t chan, uint16_t khz)
{
uint32_t freq_khz = 860480 + khz; // beginning of the band + offset
mrfDrv_t * mrf_p = &mrf[chan];
BSP_USE_CRITICAL();
BSP_CRITICAL(BSP_ASSERT(mrf_p->state == MRF_STATE_DISABLE));
BSP_ASSERT((freq_khz >= 860480) && (freq_khz <= 879510)); // min-max values of the band
mrf_p->reg_set((MRF_CFSREG) | ((uint16_t)MRF_FREQB_868_VAL_KHZ(freq_khz))); // 0xAxxx
#ifdef MRF_TRACE_SETUP_ENABLE
BSP_TRACE("ch%d freq = 860480 + %d KHz", chan, khz);
#endif
}
void BSP_Delay(uint16_t usec)
{
BSP_ASSERT(usec < BSP_DELAY_MAX_USEC);
//TA0R = 0; /* initial count */
//TA0CCR0 = BSP_TIMER_CLK_MHZ*usec; /* compare count. (delay in ticks) */
/* Start the timer in UP mode */
//TA0CTL |= MC_1;
/* Loop till compare interrupt flag is set */
//while(!(TA0CCTL0 & CCIFG));
/* Stop the timer */
//TA0CTL &= ~(MC_1);
/* Clear the interrupt flag */
//TA0CCTL0 &= ~CCIFG;
// [BM] We need to use TA1 for delay function, because TA0 is already occupied
TA1R = 0;
TA1CCR0 = BSP_TIMER_CLK_MHZ * usec;
TA1CTL |= MC_1;
while (!(TA1CCTL0 & CCIFG)) ;
TA1CTL &= ~(MC_1);
TA1CCTL0 &= ~CCIFG;
}
// ----------------------------------------------------------------------------
// Запуск таймера на миллисекундный интервал от SWTIMERS_MIN_TIME до SWTIMERS_MAX_TIME [ms]
void BSP_timer_start_ms(uint8_t id, uint32_t timeout_ms,
swTimerMode_t mode, swTimerHandler handler)
{
BSP_USE_CRITICAL();
BSP_ASSERT(id < SWTIMERS_MAX); // wrong timer id
BSP_ASSERT(timeout_ms >= SWTIMERS_MIN_TIME); // wrong timeout
BSP_ASSERT(timeout_ms <= SWTIMERS_MAX_TIME); // wrong timeout
// Установка состояния
BSP_CRITICAL(
swTimers[id].is_stopped = 0;
swTimers[id].is_fired = 0;
swTimers[id].counter = 0;
swTimers[id].threshold = timeout_ms / TIMER_ISR_PERIOD_MSEC;
swTimers[id].handler = handler;
swTimers[id].mode = mode;
);
//-------------------------------------------------------------------------------
// Set Tx power
void MRF_txpower_set(uint8_t chan, uint8_t power)
{
uint16_t power_dBm;
mrfDrv_t * mrf_p = &mrf[chan];
BSP_USE_CRITICAL();
BSP_CRITICAL(BSP_ASSERT(mrf_p->state == MRF_STATE_DISABLE));
if (power == MRF_TX_POWER_LOW) { power_dBm = MRF_OTXPWR_17D5; }
else if (power == MRF_TX_POWER_MEDIUM) { power_dBm = MRF_OTXPWR_10D5; }
else if (power == MRF_TX_POWER_FULL) { power_dBm = MRF_OTXPWR_0; }
else { BSP_ASSERT(0);}
// TXCREG = MODPLY 0 MODBW 0010 no 0 OTXPWR 000
// Modulation polarity = Default, modulation bandwidth = 45 KHz,
// transmit power = 0 or -10.5 or -17.7 dBm
mrf_p->reg_set(MRF_TXCREG | MRF_MODBW_45K | power_dBm); // 0x98xx
#ifdef MRF_TRACE_SETUP_ENABLE
BSP_TRACE("ch%d power = %d", chan, power);
#endif
}
//-------------------------------------------------------------------------------
// Set Sync byte (0x2Dxx)
void MRF_sync_set(uint8_t chan, uint8_t sync_byte)
{
mrfDrv_t * mrf_p = &mrf[chan];
BSP_USE_CRITICAL();
BSP_CRITICAL(BSP_ASSERT(mrf_p->state == MRF_STATE_DISABLE));
mrf_p->sync_byte = sync_byte;
// SYNBREG = SYNCB xxxx xxxx
mrf_p->reg_set(MRF_SYNBREG | (sync_byte & MRF_SYNCB_MASK)); // 0xCExx
#ifdef MRF_TRACE_SETUP_ENABLE
BSP_TRACE("ch%d sync %02X", chan, sync_byte);
#endif
}
/**************************************************************************************************
* @fn BSP_Init
*
* @brief Initialize the board and drivers.
*
* @param none
*
* @return none
**************************************************************************************************
*/
void BSP_Init(void)
{
BSP_INIT_BOARD();
BSP_INIT_DRIVERS();
/*-------------------------------------------------------------
* Run time integrity checks. Perform only if asserts
* are enabled.
*/
#ifdef BSP_ASSERTS_ARE_ON
/* verify endianess is correctly specified */
{
uint16_t test = 0x00AA; /* first storage byte of 'test' is non-zero for little endian */
BSP_ASSERT(!(*((uint8_t *)&test)) == !BSP_LITTLE_ENDIAN); /* endianess mismatch */
}
#endif
}
/**************************************************************************************************
* @fn BSP_Delay
*
* @brief Sleep for the requested amount of time.
*
* @param # of microseconds to sleep.
*
* @return none
**************************************************************************************************
*/
void BSP_Delay(uint32_t usec)
{
BSP_ASSERT(usec < BSP_DELAY_MAX_USEC);
TAR = 0; /* initial count */
TACCR0 = BSP_TIMER_CLK_MHZ*usec; /* compare count. (delay in ticks) */
/* Start the timer in UP mode */
TACTL |= MC_1;
/* Loop till compare interrupt flag is set */
while(!(TACCTL0 & CCIFG));
/* Stop the timer */
TACTL &= ~(MC_1);
/* Clear the interrupt flag */
TACCTL0 &= ~CCIFG;
}
/**************************************************************************************************
* @fn BSP_Delay
*
* @brief Sleep for the requested amount of time.
*
* @param # of microseconds to sleep.
*
* @return none
**************************************************************************************************
*/
void BSP_Delay(uint16_t usec)
{
BSP_ASSERT(usec < BSP_DELAY_MAX_USEC);
TA0R = 0; //initial count
TA0CCR0 = BSP_TIMER_CLK_MHZ*usec; //compare count. (delay in ticks)
/* Start the timer in UP mode */
TA0CTL = TASSEL_2 + MC_1 + TACLR;
/* Loop till compare interrupt flag is set */
while(!(TA0CCTL0 & CCIFG));
/* Stop the timer */
TA0CTL &= ~(MC_1);
/* Clear the interrupt flag */
TA0CCTL0 &= ~CCIFG;
}
/**************************************************************************************************
* @fn BSP_Init
*
* @brief Initialize the board and drivers.
*
* @param none
*
* @return none
**************************************************************************************************
*/
void BSP_Init(void)
{
BSP_INIT_BOARD();
/************* MSP-EXP430F6137Rx Edit: HAL to control LEDs & BUTTONs*********/
// BSP_INIT_DRIVERS();
/****************SimpliciTI BSP to not control LEDS & BUTTONS****************/
/*-------------------------------------------------------------
* Run time integrity checks. Perform only if asserts
* are enabled.
*/
#ifdef BSP_ASSERTS_ARE_ON
/* verify endianess is correctly specified */
{
uint16_t test = 0x00AA; /* first storage byte of 'test' is non-zero for little endian */
BSP_ASSERT(!(*((uint8_t *)&test)) == !BSP_LITTLE_ENDIAN); /* endianess mismatch */
}
#endif
}
//-------------------------------------------------------------------------------
// Configure ADC multiplexor with given ADC channel and enable ADC
void BSP_adc_enable(uint8_t channel)
{
switch(channel) {
#ifdef ADC0_ENABLED
case 0: ADC_ON(ADC_INPUT_0); break;
#endif
#ifdef ADC1_ENABLED
case 1: ADC_ON(ADC_INPUT_1); break;
#endif
#ifdef ADC2_ENABLED
case 2: ADC_ON(ADC_INPUT_2); break;
#endif
#ifdef ADC3_ENABLED
case 3: ADC_ON(ADC_INPUT_3); break;
#endif
#ifdef ADC4_ENABLED
case 4: ADC_ON(ADC_INPUT_4); break;
#endif
#ifdef ADC5_ENABLED
case 5: ADC_ON(ADC_INPUT_5); break;
#endif
#ifdef ADC6_ENABLED
case 6: ADC_ON(ADC_INPUT_6); break;
#endif
#ifdef ADC7_ENABLED
case 7: ADC_ON(ADC_INPUT_7); break;
#endif
#ifdef ADC8_ENABLED
case 8: ADC_ON(ADC_INPUT_8); break;
#endif
#ifdef ADC9_ENABLED
case 9: ADC_ON(ADC_INPUT_9); break;
#endif
#ifdef ADC10_ENABLED
case 10: ADC_ON(ADC_INPUT_10); break;
#endif
default: BSP_ASSERT(0); break;
}
adc_chan = channel;
}
void MRF_init(uint8_t chan)
{
mrfDrv_t * mrf_p = &mrf[chan];
// Hardware interfaces init
// SPI is already inialized in BSP
if (chan == 0) {
// Setup the functions for SPI exchange
mrf_p->cs_on = &(MRF_spi_cs_on);
mrf_p->cs_off = &(MRF_spi_cs_off);
mrf_p->miso_is_up = &(MRF_spi_miso_is_up);
mrf_p->spi_word = &(MRF_spi_word);
MRF_IRO_INIT(); // External falling edge interrupt IRO from MRF49
}
#ifdef MRF48XA_PAIR
else if (chan == 1) {
// Setup the functions for SPI exchange
mrf_p->cs_on = &MRF1_spi_cs_on;
mrf_p->cs_off = &MRF1_spi_cs_off;
mrf_p->miso_is_up = &MRF1_spi_miso_is_up;
mrf_p->spi_word = &MRF1_spi_word;
MRF1_IRO_INIT(); // External falling edge interrupt IRO from MRF49
}
#endif
else {
BSP_ASSERT(0);
}
// Setup buffers and counters
mrf_p->txPkt.len = 0;
mrf_p->txPkt.bytes_processed = 0;
mrf_p->rxPkt.bytes_processed = 0;
mrf_p->rxPkt.len = 0;
mrf_p->get_rss = 0;
// Dummy read of status registers to clear Power on reset flag
mrf_p->status_get(); // 0x0000
// Disabled state set
MRF_disable(chan);
// Init all registers
// PMCREG = RXCEN 0 BBCEN 0 TXCEN 0 SYNEN 0 OSCEN 1 LBDEN 0 WUTEN 0 CLKOEN 1
// (Idle mode - only Crystal enabled)
mrf_p->reg_set(MRF_PMCREG | MRF_OSCEN | MRF_CLKODIS); // 0x8209
delay_ms(5);
// GENCREG = TXDEN 0 FIFOEN 1 FBS 10 LCS 0101
// Tx = disable, FIFO = enable, band = 868, capacitor = 11pf
mrf_p->reg_set(MRF_GENCREG | MRF_FIFOEN | MRF_FBS_868 | (MRF_LCS_11PF & MRF_LCS_MASK)); // 0x8065
// PMCREG = RXCEN 0 BBCEN 0 TXCEN 0 SYNEN 0 OSCEN 1 LBDEN 0 WUTEN 0 CLKOEN 1
// (Idle mode - only Crystal enabled)
mrf_p->reg_set(MRF_PMCREG | MRF_OSCEN | MRF_CLKODIS); // 0x8209
// MRF_CFSREG = FREQB
// Freq = 860.48 Mhz - beginning of the band
MRF_freq868_set(chan, 0); // 0xAxxx
// DRSREG = DRPE 0 DRPV 0100011
// Disables the prescaler, data rate = approx. 9600 bps baud
mrf_p->reg_set(MRF_DRSREG | MRF_DPRV_VAL(9600)); // 0xC623 (default)
// RXCREG = FINTDIO 1 DIORT 10 RXBW 110 RXLNA 00 DRSSIT 011
// DIO output, DIO mode = Slow, Bandwidth = 67 kHz,
// LNA = 0 dB, digital RSSI thr = -85 dB
mrf_p->reg_set(MRF_RXCREG | MRF_FINTDIO | MRF_DIORT_SLOW | MRF_RXBW_67K | MRF_RXLNA_0DB | MRF_DRSSIT_85db); // 0x96C3
// BBFCREG = ACRLC 0 MCRLC 0 no 1 FTYPE 0 no 1 DQTI 100
// Clock recovery lock = Manual, clock recovery lock = Slow,
// baseband filter = digital filter,
// data Quality Threshold Indicator = 4 (high sensitive)
mrf_p->reg_set(MRF_BBFCREG | (4 & MRF_DQTI_MASK)); // 0xC22C (default)
// FIFORSTREG = FFBC 1000 SYCHLEN 0 FFSC 0 FSCF 1 DRSTM 1
// Bits before interrupt = 8, sync = 2 bytes,
// FIFO will fill = Only after sync, sync latch = Enable,
// disable (sensitive) reset mode
mrf_p->reg_set(MRF_FIFORSTREG | ((8 << 4) & MRF_FFBC_MASK | MRF_FSCF | MRF_DRSTM)); // 0xCA83
// Sync = 0xFF
MRF_sync_set(chan, 0xFF); // 0xCEFF
// AFCCREG = AUTOMS 00 ARFO 11 MFCS 0 HAM 0 FOREN 0 FOFEN 0
mrf_p->reg_set(MRF_AFCCREG | MRF_AUTOMS_OFF | MRF_ARFO_3to4); // 0xC430
// Set deviation and full Tx power
MRF_txpower_set(chan, MRF_TX_POWER_FULL); // 0x98xx
// PLLCREG = no 0 CBTC 00 no 1 PDDS 0 PLLDD 1 no 1 PLLBWB 0
mrf_p->reg_set(MRF_PLLCREG | MRF_CBTC_2m | MRF_PLLDD); // 0xCC16
// WTSREG = WTEV 00000 WTMV 0000000
// Wake-up = 0.5 ms
mrf_p->reg_set(MRF_WTSREG); // 0xE000
// DCSREG = DCMV 0000000 DCMEN 0
// Duty Cycle mode = Disable
mrf_p->reg_set(MRF_DCSREG); // 0xC800
// BCSREG = COFSB 000 no 0 LBDVB 0000
// Clock Output Frequency = 1 MHz,
// Threshold voltage level = 2.25 V
mrf_p->reg_set(0xC000); // 0xC000
// Disabled state set
MRF_disable(chan);
// Dummy read of status registers
mrf_p->status_get(); // 0x0000
// enable interrupt last, just in case they're already globally enabled
if (chan == 0) {
MRF_IRO_ENABLE();
}
#ifdef MRF48XA_PAIR
else if (chan == 1) {
MRF1_IRO_ENABLE();
}
#endif
#ifdef MRF_TRACE_SETUP_ENABLE
BSP_TRACE("ch%d init ok", chan);
#endif
}
