//call after set clock
void set_usb_phy_power(amlogic_usb_config_t * usb_cfg,int is_on)
{
unsigned long delay = 1000;
int port_idx = 100;
unsigned int port = usb_cfg->base_addr & USB_PHY_PORT_MSK;
usb_peri_reg_t *peri_a,*peri_b,*peri_c,*peri_d,*peri;
peri = NULL;
usb_ctrl_data_t control;
usb_adp_bc_data_t adp_bc;
peri_a = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_A);
peri_b = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_B);
// peri_c = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_C);
// peri_d = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_D);
if(port == USB_PHY_PORT_A){
peri = peri_a;
port_idx = 0;
}else if(port == USB_PHY_PORT_B){
peri = peri_b;
port_idx = 1;
}else if(port == USB_PHY_PORT_C){
peri = peri_c;
port_idx = 2;
}else if(port == USB_PHY_PORT_D){
peri = peri_d;
port_idx = 3;
}
if(is_on){
control.d32 = peri->ctrl;
control.b.por = 0;
peri->ctrl = control.d32;
udelay(delay);
/* read back clock detected flag*/
control.d32 = peri->ctrl;
if(!control.b.clk_detected){
printf("USB (%d) PHY Clock not detected!\n",port_idx);
}
if(port == USB_PHY_PORT_B){
adp_bc.d32 = peri->adp_bc;
adp_bc.b.aca_enable = 1;
peri->adp_bc = adp_bc.d32;
udelay(50);
adp_bc.d32 = peri->adp_bc;
if(adp_bc.b.aca_pin_float){
printf("USB-B ID detect failed!\n");
printf("Please use the chip after version RevA1!\n");
return -1;
}
}
}else{
control.d32 = peri->ctrl;
control.b.por = 1;
peri->ctrl = control.d32;
}
udelay(delay);
}
void cec_power_on(void)
{
/*Enable GPIOD_5*/
//writel((readl(CBUS_REG_ADDR(PREG_PAD_GPIO2_O)) | (1<<21)), CBUS_REG_ADDR(PREG_PAD_GPIO2_O));
//writel((readl(CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N)) & (~(1<<21))), CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N));
/*Enable cts_hdmi_sys_clk*/
writel(((readl(CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL)) & (~((0x7<<9) | 0x7f))) | (1<<8)), CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL));
}
// In order to prevent system hangup, add check_cts_hdmi_sys_clk_status() to check
static void check_cts_hdmi_sys_clk_status(void)
{
int i;
for(i = 0; i < GATE_NUM; i++){
if(!(aml_read_reg32(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr)) & (1<<hdmi_gate[i].gate_bit))){
aml_set_reg32_bits(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr), 1, hdmi_gate[i].gate_bit, 1);
}
}
}
// In order to prevent system hangup, add check_cts_hdmi_sys_clk_status() to check
static void check_cts_hdmi_sys_clk_status(void)
{
int i;
for(i = 0; i < GATE_NUM; i++){
if(!(aml_read_reg32(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr)) & (1<<hdmi_gate[i].gate_bit))){
printk("HDMI Gate Clock is off, turn on now\n");
aml_set_reg32_bits(CBUS_REG_ADDR(hdmi_gate[i].cbus_addr), 1, hdmi_gate[i].gate_bit, 1);
}
}
}
//static int reset_count = 0;
//int set_usb_phy_clk(struct lm_device * plmdev,int is_enable)
//{
static int set_usb_phy_clock(amlogic_usb_config_t * usb_cfg)
{
int port_idx;
usb_peri_reg_t * peri;
usb_config_data_t config;
usb_ctrl_data_t control;
int clk_sel,clk_div;
unsigned int port = usb_cfg->base_addr & USB_PHY_PORT_MSK;
int time_dly = 500; //usec
if(!usb_cfg)
return -1;
if(port == USB_PHY_PORT_A){
port_idx = 0;
peri = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_A);
}else if(port == USB_PHY_PORT_B){
port_idx = 1;
peri = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_B);
}else if(port == USB_PHY_PORT_C){
port_idx = 2;
peri = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_C);
}else if(port == USB_PHY_PORT_D){
port_idx = 3;
peri = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_D);
}else{
printf("usb base address error: %x\n",usb_cfg->base_addr);
return -1;
}
writel((1 << 2),P_RESET1_REGISTER);
printf("USB (%d) peri reg base: %x\n",port_idx,(uint32_t)peri);
clk_sel = usb_cfg->clk_selecter;
clk_div = usb_cfg->pll_divider;
config.d32 = peri->config;
config.b.clk_sel = clk_sel;
config.b.clk_div = clk_div;
config.b.clk_en = 1;
peri->config = config.d32;
printf("USB (%d) use clock source: %s\n",port_idx,g_clock_src_name_m6[clk_sel]);
control.d32 = peri->ctrl;
control.b.fsel = 2; /* PHY default is 24M (5), change to 12M (2) */
control.b.por = 1; /* power off default*/
peri->ctrl = control.d32;
udelay(time_dly);
return 0;
}
//SPL_STATIC_FUNC
void serial_putc_uart_a(const char c)
{
if (c == '\n')
{
while ((readl(CBUS_REG_ADDR(UART_PORT_0+UART_STATUS )) & UART_STAT_MASK_TFIFO_FULL));
writel('\r', CBUS_REG_ADDR(UART_PORT_0+UART_WFIFO));
}
/* Wait till dataTx register is not full */
while ((readl(CBUS_REG_ADDR(UART_PORT_0+UART_STATUS )) & UART_STAT_MASK_TFIFO_FULL));
writel(c, CBUS_REG_ADDR(UART_PORT_0+UART_WFIFO));
/* Wait till dataTx register is empty */
}
int run_arc(unsigned addr)
{
//char c;
/** copy ARM code*/
//change arm mapping
memcpy((void*)0x49008000,(void*)0x49000000,16*1024);
//remap arm memory
writel((0x49008000>>14)&0xf,P_AO_REMAP_REG0);
/** copy ARC code*/
//copy code to 49000000 and remap to zero
memcpy((void*)0x49008000,(void*)addr,16*1024);
writel(0x1<<4,P_AO_REMAP_REG1);
writel(0x7fffffff,P_AO_RTI_STATUS_REG0);
printf("start up ARC\n");
//switch to ARC jtag
// writel(0x51001,0xc8100030);
writel(1,P_AO_RTI_STATUS_REG1);
//reset arc
writel(RESET_ARC625,CBUS_REG_ADDR(RESET2_REGISTER));
__udelay(1000);
//enable arc
writel(1,CBUS_REG_ADDR(AUD_ARC_CTL));
writel(0,CBUS_REG_ADDR(AUD_ARC_CTL));
unsigned a,b;
unsigned timer_base;
a=b=0x7fffffff;
printf("ARM is Live\n");
timer_base=get_timer(0);
do{
a=readl(P_AO_RTI_STATUS_REG0);
if((a&0x80000000)|| ((a==b)&&(get_timer(timer_base)<10000000)))
{
continue;
}
timer_base=get_timer(0);
b=a;
printf("ARM is Live: %x",a);
switch(a&0xffff)
{
case 0:
printf("ARM Exit Sleep Mode\n");
break;
}
}while(a);
return 0;
}
//call after set clock
void set_usb_phy_power(amlogic_usb_config_t * usb_cfg,int is_on)
{
unsigned long delay = 1000;
int port_idx;
unsigned int port;
usb_peri_reg_t *peri_a,*peri_b,*peri;
usb_ctrl_data_t control;
if(!usb_cfg)
return;
port = usb_cfg->base_addr & USB_PHY_PORT_MSK;
peri_a = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_A);
peri_b = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_B);
if(port == USB_PHY_PORT_A){
peri = peri_a;
port_idx = 0;
}else{
peri = peri_b;
port_idx = 1;
}
if(is_on){
control.d32 = peri_a->ctrl;
control.b.por = 0;
peri_a->ctrl = control.d32;
control.d32 = peri_b->ctrl;
control.b.por = 0;
peri_b->ctrl = control.d32;
/* read back clock detected flag*/
control.d32 = peri->ctrl;
if(!control.b.clk_detected){
printf("USB (%d) PHY Clock not detected!\n",port_idx);
}
}else{
control.d32 = peri_a->ctrl;
control.b.por = 1;
peri_a->ctrl = control.d32;
control.d32 = peri_b->ctrl;
control.b.por = 1;
peri_b->ctrl = control.d32;
}
udelay(delay);
}
SPL_STATIC_FUNC void serial_init_uart_a(unsigned set)
{
/* baud rate */
writel(set
|UART_CNTL_MASK_RST_TX
|UART_CNTL_MASK_RST_RX
|UART_CNTL_MASK_CLR_ERR
|UART_CNTL_MASK_TX_EN
|UART_CNTL_MASK_RX_EN
,CBUS_REG_ADDR(UART_PORT_0+UART_CONTROL));
SET_CBUS_REG_MASK(0x2030, 0x3000);
CLEAR_CBUS_REG_MASK(0x202f,0x3000);
clrbits_le32(CBUS_REG_ADDR(UART_PORT_0+UART_CONTROL),
UART_CNTL_MASK_RST_TX | UART_CNTL_MASK_RST_RX | UART_CNTL_MASK_CLR_ERR);
}
int run_testpd(unsigned addr)
{
char cmd;
rbt_save_env();
/** copy ARM code*/
//change arm mapping
memcpy((void*)0x49008000,(void*)0x49000000,16*1024);
//remap arm memory
writel((0x49008000>>14)&0xf,P_AO_REMAP_REG0);
/** copy ARC code*/
//copy code to 49000000 and remap to zero
memcpy((void*)0x49008000,(void*)addr,16*1024);
writel(0x1<<4,P_AO_REMAP_REG1);
printf("start up ARC\n");
//switch to ARC jtag
// writel(0x51001,0xc8100030);
//reset arc
writel(RESET_ARC625,CBUS_REG_ADDR(RESET2_REGISTER));
__udelay(1000);
//enable arc
writel(1,CBUS_REG_ADDR(AUD_ARC_CTL));
writel(0,CBUS_REG_ADDR(AUD_ARC_CTL));
do{
printf("cmd >");
cmd = getc();
writel((unsigned)cmd,P_AO_RTI_STATUS_REG0);
__udelay(1000);
__udelay(1000);
if(cmd == 't'){
asm volatile ("wfi");
}
else{
while(readl(P_AO_RTI_STATUS_REG0) != 0)
{
__udelay(1000);
}
}
static int aml_fe_dvbt_init(struct dvb_frontend *fe)
{
struct amlfe_state *state = fe->demodulator_priv;
struct aml_demod_sys sys;
struct aml_demod_i2c i2c;
pr_dbg("AML Demod DVB-T init\r\n");
memset(&sys, 0, sizeof(sys));
memset(&i2c, 0, sizeof(i2c));
sys.clk_en = 1;
sys.clk_src = 0;
sys.clk_div = 0;
sys.pll_n = 1;
sys.pll_m = 50;
sys.pll_od = 0;
sys.pll_sys_xd = 20;
sys.pll_adc_xd = 21;
sys.agc_sel = 2;
sys.adc_en = 1;
sys.i2c = (long)&i2c;
sys.debug = 0;
i2c.tuner = state->config.tuner_type;
i2c.addr = state->config.tuner_addr;
#if 0
i2c.scl_oe = i2c.sda_oe = CBUS_REG_ADDR(PREG_EGPIO_EN_N)/*0xc1108030*/;
i2c.scl_out = i2c.sda_out = CBUS_REG_ADDR(PREG_EGPIO_O)/*0xc1108034*/;
i2c.scl_in = i2c.sda_in = CBUS_REG_ADDR(PREG_EGPIO_I)/*0xc1108038*/;
i2c.scl_bit = 15;
i2c.sda_bit = 16;
i2c.udelay = 1;
i2c.retries = 3;
i2c.debug = 0;
#endif
_prepare_i2c(fe, &i2c);
demod_set_sys(state->sta, state->i2c, &sys);
state->sys = sys;
return 0;
}
/*
* Read a single byte from the serial port.
*/
SPL_STATIC_FUNC
int serial_getc_uart_a(void)
{
unsigned char ch;
/* Wait till character is placed in fifo */
while((readl(CBUS_REG_ADDR(UART_PORT_0+UART_STATUS)) & UART_STAT_MASK_RFIFO_CNT)==0) ;
/* Also check for overflow errors */
if (readl(CBUS_REG_ADDR(UART_PORT_0+UART_STATUS)) & (UART_STAT_MASK_PRTY_ERR | UART_STAT_MASK_FRAM_ERR))
{
setbits_le32(CBUS_REG_ADDR(UART_PORT_0+UART_CONTROL),UART_CNTL_MASK_CLR_ERR);
clrbits_le32(CBUS_REG_ADDR(UART_PORT_0+UART_CONTROL),UART_CNTL_MASK_CLR_ERR);
}
ch = readl(CBUS_REG_ADDR(UART_PORT_0+UART_RFIFO)) & 0x00ff;
return ((int)ch);
}
static int set_mio_mux(unsigned mux_index, unsigned mux_mask)
{
unsigned mux_reg[] = {PERIPHS_PIN_MUX_0, PERIPHS_PIN_MUX_1, PERIPHS_PIN_MUX_2,PERIPHS_PIN_MUX_3,
PERIPHS_PIN_MUX_4,PERIPHS_PIN_MUX_5,PERIPHS_PIN_MUX_6,PERIPHS_PIN_MUX_7,PERIPHS_PIN_MUX_8,
PERIPHS_PIN_MUX_9,PERIPHS_PIN_MUX_10,PERIPHS_PIN_MUX_11,PERIPHS_PIN_MUX_12};
if (mux_index < 13) {
setbits_le32(CBUS_REG_ADDR(mux_reg[mux_index]), mux_mask);
return 0;
}
return -1;
}
static void read_reg(char *para)
{
char count=1;
vout_reg_t reg;
memcpy(®.addr,parse_para(para+1,&count),sizeof(unsigned int));
if (((*para) == 'm') || ((*para) == 'M'))
{
amlog_level(LOG_LEVEL_HIGH,"[0x%x] : 0x%x\r\n", CBUS_REG_ADDR(reg.addr), READ_MPEG_REG(reg.addr));
}else if (((*para) == 'p') || ((*para) == 'P')) {
if (APB_REG_ADDR_VALID(reg.addr))
amlog_level(LOG_LEVEL_HIGH,"[0x%x] : 0x%x\r\n", APB_REG_ADDR(reg.addr), READ_APB_REG(reg.addr));
}else if (((*para) == 'h') || ((*para) == 'H')) {
amlog_level(LOG_LEVEL_HIGH,"[0x%x] : 0x%x\r\n", AHB_REG_ADDR(reg.addr), READ_AHB_REG(reg.addr));
}
}
static void write_reg(char *para)
{
char count=2;
vout_reg_t reg;
memcpy(®, parse_para(para+1,&count), sizeof(vout_reg_t));
if (((*para) == 'm') || ((*para) == 'M')){
WRITE_MPEG_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", CBUS_REG_ADDR(reg.addr), reg.value, READ_MPEG_REG(reg.addr));
}
else if (((*para) == 'p') || ((*para) == 'P')) {
if (APB_REG_ADDR_VALID(reg.addr)){
WRITE_APB_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", APB_REG_ADDR(reg.addr), reg.value, READ_APB_REG(reg.addr));
}
}
else if (((*para) == 'h') || ((*para) == 'H')) {
WRITE_AHB_REG(reg.addr,reg.value);
amlog_level(LOG_LEVEL_HIGH,"[0x%x] = 0x%x 0x%x\r\n", AHB_REG_ADDR(reg.addr), reg.value, READ_AHB_REG(reg.addr));
}
}
void cec_power_on(void)
{
/*Enable GPIOD5*/
writel((readl(CBUS_REG_ADDR(PREG_PAD_GPIO2_O)) | (1<<21)), CBUS_REG_ADDR(PREG_PAD_GPIO2_O));
writel((readl(CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N)) & (~(1<<21))), CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N));
/*Enable cts_hdmi_sys_clk*/
writel(((readl(CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL)) & (~((0x7<<9) | 0x7f))) | (1<<8)), CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL));
/*Enable CEC function :pin mux*/
//writel((readl(P_PERIPHS_PIN_MUX_1) | (1<<25)), P_PERIPHS_PIN_MUX_1);
//enable all clk gate for test
//writel(0xffffffff, P_HHI_GCLK_MPEG0);
//writel(0xffffffff, P_HHI_GCLK_MPEG1);
//writel(0xffffffff, P_HHI_GCLK_MPEG2);
//writel(0xffffffff, P_HHI_GCLK_OTHER);
}
hdmi_wr_reg(0x8005, 1);
// LED
WRITE_CBUS_REG(PWM_PWM_C, (0xff00<<16) |(0xff00<<0));
}
else
{
printk("set gpio suspend.\n");
// LED
WRITE_CBUS_REG(PWM_PWM_C, (0xff00<<16) |(0<<0));
}
}
static struct meson_pm_config aml_pm_pdata = {
.pctl_reg_base = IO_APB_BUS_BASE,
.mmc_reg_base = APB_REG_ADDR(0x1000),
.hiu_reg_base = CBUS_REG_ADDR(0x1000),
.power_key = (1<<8),
.ddr_clk = 0x00110820,
.sleepcount = 128,
.set_vccx2 = set_vccx2,
.core_voltage_adjust = 7, //5,8
.set_exgpio_early_suspend = set_gpio_suspend_resume,
};
static struct platform_device aml_pm_device = {
.name = "pm-meson",
.dev = {
.platform_data = &aml_pm_pdata,
},
.id = -1,
};
static void usb_bc_detect(amlogic_usb_config_t * usb_cfg)
{
int port_idx,timeout_det;
unsigned int port = usb_cfg->base_addr & USB_PHY_PORT_MSK;
usb_peri_reg_t *peri_a,*peri_b,*peri_c,*peri_d,*peri;
usb_adp_bc_data_t adp_bc;
int bc_mode = BC_MODE_UNKNOWN;
peri_a = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_A);
peri_b = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_B);
// peri_c = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_C);
// peri_d = (usb_peri_reg_t*)CBUS_REG_ADDR(PREI_USB_PHY_REG_D);
if(port == USB_PHY_PORT_A){
peri = peri_a;
port_idx = 0;
}else if(port == USB_PHY_PORT_B){
peri = peri_b;
port_idx = 1;
}else if(port == USB_PHY_PORT_C){
peri = peri_c;
port_idx = 2;
}else if(port == USB_PHY_PORT_D){
peri = peri_d;
port_idx = 3;
}
adp_bc.d32 = peri->adp_bc;
if(adp_bc.b.device_sess_vld){
mdelay(T_DCD_TIMEOUT);
/* Turn on VDPSRC */
adp_bc.b.chrgsel = 0;
adp_bc.b.vdatdetenb = 1;
adp_bc.b.vdatsrcenb = 1;
adp_bc.b.dcd_enable = 0;
peri->adp_bc = adp_bc.d32;
/* SDP and CDP/DCP distinguish */
timeout_det = T_VDMSRC_EN;
while(timeout_det--){
adp_bc.d32 = peri->adp_bc;
if(adp_bc.b.chg_det)
break;
mdelay(1);
};
if(adp_bc.b.chg_det){
/* Turn off VDPSRC */
adp_bc.d32 = peri->adp_bc;
adp_bc.b.vdatdetenb = 0;
adp_bc.b.vdatsrcenb = 0;
peri->adp_bc = adp_bc.d32;
/* Wait VDMSRC_DIS */
timeout_det = T_VDMSRC_DIS;
while(timeout_det--){
adp_bc.d32 = peri->adp_bc;
if(!adp_bc.b.chg_det)
break;
mdelay(1);
};
if(timeout_det <= 0)
printf("Time out for VDMSRC_DIS!");
/* Turn on VDMSRC */
adp_bc.d32 = peri->adp_bc;
adp_bc.b.chrgsel = 1;
adp_bc.b.vdatdetenb = 1;
adp_bc.b.vdatsrcenb = 1;
peri->adp_bc = adp_bc.d32;
mdelay(T_VDMSRC_ON);
adp_bc.d32 = peri->adp_bc;
if(adp_bc.b.chg_det)
bc_mode = BC_MODE_DCP;
else
bc_mode = BC_MODE_CDP;
}
else{
bc_mode = BC_MODE_SDP;
}
adp_bc.d32 = peri->adp_bc;
adp_bc.b.vdatdetenb = 0;
adp_bc.b.vdatsrcenb = 0;
adp_bc.b.dcd_enable = 0;
peri->adp_bc = adp_bc.d32;
}
printf("detect usb battery charger mode: %s\n",bc_name[bc_mode]);
usb_cfg->battery_charging_det_cb(bc_mode);
}
void analog_switch(int flag)
{
int i;
unsigned reg_value = 0;
if (flag) {
printf("analog on\n");
SET_CBUS_REG_MASK(AM_ANALOG_TOP_REG0, 1 << 1); // set 0x206e bit[1] 1 to power on top analog
for (i = 0; i < ANALOG_COUNT; i++) {
if (analog_regs[i].enable && (analog_regs[i].set_bits || analog_regs[i].clear_bits)) {
if (analog_regs[i].enable == 1) {
WRITE_CBUS_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
} else if (analog_regs[i].enable == 2) {
WRITE_APB_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
} else if (analog_regs[i].enable == 3) {
WRITE_AHB_REG(analog_regs[i].reg_addr, analog_regs[i].reg_value);
}
}
}
} else {
printf("analog off\n");
for (i = 0; i < ANALOG_COUNT; i++) {
if (analog_regs[i].enable && (analog_regs[i].set_bits || analog_regs[i].clear_bits)) {
if (analog_regs[i].enable == 1) {
analog_regs[i].reg_value = READ_CBUS_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, CBUS_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_CBUS_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_CBUS_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_CBUS_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
} else if (analog_regs[i].enable == 2) {
analog_regs[i].reg_value = READ_APB_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, APB_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_APB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_APB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_APB_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
} else if (analog_regs[i].enable == 3) {
analog_regs[i].reg_value = READ_AHB_REG(analog_regs[i].reg_addr);
printf("%s(0x%x):0x%x", analog_regs[i].name, AHB_REG_ADDR(analog_regs[i].reg_addr), analog_regs[i].reg_value);
if (analog_regs[i].clear_bits) {
CLEAR_AHB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].clear_bits);
printf(" & ~0x%x", analog_regs[i].clear_bits);
}
if (analog_regs[i].set_bits) {
SET_AHB_REG_MASK(analog_regs[i].reg_addr, analog_regs[i].set_bits);
printf(" | 0x%x", analog_regs[i].set_bits);
}
reg_value = READ_AHB_REG(analog_regs[i].reg_addr);
printf(" = 0x%x\n", reg_value);
}
}
}
CLEAR_CBUS_REG_MASK(AM_ANALOG_TOP_REG0, 1 << 1); // set 0x206e bit[1] 0 to shutdown top analog
}
}
{
printk("set gpio resume.\n");
hdmi_wr_reg(0x8005, 2);
udelay(50);
hdmi_wr_reg(0x8005, 1);
}
else
{
printk("set gpio suspend.\n");
}
}
static struct meson_pm_config aml_pm_pdata = {
.pctl_reg_base = (void __iomem *)IO_APB_BUS_BASE,
.mmc_reg_base = (void __iomem *)APB_REG_ADDR(0x1000),
.hiu_reg_base = (void __iomem *)CBUS_REG_ADDR(0x1000),
.power_key = (1<<8),
.ddr_clk = 0x00110820,
.sleepcount = 128,
.set_vccx2 = set_vccx2,
.core_voltage_adjust = 7, //5,8
.set_exgpio_early_suspend = set_gpio_suspend_resume,
};
static struct platform_device aml_pm_device = {
.name = "pm-meson",
.dev = {
.platform_data = &aml_pm_pdata,
},
.id = -1,
};
//SPL_STATIC_FUNC
void serial_wait_tx_empty_uart_a(void)
{
while ((readl(CBUS_REG_ADDR(UART_PORT_0+UART_STATUS)) & UART_STAT_MASK_TFIFO_EMPTY)==0);
}
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise 0.
*/
SPL_STATIC_FUNC
int serial_tstc_uart_a(void)
{
return (readl(CBUS_REG_ADDR(UART_PORT_0+UART_STATUS)) & UART_STAT_MASK_RFIFO_CNT);
}
int main(void)
{
unsigned cmd;
char c;
p_arc_pwr_op = &arc_pwr_op;
timer_init();
arc_pwr_register((struct arc_pwr_op *)p_arc_pwr_op);//init arc_pwr_op
arc_param->serial_disable=0;
serial_put_hex(readl(P_AO_RTI_STATUS_REG1),32);
writel(0,P_AO_RTI_STATUS_REG1);
f_serial_puts("sleep .......\n");
arc_param->serial_disable=0;
while(1){
cmd = readl(P_AO_RTI_STATUS_REG0);
if(cmd == 0)
{
delay_ms(10);
continue;
}
c = (char)cmd;
if(c == 't')
{
init_I2C();
// copy_reboot_code();
#ifdef CONFIG_MESON_TRUSTZONE
copy_reboot_code_temp(temp_arm_base, sizeof(temp_arm_base));
#endif
enter_power_down();
//test_arc_core();
break;
}
else if(c == 'q')
{
f_serial_puts(" - quit command loop\n");
writel(0,P_AO_RTI_STATUS_REG0);
break;
}
else
{
f_serial_puts(" - cmd no support (ARC)\n");
}
//command executed
writel(0,P_AO_RTI_STATUS_REG0);
}
// asm("SLEEP");
while(1){
// udelay__(600);
cmd = readl(P_AO_RTI_STATUS_REG1);
c = (char)cmd;
// f_serial_puts("REG2=");
// serial_put_hex(readl(P_AO_RTI_STATUS_REG2),32);
if(c == 0)
{
udelay__(6000);
cmd = readl(P_AO_RTI_STATUS_REG1);
c = (char)cmd;
if((c == 0)||(c!='r'))
{
#ifdef _UART_DEBUG_COMMUNICATION_
serial_put_hex(cmd,32);
f_serial_puts(" arm boot fail\n\n");
wait_uart_empty();
#endif
#if 0 //power down
cmd = readl(P_AO_GPIO_O_EN_N);
cmd &= ~(1<<6);
cmd &= ~(1<<22);
writel(cmd,P_AO_GPIO_O_EN_N);
#endif
}
} else if ( cmd == 1 )
{
serial_put_hex(cmd,32);
f_serial_puts(" ARM has started running\n");
wait_uart_empty();
} else if ( cmd == 2 )
{
serial_put_hex(cmd,32);
f_serial_puts(" Reenable SEC\n");
wait_uart_empty();
}
else if(c=='r')
{
f_serial_puts("arm boot succ\n");
//set GPIODV_29 to 0
writel( (readl(CBUS_REG_ADDR(PREG_PAD_GPIO2_O)) & ~(1<<29) ), CBUS_REG_ADDR(PREG_PAD_GPIO2_O) );
wait_uart_empty();
asm(".long 0x003f236f"); //add sync instruction.
asm("flag 1");
asm("nop");
asm("nop");
asm("nop");
}
else
{
#ifdef _UART_DEBUG_COMMUNICATION_
serial_put_hex(cmd,32);
f_serial_puts(" arm unkonw state\n");
wait_uart_empty();
#endif
}
//cmd='f';
//writel(cmd,P_AO_RTI_STATUS_REG1);
}
return 0;
}
void cooling(void)
{
int i;
unsigned int tmp_data;
static struct meson_pm_config aml_pm_pdata = {
.pctl_reg_base = (void *)IO_APB_BUS_BASE,
.mmc_reg_base = (void *)APB_REG_ADDR(0x1000),
.hiu_reg_base = (void *)CBUS_REG_ADDR(0x1000),
.power_key = (1<<15),
.ddr_clk = 0x00120234, // 312m, 0x00110220, //384m
.sleepcount = 128,
//.set_vccx2 = set_vccx2, //Elvis Fool
.core_voltage_adjust = 5,
};
tvin_powerdown();
writel(0,P_WATCHDOG_TC);//disable Watchdog
//amp reset down GPIOX_51
clrbits_le32(P_PREG_FGPIO_O, 1<<19);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<19);
__udelay(1000);
//USB_PWR_CTL down x44
clrbits_le32(P_PREG_FGPIO_O, 1<<12);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<12);
//mute down x69
setbits_le32(P_PREG_GGPIO_O, 1<<5);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl BL_EN
setbits_le32(P_PREG_FGPIO_O, 1<<21);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21);
//pwm x55
clrbits_le32(P_PREG_FGPIO_O, 1<<23);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<23);
//pwm b2
setbits_le32(P_PREG_GGPIO_O, 1<<10);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<10);
//pwm b3
setbits_le32(P_PREG_GGPIO_O, 1<<11);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<11);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_48 LED_G
clrbits_le32(P_PREG_FGPIO_O, 1<<16);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<16);
//GPIOX_56 LED_R
setbits_le32(P_PREG_FGPIO_O, 1<<24);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<24);
//vcc_12v/24v power down GPIOX_70
//clrbits_le32(P_PREG_GGPIO_O, 1<<6);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
serial_hw_init();
//setbits_le32(P_PERIPHS_PIN_MUX_2,((1<<29)|(1<<30)));
writel(0x18003033, P_UART1_CONTROL);
serial_puts("\nstandby...\n");
writel(0x209861f1, P_HHI_GCLK_MPEG0);
writel(0x208b8028, P_HHI_GCLK_MPEG1);
writel(0xfffffc07, P_HHI_GCLK_MPEG2);
writel(0xffc40021, P_HHI_GCLK_OTHER);
//analog off
WRITE_CBUS_REG(SAR_ADC_REG3, 0x3008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb off
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x8040012b);
//clock off
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840e);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x202);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x203);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1083);
//pll off
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x8232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x8641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0xca80);
WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x887d);
#ifdef SYSTEM_16K
if (READ_CBUS_REG(HHI_MPEG_CLK_CNTL)&(1<<8))
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<9)); // xtal_rtc = rtc
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1, 0, 6); // devider = 2
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#else
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0x1e, 0, 6); // devider = 30
WRITE_CBUS_REG_BITS(HHI_MPEG_CLK_CNTL, 0, 12, 2); // clk81 src -> xtal_rtc
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, (1<<8)); // clk81 = xtal_rtc / devider
#endif
CLEAR_CBUS_REG_MASK(HHI_A9_CLK_CNTL, (1<<7)); // clka9 = xtal_rtc / 2
#ifdef SYSTEM_16K
SET_CBUS_REG_MASK(PREG_CTLREG0_ADDR, 1);
#endif
WRITE_CBUS_REG(HHI_A9_AUTO_CLK0,
(2 << 24) | // sleep select 1000uS timebase
(0x20 << 16) | // Set the delay wakeup time (32mS)
(0 << 5) | // don't clear the FIQ global mask
(0 << 4) | // don't clear the IRQ global mask
(2 << 2)); // Set interrupt wakeup only
WRITE_CBUS_REG(HHI_A9_AUTO_CLK1,
(0 << 20) | // start delay timebase
(1 << 12) | // 1uS enable delay
(1 << 8) | // 1uS gate delay
(1 << 0)); // 1us start delay
SET_CBUS_REG_MASK(HHI_A9_AUTO_CLK0, 1 << 0); //ENABLE: If this bit is set to 1, then the auto-clock ratio module will execute a change once the START pulses is generated.
SET_CBUS_REG_MASK(HHI_SYS_PLL_CNTL, (1<<15)); // turn off sys pll
/*
while(1)
{
if(serial_tstc()) break;
}*/
WRITE_CBUS_REG(0x2620, 0x10001);
WRITE_CBUS_REG(0x2621, 0x24);
WRITE_CBUS_REG(0x2622, 0);
WRITE_CBUS_REG(0x2623, 0);
WRITE_CBUS_REG(0x2624, 0);
enable_custom_trigger();
#ifdef CONFIG_MACH_MESON2_7366M_CST02
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 1); //enable gpio interrupt
#endif
#ifdef CONFIG_MACH_MESON2_7366M_REFE03
WRITE_CBUS_REG(A9_0_IRQ_IN2_INTR_MASK, 1); //enable gpio interrupt
#endif
tmp_data = READ_CBUS_REG(PREG_CTLREG0_ADDR);
WRITE_CBUS_REG(PREG_CTLREG0_ADDR, tmp_data | 0x1);
tmp_data = READ_CBUS_REG(IR_DEC_REG0);
WRITE_CBUS_REG(IR_DEC_REG0, tmp_data & 0xFFFFFF00);
tmp_data = READ_CBUS_REG(IR_DEC_REG1);
WRITE_CBUS_REG(IR_DEC_REG1, tmp_data | 0x00000001);
WRITE_CBUS_REG(IR_DEC_REG1, tmp_data & 0xFFFFFFFE);
//hub reset down x50
clrbits_le32(P_PREG_FGPIO_O, 1<<18);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<18);
//GPIOX_32 si2176_RESET down
clrbits_le32(P_PREG_FGPIO_O, 1<<0);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<0);
//PHY_RESET x57
clrbits_le32(P_PREG_FGPIO_O, 1<<25);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<25);
//close ddr
//gpiob_8
setbits_le32(P_PREG_GGPIO_O, 1<<16);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16);
//gpiob_5
setbits_le32(P_PREG_GGPIO_O, 1<<13);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13);
//gpiob_6
//setbits_le32(P_PREG_GGPIO_O, 1<<14);
//clrbits_le32(P_PREG_GGPIO_EN_N, 1<<14);
for(i=0; i<100; i++)
{
__udelay(1000);
}
meson_cpu_suspend(aml_pm_pdata);
for(i=0; i<100; i++)
{
__udelay(1000);
}
//GPIOX_54 reset chip panel power
clrbits_le32(P_PREG_FGPIO_O, 1<<22);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<22);
//pwm x55
setbits_le32(P_PREG_FGPIO_O, 1<<23);
clrbits_le32(P_PREG_FGPIO_EN_N, 1<<23);
//pwm b2
clrbits_le32(P_PREG_GGPIO_O, 1<<10);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<10);
//pwm b3
clrbits_le32(P_PREG_GGPIO_O, 1<<11);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<11);
for(i=0; i<300; i++)
{
__udelay(1000);
}
//vcc_12v/24v power on
setbits_le32(P_PREG_GGPIO_O, 1<<6);
clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
//setbits_le32(P_PREG_GGPIO_EN_N, 1<<6);
for(i=0; i<800; i++)
{
__udelay(1000);
}
//GPIOX_53 reset chip power ctrl
//setbits_le32(P_PREG_FGPIO_O, 1<<21);
memory_pll_init(0,NULL);
serial_puts("\ngate clock on...\n");
writel(0xffffffff, P_HHI_GCLK_MPEG0);
writel(0xffffffff, P_HHI_GCLK_MPEG1);
writel(0xffffffff, P_HHI_GCLK_MPEG2);
writel(0xffffffff, P_HHI_GCLK_OTHER);
#if 0
//analog on
WRITE_CBUS_REG(SAR_ADC_REG3, 0x2008510a);
//WRITE_CBUS_REG(VGHL_PWM_REG0, 0x0); //the same with off
//WRITE_CBUS_REG(WIFI_ADC_SAMPLING, 0x0); //the same with off
//WRITE_APB_REG(ADC_EN_ADC, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_ADC_DAC, 0x0); //the same with off
//WRITE_AHB_REG(ADC_EN_CMLGEN_RES, 0x0); //the same with off
//WRITE_AHB_REG(WIFI_SARADC, 0x0); //the same with off
//usb on
WRITE_CBUS_REG(PREI_USB_PHY_REG, 0x80400128);
//clock on
//WRITE_CBUS_REG(HHI_DEMOD_CLK_CNTL, 0x400); //the same with off
//WRITE_CBUS_REG(HHI_SATA_CLK_CNTL, 0x0); //the same with off
//WRITE_CBUS_REG(HHI_ETH_CLK_CNTL, 0x207); //the same with off
//WRITE_CBUS_REG(HHI_WIFI_CLK_CNTL, 0x0); //the same with off
WRITE_CBUS_REG(HHI_VID_CLK_CNTL, 0x840f);
WRITE_CBUS_REG(HHI_AUD_CLK_CNTL, 0x800018);
WRITE_CBUS_REG(HHI_MALI_CLK_CNTL, 0x302);
WRITE_CBUS_REG(HHI_HDMI_CLK_CNTL, 0x303);
WRITE_CBUS_REG(HHI_MPEG_CLK_CNTL, 0x1183);
//pll on
WRITE_CBUS_REG(HHI_DEMOD_PLL_CNTL, 0x232);
WRITE_CBUS_REG(HHI_VID_PLL_CNTL, 0x641);
WRITE_CBUS_REG(HHI_AUD_PLL_CNTL, 0x4a80);
//WRITE_CBUS_REG(HHI_OTHER_PLL_CNTL, 0x87d);
#endif
return 0;
}
void enter_power_down()
{
//set GPIODV_29 to 1
writel( (readl(CBUS_REG_ADDR(PREG_PAD_GPIO2_O)) | (1<<29) ), CBUS_REG_ADDR(PREG_PAD_GPIO2_O) );
unsigned int uboot_cmd_flag=readl(P_AO_RTI_STATUS_REG2);//u-boot suspend cmd flag
unsigned int vcin_state = 0;
//int voltage = 0;
//int axp_ocv = 0;
int wdt_flag;
// First, we disable all memory accesses.
f_serial_puts("step 1\n");
asm(".long 0x003f236f"); //add sync instruction.
store_restore_plls(0);
f_serial_puts("ddr self-refresh\n");
wait_uart_empty();
ddr_self_refresh();
f_serial_puts("CPU off...\n");
wait_uart_empty();
cpu_off();
f_serial_puts("CPU off done\n");
wait_uart_empty();
#ifdef CONFIG_CEC_WAKEUP
hdmi_cec_func_config = readl(P_AO_DEBUG_REG0);
f_serial_puts("CEC M8:uboot: P_AO_DEBUG_REG0:\n");
serial_put_hex(hdmi_cec_func_config,32);
f_serial_puts("\n");
#endif
if(p_arc_pwr_op->power_off_at_24M)
p_arc_pwr_op->power_off_at_24M();
#ifdef CONFIG_M201_COSTDOWN
/* for led */
clrbits_le32(P_AO_GPIO_O_EN_N,1<<18);
setbits_le32(P_AO_GPIO_O_EN_N,1<<29);
#endif
// while(readl(0xc8100000) != 0x13151719)
// {}
//non 32k crystal oscillator platform DONT enter 32k in suspend mode
#ifndef CONFIG_NON_32K
switch_24M_to_32K();
#endif
if(p_arc_pwr_op->power_off_at_32K_1)
p_arc_pwr_op->power_off_at_32K_1();
if(p_arc_pwr_op->power_off_at_32K_2)
p_arc_pwr_op->power_off_at_32K_2();
// gate off: bit0: REMOTE; bit3: UART
#ifndef CONFIG_NON_32K
writel(readl(P_AO_RTI_GEN_CNTL_REG0)&(~(0x8)),P_AO_RTI_GEN_CNTL_REG0);
#endif
if(uboot_cmd_flag == 0x87654321)//u-boot suspend cmd flag
{
if(p_arc_pwr_op->power_off_ddr15)
p_arc_pwr_op->power_off_ddr15();
}
wdt_flag=readl(P_WATCHDOG_TC)&(1<<19);
if(wdt_flag)
writel(readl(P_WATCHDOG_TC)&(~(1<<19)),P_WATCHDOG_TC);
#if 1
vcin_state = p_arc_pwr_op->detect_key(uboot_cmd_flag);
#else
for(i=0;i<10;i++)
{
udelay__(1000);
//udelay(1000);
}
#endif
if(uboot_cmd_flag == 0x87654321)//u-boot suspend cmd flag
{
if(p_arc_pwr_op->power_on_ddr15)
p_arc_pwr_op->power_on_ddr15();
}
if(wdt_flag)
writel((6*7812|((1<<16)-1))|(1<<19),P_WATCHDOG_TC);
// gate on: bit0: REMOTE; bit3: UART
writel(readl(P_AO_RTI_GEN_CNTL_REG0)|0x8,P_AO_RTI_GEN_CNTL_REG0);
if(p_arc_pwr_op->power_on_at_32K_2)
p_arc_pwr_op->power_on_at_32K_2();
if(p_arc_pwr_op->power_on_at_32K_1)
p_arc_pwr_op->power_on_at_32K_1();
#ifndef CONFIG_NON_32K
switch_32K_to_24M();
#endif
// power on even more domains
if(p_arc_pwr_op->power_on_at_24M)
p_arc_pwr_op->power_on_at_24M();
uart_reset();
f_serial_puts("step 8: ddr resume\n");
wait_uart_empty();
ddr_resume();
#ifdef CONFIG_M201_COSTDOWN
/* for led */
clrbits_le32(P_AO_GPIO_O_EN_N,1<<29);
setbits_le32(P_AO_GPIO_O_EN_N,1<<18);
#endif
f_serial_puts("restore pll\n");
wait_uart_empty();
store_restore_plls(1);//Before switch back to clk81, we need set PLL
if (uboot_cmd_flag == 0x87654321 && (vcin_state == FLAG_WAKEUP_PWROFF)) {
/*
* power off system before ARM is restarted
*/
f_serial_puts("no extern power shutdown\n");
wait_uart_empty();
p_arc_pwr_op->shut_down();
do {
udelay__(2000 * 100);
f_serial_puts("wait shutdown...\n");
wait_uart_empty();
}while(1);
}
#ifdef CONFIG_MESON_TRUSTZONE
copy_reboot_code(temp_arm_base);
#else
copy_reboot_code(NULL);
#endif
writel(vcin_state,P_AO_RTI_STATUS_REG2);
f_serial_puts("restart arm\n");
wait_uart_empty();
restart_arm();
if (uboot_cmd_flag == 0x87654321) {
writel(0,P_AO_RTI_STATUS_REG2);
writel(readl(P_AO_RTI_PWR_CNTL_REG0)|(1<<4),P_AO_RTI_PWR_CNTL_REG0);
clrbits_le32(P_HHI_SYS_CPU_CLK_CNTL,1<<19);
//writel(10,0xc1109904);
writel(1<<19|1<<24|10,0xc1109900);
do{udelay__(200);f_serial_puts("wait reset...\n");wait_uart_empty();}while(1);
}
}
