char nrf_snd_pkt_crc_encr(int size, uint8_t * pkt, uint32_t const key[4]){
if(size > MAX_PKT)
size=MAX_PKT;
nrf_write_reg(R_CONFIG,
R_CONFIG_PWR_UP| // Power on
R_CONFIG_EN_CRC // CRC on, single byte
);
// nrf_write_long(C_W_TX_PAYLOAD,size,pkt);
uint16_t crc=crc16(pkt,size-2);
pkt[size-2]=(crc >>8) & 0xff;
pkt[size-1]=crc & 0xff;
if(key !=NULL)
xxtea_encode_words((uint32_t*)pkt,size/4,key);
CS_LOW();
xmit_spi(C_W_TX_PAYLOAD);
sspSend(0,pkt,size);
CS_HIGH();
CE_HIGH();
delayms(1); // Send it. (only needs >10ys, i think)
CE_LOW();
return nrf_cmd_status(C_NOP);
};
/* Send function.
* Write to send_buf[1] - send_buf[31] before calling this function.
* command will be placed in send_buf[0].*/
void send(command_t command)
{
uint8_t i;
// Set operation mode to transmit.
CE_LOW();
hal_nrf_set_operation_mode(HAL_NRF_PTX);
// Copy command to send buffer.
send_buf[0] = command;
hal_nrf_write_tx_payload(send_buf, PAYLOAD_SIZE);
// Activate sender
CE_PULSE();
send_success = false;
// Wait for radio to transmit
while (RFF != 1) ;
RFF = 0;
nrf_irq();
// Clear send buffer.
for (i = 0; i < PAYLOAD_SIZE; i++) {
send_buf[i] = 0x00;
}
// Reset operation mode to receive.
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
}
/** Initialized the RF configurations and powre up the RF.
* Use this function to initialize RF configurations.
* Note that the pipe isn't opened in this function,
* please use "rf_rcv_pipe_config" after using this
* function to configure RX pipe.
*
* @param in_channel RF Frequency (in_channel + 2400MHz)
* @param in_datarate Data rate of the RF transmission. (1Mbps or 2Mbps)
* @param in_output_power RF output power configuration.
* @param in_auto_retr Enable auto retransmission or not.
* @param in_auto_retr_delay Auto retransmission delay.
* @param in_addr_width Address width configuration for both PTX and PRX pipe.
* @param in_crc_mode CRC enable or disable configuration.
* @param in_spi_clk_rate SPI clock rate. (SPI speed)
* @param in_rf_int RF interrupt enable bit.
*/
void epl_rf_en_init(unsigned char in_channel, epl_rf_en_datarate_t in_datarate, char in_output_power, unsigned char in_auto_retr, unsigned int in_auto_retr_delay, char in_addr_width, epl_rf_en_crc_mode_t in_crc_mode, unsigned char in_rf_int)
{
RFCKEN = 1; // RF clock enable.
CE_LOW();
//--- Default static setup. These setting is optimized to match the RF protocol with nRF24E1. ---//
hal_nrf_close_pipe(HAL_NRF_ALL); // Close all pipes first. By default, pipe0 and pipe1 are opened.
hal_nrf_set_datarate(in_datarate);
hal_nrf_set_auto_retr(in_auto_retr, in_auto_retr_delay); // First parameter is set to zero indicating the auto retransmission is off.
hal_nrf_set_output_power(in_output_power); // Maximum radio output power (0dbm).
hal_nrf_set_crc_mode(in_crc_mode);
hal_nrf_set_address_width(in_addr_width); // Both RX and TX's address width are Configured.
hal_nrf_set_operation_mode(HAL_NRF_PTX); // Enter RF TX mode
hal_nrf_set_rf_channel(in_channel);
hal_nrf_set_power_mode(HAL_NRF_PWR_UP); // Power up radio
hal_nrf_get_clear_irq_flags();
// IEN1 RF interrupt enable bit
RF = in_rf_int;
}
void hal_nrf_init(void)
{
hal_nrf_sta=HAL_NRF_STA_RX;
hal_nrf_tx_sta = HAL_NRF_TX_STA_IDLE;
hal_nrf_tx_rd_index=0, hal_nrf_tx_cnt=0, hal_nrf_tx_wr_index=0;
hal_nrf_tx_busy = 0;
hal_nrf_rx_sta = HAL_NRF_RX_STA_IDLE;
hal_nrf_rx_rd_index=0, hal_nrf_rx_cnt=0, hal_nrf_rx_wr_index=0;
CSN_OUTPUT();
CE_OUTPUT();
CSN_HIGH();
CE_LOW();
IRQ_INPUT() ;
IRQ_EN();
t2_init();
spi_init();
hal_nrf_tick_num = sys_tick_apply();
sys_tick_set(hal_nrf_tick_num, ON);
hal_nrf_cnt = 0;
}
void nrf_init() {
// Enable SPI correctly
sspInit(0, sspClockPolarity_Low, sspClockPhase_RisingEdge);
// Enable CS & CE pins
gpioSetDir(RB_SPI_NRF_CS, gpioDirection_Output);
gpioSetPullup(&RB_SPI_NRF_CS_IO, gpioPullupMode_Inactive);
gpioSetDir(RB_NRF_CE, gpioDirection_Output);
gpioSetPullup(&RB_NRF_CE_IO, gpioPullupMode_PullUp);
CE_LOW();
// Setup for nrf24l01+
// power up takes 1.5ms - 3.5ms (depending on crystal)
CS_LOW();
nrf_write_reg(R_CONFIG,
R_CONFIG_PRIM_RX| // Receive mode
R_CONFIG_PWR_UP| // Power on
R_CONFIG_EN_CRC // CRC on, single byte
);
nrf_write_reg(R_EN_AA, 0); // Disable Enhanced ShockBurst;
// Set speed / strength
nrf_write_reg(R_RF_SETUP,DEFAULT_SPEED|R_RF_SETUP_RF_PWR_3);
// Clear MAX_RT, just in case.
nrf_write_reg(R_STATUS,R_STATUS_MAX_RT);
};
// Sends requested bytes of data to host.
void readHexRecord()
{
uint8_t i, bytes;
uint16_t addr;
CE_LOW();
// Get memory address and number of bytes to read.
bytes = MSG_RE_BYTE_COUNT;
addr = MSG_RE_ADDR;
// Copy flash memory bytes to temporary idata buffer.
PCON |= PMW;
hal_flash_bytes_read(addr, temp_data, bytes);
PCON &= ~PMW;
// If request is for reset vector, read from non-volatile mem.
if (addr == 0x0000) {
hal_flash_bytes_read(FW_RESET_OPCODE, temp_data, 3);
}
// Copy to send buffer
for (i = 0; i < bytes; i++) {
send_buf[i+1] = temp_data[i];
}
send(CMD_ACK);
return;
}
void nrf_init()
{
//ce
LPC_GPIO2->FIODIR |= (1<<2);
//cs_rad
LPC_GPIO2->FIODIR |= (1<<6);
CE_LOW();
delay_ms(11);
// Setup for nrf24l01+
// power up takes 1.5ms - 3.5ms (depending on crystal)
CS_LOW();
nrf_write_reg(R_CONFIG,
R_CONFIG_PRIM_RX| // Receive mode
R_CONFIG_PWR_UP| // Power on
R_CONFIG_EN_CRC // CRC on, single byte
);
nrf_write_reg(R_EN_AA, 0); // Disable Enhanced ShockBurst;
// Set speed / strength
nrf_write_reg(R_RF_SETUP,DEFAULT_SPEED|R_RF_SETUP_RF_PWR_3);
// Clear MAX_RT, just in case.
nrf_write_reg(R_STATUS,R_STATUS_MAX_RT);
// CS_HIGH();
};
// Writes hex-record's data field to flash memory.
// Will update bytes_received and send reply to host.
void writeHexRecord(state_t *state, uint16_t *bytes_received)
{
uint8_t i, checksum = 0, bytes = MSG_WR_BYTE_COUNT;
uint16_t addr = MSG_WR_ADDR;
// Disable RF receiving while writing.
CE_LOW();
// Calculate checksum for message.
for (i = 0; i < bytes+HEX_BYTES; i++) {
checksum += MSG_PAYLOAD(i);
}
if (checksum != 0) {
// Checksum fail
send_buf[1] = ERROR_CHECKSUM_FAIL;
send(CMD_NACK);
return;
}
// Copy data portion of payload to idata temp memory.
for (i = 0; i < bytes; i++) {
temp_data[i] = MSG_WR_DATA(i);
}
// This will prevent the reset vector from being overwritten.
if (addr == 0x0000) {
PCON |= PMW;
// Offset write with the 3 bytes of the reset vector
hal_flash_bytes_write((addr+3), (temp_data+3), (bytes-3));
PCON &= ~PMW;
// Make sure that bytes to be written is within legal pages.
} else if (addr+bytes < FLASH_FW_MAX_SIZE) {
// Write line to flash.
PCON |= PMW;
hal_flash_bytes_write(addr, temp_data, bytes);
PCON &= ~PMW;
// Address is outside pages available to new firmware.
} else {
// Invalid address
send_buf[1] = ERROR_ILLEGAL_ADDRESS;
send(CMD_NACK);
return;
}
// Add bytes to total received.
*bytes_received += bytes;
// Acknowledge message
send(CMD_ACK);
if (!send_success) {
*state = ERROR;
}
return;
}
void mcu_init()
{
RF = 1; // Radio IRQ enable
CE_LOW();
RFCTL = 0x10; // RF SPI Enable
T2CON = 0x10; // Reload mode 0, osc / 12
T2I0 = 1; // Start Timer2
}
T2_ISR()
{
T2_STOP();
TF2 = 0;
if(t2_sta==1){
CE_HIGH();
t2_sta = 2;
T2 = (65536-16*TIME/12);
T2_START();
}else if(t2_sta == 2){
CE_LOW();
T2_STOP();
}
}
__interrupt void t2_irq(void)
{
if(t2_sta == 1){
t2_sta = 2;
CE_HIGH();
TCCR2B = 0;
TCNT2 = 0;
OCR2A = 240;
TCCR2B = 0x01;
}else if(t2_sta == 2){
T2_STOP();
TCNT2 = 0;
CE_LOW();
}
}
void hal_nrf_set_sta(hal_nrf_sta_t sta)
{
u8 len, i;
if(hal_nrf_tx_cnt){
hal_nrf_tx_cmd_flag = 0;
HAL_NRF_WAIT_ACK_DONE();
IRQ_DIS();
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
hal_nrf_sta = HAL_NRF_STA_TX;
hal_nrf_tx_busy = 1;
len = hal_nrf_tx_buf[hal_nrf_tx_rd_index];
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
hal_nrf_tx_cnt = hal_nrf_tx_cnt-len-1;
// hal_nrf_write_tx_payload(hal_nrf_tx_buf_tmp, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(W_TX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(hal_nrf_tx_buf[hal_nrf_tx_rd_index]);
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
HAL_NRF_HW_SPI_READ();
}
CSN_HIGH();
hal_nrf_set_operation_mode(HAL_NRF_PTX);
// CE_HIGH();
// T2_START();
t2_start_delay();
IRQ_EN();
}else{
read_flash_buf(slave_cmd, slave_cmd_end, CMD_LENGTH);
hal_nrf_send_cmd(slave_cmd, HAL_NRF_STA_RX);
hal_nrf_tx_cmd_flag = 2;
}
}
void hal_nrf_send_cmd(u8 *buf, u8 sta)
{
/** auto ack delay */
HAL_NRF_WAIT_ACK_DONE();
IRQ_DIS();
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
hal_nrf_sta = HAL_NRF_STA_TX_CMD;
// hal_nrf_sta_next = sta;
hal_nrf_write_tx_payload(buf, CMD_LENGTH);
// hal_nrf_write_tx_payload_noack(buf, CMD_LENGTH);
hal_nrf_set_operation_mode(HAL_NRF_PTX);
// CE_HIGH();
// T2_START();
t2_start_delay();
IRQ_EN();
}
char snd_pkt_no_crc(int size, uint8_t * pkt)
{
if(size > MAX_PKT)
size=MAX_PKT;
nrf_write_reg(R_CONFIG,
R_CONFIG_PWR_UP| // Power on
R_CONFIG_EN_CRC // CRC on, single byte
);
CS_LOW();
xmit_spi(C_W_TX_PAYLOAD);
sspSend(0,pkt,size);
CS_HIGH();
CE_HIGH();
delayms(1); // Send it. (only needs >10ys, i think)
CE_LOW();
return nrf_cmd_status(C_NOP);
}
// Resets RF parameters to default values.
// Must be called before jumping to new firmware.
void resetRF()
{
// Reset values set by the RF setup.
CE_LOW();
// PWR_UP = 0
hal_nrf_set_power_mode(HAL_NRF_PWR_DOWN);
// PRIM_RX = 0
hal_nrf_set_operation_mode(HAL_NRF_PTX);
// RF_CH = 0x02;
hal_nrf_set_rf_channel(reset_channel);
// AW = 11 (Default = 5 bytes)
// RX_ADDR_P0 = TX_ADDR = 0xE7E7E7E7E7
hal_nrf_set_address(HAL_NRF_TX, reset_pipe_address);
hal_nrf_set_address(HAL_NRF_PIPE0, reset_pipe_address);
// ARD = 0000, ARC = 0011
hal_nrf_set_auto_retr(3, 250);
// RX_PW_P0 = 0x00
hal_nrf_set_rx_payload_width((int)HAL_NRF_PIPE0, 0);
// Disable radio clock
RFCKEN = 0;
return;
}
app_states_t app_susp_we(void)
{
// wdp_host_rx_setup(WDP_RX_SUSPEND); // Set up WDP low power receive mode
usb_wakeup();
return APP_NORMAL;
CE_LOW();
hal_nrf_set_power_mode(HAL_NRF_PWR_DOWN); // Power up radio
RFCKEN = 0; // disable the radio clock
// usb_wakeup();
// return APP_NORMAL;
// Minimize the powerconsumption by powering down the MCU
cklf_gpio_wakeup(0x0000, 0x0000); // GPIO wakeup off
cklf_rtc_disable();
cklf_rtc_init(0x00, 0x1FFF); // Setup power down timeout to app. 1 s
cpu_pwr_down(); // MCU goto sleep
WUF = 0; // Clear WU flag
return APP_SUSP_WE;
}
void CE_PULSE(){
CE_HIGH();
i_delay = 300;
while(i_delay--);
CE_LOW();
}
__interrupt void HAL_NRF_ISR(void)
{
u8 status, len, i;
if(!IRQ) {
/** */
// Read and clear IRQ flags from radio
status = hal_nrf_nop();
// if(hal_nrf_ack_flag){
// if((status&0x60) == 0x60){
// hal_nrf_ack_flag = 0;
// }else{
// read_flash_buf(slave_cmd, slave_cmd_request, CMD_LENGTH);
// hal_nrf_write_ack_payload(0, slave_cmd, CMD_LENGTH);
// }
// }
#ifdef SLAVE_DEBUG
hal_nrf_irq_flag = status;
#endif
if(status & (1<< (uint8_t)HAL_NRF_RX_DR)){
do{
len = hal_nrf_read_rx_payload_width();
if(len > 32){
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
hal_nrf_rx_sta = HAL_NRF_RX_STA_COM_ERROR;
return;
}
if((hal_nrf_rx_cnt + len + 1) < HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_buf[hal_nrf_rx_wr_index] = len;
hal_nrf_rx_wr_index++;
if(hal_nrf_rx_wr_index == HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_wr_index=0;
}
// hal_nrf_read_payload((u8*)hal_nrf_rx_buf[hal_nrf_rx_wr_index].buf, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(R_RX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(0U);
while(HAL_NRF_HW_SPI_BUSY){}
hal_nrf_rx_buf[hal_nrf_rx_wr_index] = HAL_NRF_HW_SPI_READ();
hal_nrf_rx_wr_index++;
if(hal_nrf_rx_wr_index == HAL_NRF_RX_BUF_LEN){
hal_nrf_rx_wr_index=0;
}
}
CSN_HIGH();
hal_nrf_rx_cnt = hal_nrf_rx_cnt+len+1;
}else{
hal_nrf_flush_rx();
hal_nrf_rx_sta = HAL_NRF_RX_STA_BUF_OVF;
/** clear RX_DR */
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
break;
}
/** clear RX_DR */
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_RX_DR));
}while(!hal_nrf_rx_fifo_empty());
}
if(status & (1 << (uint8_t)HAL_NRF_TX_DS)){
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_TX_DS));
switch(hal_nrf_sta){
case HAL_NRF_STA_TX:
hal_nrf_tx_cmd_flag = 0;
if(hal_nrf_tx_cnt){
hal_nrf_tx_busy = 1;
len = hal_nrf_tx_buf[hal_nrf_tx_rd_index];
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
hal_nrf_tx_cnt = hal_nrf_tx_cnt-len-1;
// hal_nrf_write_tx_payload(hal_nrf_tx_buf_tmp, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(W_TX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(hal_nrf_tx_buf[hal_nrf_tx_rd_index]);
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
HAL_NRF_HW_SPI_READ();
}
CSN_HIGH();
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
if(hal_nrf_tx_sta == HAL_NRF_TX_STA_IDLE){
/** send end pkt */
hal_nrf_tx_sta = HAL_NRF_TX_STA_DONE;
read_flash_buf(slave_cmd, slave_cmd_end, CMD_LENGTH);
hal_nrf_write_tx_payload(slave_cmd, CMD_LENGTH);
hal_nrf_tx_cmd_flag = 2;
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
hal_nrf_tx_sta = HAL_NRF_TX_STA_IDLE;
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
}
}
break;
case HAL_NRF_STA_RX:
/** ack payload send */
break;
case HAL_NRF_STA_TX_CMD:
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
hal_nrf_tx_cmd_flag = 0;
break;
}
}
if(status & (1 << (uint8_t)HAL_NRF_MAX_RT)){
#if 0
// When a MAX_RT interrupt occurs the TX payload will not be removed from the TX FIFO.
// If the packet is to be discarded this must be done manually by flushing the TX FIFO.
// Alternatively, CE_PULSE() can be called re-starting transmission of the payload.
// (Will only be possible after the radio irq flags are cleared)
hal_nrf_flush_tx();
hal_nrf_flush_rx();
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_sta=HAL_NRF_STA_RX;
/** discard all data in buffer */
hal_nrf_tx_busy = 0;
hal_nrf_tx_cnt = 0;
hal_nrf_tx_rd_index =0;
hal_nrf_tx_wr_index = 0;
// hal_nrf_flush_rx();
// hal_nrf_rx_cnt = 0;
// hal_nrf_rx_rd_index =0;
// hal_nrf_rx_wr_index = 0;
/** set timeout flag */
hal_nrf_timeout = 1;
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_MAX_RT));
#else
hal_nrf_write_reg (STATUS, (1<< (uint8_t)HAL_NRF_MAX_RT));
switch(hal_nrf_sta){
case HAL_NRF_STA_TX:
hal_nrf_tx_cmd_flag = 0;
if(hal_nrf_tx_cnt){
hal_nrf_tx_busy = 1;
len = hal_nrf_tx_buf[hal_nrf_tx_rd_index];
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
hal_nrf_tx_cnt = hal_nrf_tx_cnt-len-1;
// hal_nrf_write_tx_payload(hal_nrf_tx_buf_tmp, len);
CSN_LOW();
HAL_NRF_HW_SPI_WRITE(W_TX_PAYLOAD);
while(HAL_NRF_HW_SPI_BUSY) {}
HAL_NRF_HW_SPI_READ();
for(i=0; i<len; i++){
HAL_NRF_HW_SPI_WRITE(hal_nrf_tx_buf[hal_nrf_tx_rd_index]);
hal_nrf_tx_rd_index++;
if(hal_nrf_tx_rd_index == HAL_NRF_TX_BUF_LEN){
hal_nrf_tx_rd_index = 0;
}
while(HAL_NRF_HW_SPI_BUSY) {} /* wait for byte transfer finished */
HAL_NRF_HW_SPI_READ();
}
CSN_HIGH();
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
if(hal_nrf_tx_sta == HAL_NRF_TX_STA_IDLE){
/** send end pkt */
hal_nrf_tx_sta = HAL_NRF_TX_STA_DONE;
read_flash_buf(slave_cmd, slave_cmd_end, CMD_LENGTH);
hal_nrf_write_tx_payload(slave_cmd, CMD_LENGTH);
hal_nrf_tx_cmd_flag = 2;
// CE_HIGH();
// T2_START();
t2_start_delay();
}else{
hal_nrf_tx_sta = HAL_NRF_TX_STA_IDLE;
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
}
}
break;
case HAL_NRF_STA_RX:
/** ack payload send */
break;
case HAL_NRF_STA_TX_CMD:
hal_nrf_sta = HAL_NRF_STA_RX;
CE_LOW();
hal_nrf_flush_tx();
hal_nrf_flush_rx();
/** return to RX mode */
hal_nrf_set_operation_mode(HAL_NRF_PRX);
CE_HIGH();
hal_nrf_tx_busy = 0;
hal_nrf_tx_cmd_flag = 0;
break;
}
#endif
}
}
}
void main(void)
{
data app_states_t app_state = APP_INIT;
CLKCTL = 0; // Reset clock control register
P0DIR = (1<<3)|(1<<1)|(1<<0);
// P0DIR = 0x18; // Output: P0.0 - P0.2, Input: P0.3 - P0.5
// P0ALT = 0; // All general I/O
// P0 = 0;
/*
P0ALT = 0x0F;
P0EXP = 0x02; // Slave SPI for P0
SSCONF = 0x01; //Enable slave SPI
*/
CE_LOW(); // Radio chip enable low
RFCTL = 0x10; // Internal MCU to radio SPI enable
RFCKEN = 1; // Radio clk enable
RF = 1; // Radio IRQ enable
// Enable global interrupt
/** USB-init **/
usbpair |= 0x01;
hal_usb_init(true, device_req_cb, reset_cb, resume_cb, suspend_cb);
hal_usb_endpoint_config(0x82, 32, ep_1_in_cb);
hal_usb_endpoint_config(0x02, 32, ep_1_out_cb);
ep1_sent = true;
ep2_sent = true;
usb_state = USB_AWAKE;
EA = 1;
usb_wait_for_configuration(); // Wait until USB enumerated
byteCnt = PKTLENGTH;
payload[1][PKTLENGTH-1] = 0xAA;
payload[0][PKTLENGTH-1] = 0xAA;
for(;;)
{
switch(app_state)
{
case APP_INIT:
app_state = app_init();
break;
case APP_NORMAL: // Normal state
app_state = app_normal();
break;
case APP_SUSP_WE: // PC suspend state, remote wakeup enabled
case APP_SUSP_WD: // PC suspend state, remote wakeup disabled
// P0_4=1;
app_state = app_susp_we();
// P0_4=0;
break;
default:
break;
}
}
return;
}
void nrf_rcv_pkt_end(void)
{
CE_LOW();
nrf_cmd(C_FLUSH_RX);
nrf_write_reg(R_STATUS,R_STATUS_RX_DR);
};
/* Ma-ma-ma-main function! */
void main()
{
state_t state = LISTENING;
command_t cmd = CMD_NO_CMD;
firmware_start firmware;
uint16_t channel_timer = 0, bootloader_timer = 0, connection_timer = 0;
uint8_t ch_i = 0, firmware_number = 0;
bool running;
uint16_t bytes_received = 0;
uint16_t bytes_total = 0;
uint8_t ea_default, rf_default;
// Disable RF interrupt
rf_default = RF;
RF = 0;
// Disable global interrupt
ea_default = EA;
EA = 0;
// Set up parameters for RF communication.
configureRF();
#ifdef DEBUG_LED_
P0DIR = 0;
P0 = 0x55;
#endif
running = true;
// Boot loader loop.
// Will terminate after a couple of seconds if firmware has been successfully
// installed.
while (running) {
// Polls the RF-interrupt bit every iteration.
if (RFF) {
RFF = 0;
nrf_irq();
if (packet_received) {
packet_received = false;
connection_timer = 0;
cmd = MSG_CMD;
switch (cmd) {
// Host initiates contact with the device.
case CMD_INIT:
// Send ACK to host, go to CONNECTED state if successful.
sendInitAck(&state);
// Reset timers
channel_timer = bootloader_timer = 0;
break;
// Host starts a firmware update.
case CMD_UPDATE_START:
if (state == CONNECTED) {
// Initiate firmware updates, go to RECEIVING_FIRMWARE state
// if successful.
startFirmwareUpdate(&state, &bytes_total, &bytes_received,
&firmware_number);
}
#ifdef DEBUG_LED_
P0 = state;
#endif
break;
// Write message containing one hex record.
case CMD_WRITE:
if (state == RECEIVING_FIRMWARE) {
writeHexRecord(&state, &bytes_received);
}
#ifdef DEBUG_LED_
P0 = 0x40;
#endif
break;
// Firmware update has been completed.
case CMD_UPDATE_COMPLETE:
CE_LOW();
// Check that every byte is received.
if (bytes_received == bytes_total) {
// Mark firmware as successfully installed.
hal_flash_byte_write(FW_INSTALLED, 0x01);
hal_flash_byte_write(FW_NUMBER, firmware_number);
state = CONNECTED;
send(CMD_ACK);
} else {
send(CMD_NACK);
}
if (!send_success) {
state = ERROR;
}
#ifdef DEBUG_LED_
P0 = 0x10;
#endif
break;
// Host request data from flash at specified address.
case CMD_READ:
readHexRecord();
#ifdef DEBUG_LED_
P0 = 0x20;
#endif
break;
// Host sends ping to check connections with device.
case CMD_PING:
if (state != LISTENING) {
send(CMD_PONG);
}
#ifdef DEBUG_LED_
P0 = 0x80;
#endif
break;
// Host sends disconnect
case CMD_EXIT:
state = LISTENING;
break;
// These commands should no be received.
case CMD_NO_CMD:
default:
state = ERROR;
break;
}
// Clear command
cmd = CMD_NO_CMD;
}
// RF interrupt bit not set
} else if (state == LISTENING) {
// Will listen to one channel for 'a while' before changing.
channel_timer++;
if (channel_timer > CHANNEL_TIMEOUT) {
channel_timer = 0;
// Go to next channel
ch_i = (ch_i+1)%3;
hal_nrf_set_rf_channel(default_channels[ch_i]);
#ifdef DEBUG_LED_
P0 = ch_i;
#endif
// After changing channels and being in the LISTENING state
// for 'a while', boot loader loop will check if there is firmware
// installed, and if so end the while(running) loop.
bootloader_timer++;
if (bootloader_timer > BOOTLOADER_TIMEOUT) {
bootloader_timer = 0;
running = (hal_flash_byte_read(FW_INSTALLED) == 0x01) ? false : true;
}
}
// While connected must receive something or connection times out.
// Connection timer reset when packet received.
} else if (state == CONNECTED) {
connection_timer++;
if (connection_timer > CONNECTION_TIMEOUT) {
state = LISTENING;
}
}
}
resetRF();
#ifdef DEBUG_LED_
// Default value for P0DIR
P0 = 0x00;
P0DIR = 0xFF;
#endif
EA = ea_default;
RF = rf_default;
// Reads address of firmware's reset vector.
temp_data[0] = hal_flash_byte_read(FW_RESET_ADDR_H);
temp_data[1] = hal_flash_byte_read(FW_RESET_ADDR_L);
firmware = (firmware_start)(((uint16_t)temp_data[0]<<8) | (temp_data[1]));
// Jump to firmware. Goodbye!
firmware();
}
// High-Level:
int nrf_rcv_pkt_time_encr(int maxtime, int maxsize, uint8_t * pkt, uint32_t const key[4]){
uint8_t len;
uint8_t status=0;
uint16_t cmpcrc;
nrf_write_reg(R_CONFIG,
R_CONFIG_PRIM_RX| // Receive mode
R_CONFIG_PWR_UP| // Power on
R_CONFIG_EN_CRC // CRC on, single byte
);
nrf_cmd(C_FLUSH_RX);
nrf_write_reg(R_STATUS,0);
CE_HIGH();
for(int i=0;i<maxsize;i++) pkt[i] = 0x00; // Sanity: clear packet buffer
#define LOOPY 10
for (;maxtime >= LOOPY;maxtime-=LOOPY){
delayms(LOOPY);
status =nrf_cmd_status(C_NOP);
if( (status & R_STATUS_RX_DR) == R_STATUS_RX_DR){
if( (status & R_STATUS_RX_P_NO) == R_STATUS_RX_FIFO_EMPTY){
nrf_cmd(C_FLUSH_RX);
delayms(1);
nrf_write_reg(R_STATUS,0);
continue;
}else{ // Get/Check packet...
nrf_read_long(C_R_RX_PL_WID,1,&len);
if(len>32 || len==0){
continue;
return -2; // no packet error
};
if(len>maxsize){
continue;
return -1; // packet too large
};
nrf_read_pkt(len,pkt);
if(key != NULL)
xxtea_decode_words((uint32_t*)pkt,len/4,key);
cmpcrc=crc16(pkt,len-2);
if(cmpcrc != (pkt[len-2] <<8 | pkt[len-1])) {
continue;
return -3; // CRC failed
};
break;
};
};
};
CE_LOW();
CS_HIGH();
if(maxtime<LOOPY)
return 0; // timeout
return len;
};
