void ResetOverlayRegisters(volatile STG4000REG __iomem *pSTGReg)
{
u32 tmp;
tmp = STG_READ_REG(DACOverlayAddr);
CLEAR_BITS_FRM_TO(0, 20);
CLEAR_BIT(31);
STG_WRITE_REG(DACOverlayAddr, tmp);
tmp = STG_READ_REG(DACOverlayUAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACOverlayUAddr, tmp);
tmp = STG_READ_REG(DACOverlayVAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACOverlayVAddr, tmp);
tmp = STG_READ_REG(DACOverlaySize);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(12, 31);
STG_WRITE_REG(DACOverlaySize, tmp);
tmp = STG4000_NO_DECIMATION;
STG_WRITE_REG(DACOverlayVtDec, tmp);
tmp = STG_READ_REG(DACPixelFormat);
CLEAR_BITS_FRM_TO(4, 7);
CLEAR_BITS_FRM_TO(16, 22);
STG_WRITE_REG(DACPixelFormat, tmp);
tmp = STG_READ_REG(DACVerticalScal);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 22);
tmp |= STG4000_NO_SCALING;
STG_WRITE_REG(DACVerticalScal, tmp);
tmp = STG_READ_REG(DACHorizontalScal);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 17);
tmp |= STG4000_NO_SCALING;
STG_WRITE_REG(DACHorizontalScal, tmp);
tmp = STG_READ_REG(DACBlendCtrl);
CLEAR_BITS_FRM_TO(0, 30);
tmp = (GRAPHICS_MODE << 28);
STG_WRITE_REG(DACBlendCtrl, tmp);
}
void SetupVTG(volatile STG4000REG __iomem *pSTGReg,
const struct kyrofb_info * pTiming)
{
u32 tmp = 0;
u32 margins = 0;
u32 ulBorder;
u32 xRes = pTiming->XRES;
u32 yRes = pTiming->YRES;
/* Horizontal */
u32 HAddrTime, HRightBorder, HLeftBorder;
u32 HBackPorcStrt, HFrontPorchStrt, HTotal,
HLeftBorderStrt, HRightBorderStrt, HDisplayStrt;
/* Vertical */
u32 VDisplayStrt, VBottomBorder, VTopBorder;
u32 VBackPorchStrt, VTotal, VTopBorderStrt,
VFrontPorchStrt, VBottomBorderStrt, VAddrTime;
/* Need to calculate the right border */
if ((xRes == 640) && (yRes == 480)) {
if ((pTiming->VFREQ == 60) || (pTiming->VFREQ == 72)) {
margins = 8;
}
}
/* Work out the Border */
ulBorder =
(pTiming->HTot -
(pTiming->HST + (pTiming->HBP - margins) + xRes +
(pTiming->HFP - margins))) >> 1;
/* Border the same for Vertical and Horizontal */
VBottomBorder = HLeftBorder = VTopBorder = HRightBorder = ulBorder;
/************ Get Timing values for Horizontal ******************/
HAddrTime = xRes;
HBackPorcStrt = pTiming->HST;
HTotal = pTiming->HTot;
HDisplayStrt =
pTiming->HST + (pTiming->HBP - margins) + HLeftBorder;
HLeftBorderStrt = HDisplayStrt - HLeftBorder;
HFrontPorchStrt =
pTiming->HST + (pTiming->HBP - margins) + HLeftBorder +
HAddrTime + HRightBorder;
HRightBorderStrt = HFrontPorchStrt - HRightBorder;
/************ Get Timing values for Vertical ******************/
VAddrTime = yRes;
VBackPorchStrt = pTiming->VST;
VTotal = pTiming->VTot;
VDisplayStrt =
pTiming->VST + (pTiming->VBP - margins) + VTopBorder;
VTopBorderStrt = VDisplayStrt - VTopBorder;
VFrontPorchStrt =
pTiming->VST + (pTiming->VBP - margins) + VTopBorder +
VAddrTime + VBottomBorder;
VBottomBorderStrt = VFrontPorchStrt - VBottomBorder;
/* Set Hor Timing 1, 2, 3 */
tmp = STG_READ_REG(DACHorTim1);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (HTotal) | (HBackPorcStrt << 16);
STG_WRITE_REG(DACHorTim1, tmp);
tmp = STG_READ_REG(DACHorTim2);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (HDisplayStrt << 16) | HLeftBorderStrt;
STG_WRITE_REG(DACHorTim2, tmp);
tmp = STG_READ_REG(DACHorTim3);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (HFrontPorchStrt << 16) | HRightBorderStrt;
STG_WRITE_REG(DACHorTim3, tmp);
/* Set Ver Timing 1, 2, 3 */
tmp = STG_READ_REG(DACVerTim1);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (VBackPorchStrt << 16) | (VTotal);
STG_WRITE_REG(DACVerTim1, tmp);
tmp = STG_READ_REG(DACVerTim2);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (VDisplayStrt << 16) | VTopBorderStrt;
STG_WRITE_REG(DACVerTim2, tmp);
tmp = STG_READ_REG(DACVerTim3);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 27);
tmp |= (VFrontPorchStrt << 16) | VBottomBorderStrt;
STG_WRITE_REG(DACVerTim3, tmp);
/* Set Verical and Horizontal Polarity */
tmp = STG_READ_REG(DACSyncCtrl) | SET_BIT(3) | SET_BIT(1);
if ((pTiming->HSP > 0) && (pTiming->VSP < 0)) { /* +hsync -vsync */
tmp &= ~0x8;
} else if ((pTiming->HSP < 0) && (pTiming->VSP > 0)) { /* -hsync +vsync */
tmp &= ~0x2;
} else if ((pTiming->HSP < 0) && (pTiming->VSP < 0)) { /* -hsync -vsync */
tmp &= ~0xA;
} else if ((pTiming->HSP > 0) && (pTiming->VSP > 0)) { /* +hsync -vsync */
tmp &= ~0x0;
}
STG_WRITE_REG(DACSyncCtrl, tmp);
}
int CreateOverlaySurface(volatile STG4000REG __iomem *pSTGReg,
u32 inWidth,
u32 inHeight,
int bLinear,
u32 ulOverlayOffset,
u32 * retStride, u32 * retUVStride)
{
u32 tmp;
u32 ulStride;
if (inWidth > STG4000_OVRL_MAX_WIDTH ||
inHeight > STG4000_OVRL_MAX_HEIGHT) {
return -EINVAL;
}
if (bLinear) {
if ((inWidth & 0x7) == 0) {
ulStride = (inWidth / 8);
} else {
ulStride = ((inWidth + 8) / 8);
}
} else {
if ((inWidth & 0xf) == 0) {
ulStride = (inWidth / 16);
} else {
ulStride = ((inWidth + 16) / 16);
}
}
tmp = STG_READ_REG(DACOverlayAddr);
CLEAR_BITS_FRM_TO(0, 20);
if (bLinear) {
CLEAR_BIT(31);
} else {
tmp |= SET_BIT(31);
}
tmp |= (ulOverlayOffset >> 4);
STG_WRITE_REG(DACOverlayAddr, tmp);
if (!bLinear) {
u32 uvSize =
(inWidth & 0x1) ? (inWidth + 1 / 2) : (inWidth / 2);
u32 uvStride;
u32 ulOffset;
if ((uvSize & 0xf) == 0) {
uvStride = (uvSize / 16);
} else {
uvStride = ((uvSize + 16) / 16);
}
ulOffset = ulOverlayOffset + (inHeight * (ulStride * 16));
if ((ulOffset & 0x1f) != 0)
ulOffset = (ulOffset + 32L) & 0xffffffE0L;
tmp = STG_READ_REG(DACOverlayUAddr);
CLEAR_BITS_FRM_TO(0, 20);
tmp |= (ulOffset >> 4);
STG_WRITE_REG(DACOverlayUAddr, tmp);
ulOffset += (inHeight / 2) * (uvStride * 16);
if ((ulOffset & 0x1f) != 0)
ulOffset = (ulOffset + 32L) & 0xffffffE0L;
tmp = STG_READ_REG(DACOverlayVAddr);
CLEAR_BITS_FRM_TO(0, 20);
tmp |= (ulOffset >> 4);
STG_WRITE_REG(DACOverlayVAddr, tmp);
*retUVStride = uvStride * 16;
}
void ResetOverlayRegisters(volatile STG4000REG * pSTGReg)
{
u32 tmp;
/* Set Overlay address to default */
tmp = STG_READ_REG(DACOverlayAddr);
CLEAR_BITS_FRM_TO(0, 20);
CLEAR_BIT(31);
STG_WRITE_REG(DACOverlayAddr, tmp);
/* Set Overlay U address */
tmp = STG_READ_REG(DACOverlayUAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACOverlayUAddr, tmp);
/* Set Overlay V address */
tmp = STG_READ_REG(DACOverlayVAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACOverlayVAddr, tmp);
/* Set Overlay Size */
tmp = STG_READ_REG(DACOverlaySize);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(12, 31);
STG_WRITE_REG(DACOverlaySize, tmp);
/* Set Overlay Vt Decimation */
tmp = STG4000_NO_DECIMATION;
STG_WRITE_REG(DACOverlayVtDec, tmp);
/* Set Overlay format to default value */
tmp = STG_READ_REG(DACPixelFormat);
CLEAR_BITS_FRM_TO(4, 7);
CLEAR_BITS_FRM_TO(16, 22);
STG_WRITE_REG(DACPixelFormat, tmp);
/* Set Vertical scaling to default */
tmp = STG_READ_REG(DACVerticalScal);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 22);
tmp |= STG4000_NO_SCALING; /* Set to no scaling */
STG_WRITE_REG(DACVerticalScal, tmp);
/* Set Horizontal Scaling to default */
tmp = STG_READ_REG(DACHorizontalScal);
CLEAR_BITS_FRM_TO(0, 11);
CLEAR_BITS_FRM_TO(16, 17);
tmp |= STG4000_NO_SCALING; /* Set to no scaling */
STG_WRITE_REG(DACHorizontalScal, tmp);
/* Set Blend mode to Alpha Blend */
/* ????? SG 08/11/2001 Surely this isn't the alpha blend mode,
hopefully its overwrite
*/
tmp = STG_READ_REG(DACBlendCtrl);
CLEAR_BITS_FRM_TO(0, 30);
tmp = (GRAPHICS_MODE << 28);
STG_WRITE_REG(DACBlendCtrl, tmp);
}
int CreateOverlaySurface(volatile STG4000REG * pSTGReg,
u32 inWidth,
u32 inHeight,
int bLinear,
u32 ulOverlayOffset,
u32 * retStride, u32 * retUVStride)
{
u32 tmp;
u32 ulStride;
if (inWidth > STG4000_OVRL_MAX_WIDTH ||
inHeight > STG4000_OVRL_MAX_HEIGHT) {
return -EINVAL;
}
/* Stride in 16 byte words - 16Bpp */
if (bLinear) {
/* Format is 16bits so num 16 byte words is width/8 */
if ((inWidth & 0x7) == 0) { /* inWidth % 8 */
ulStride = (inWidth / 8);
} else {
/* Round up to next 16byte boundary */
ulStride = ((inWidth + 8) / 8);
}
} else {
/* Y component is 8bits so num 16 byte words is width/16 */
if ((inWidth & 0xf) == 0) { /* inWidth % 16 */
ulStride = (inWidth / 16);
} else {
/* Round up to next 16byte boundary */
ulStride = ((inWidth + 16) / 16);
}
}
/* Set Overlay address and Format mode */
tmp = STG_READ_REG(DACOverlayAddr);
CLEAR_BITS_FRM_TO(0, 20);
if (bLinear) {
CLEAR_BIT(31); /* Overlay format to Linear */
} else {
tmp |= SET_BIT(31); /* Overlay format to Planer */
}
/* Only bits 24:4 of the Overlay address */
tmp |= (ulOverlayOffset >> 4);
STG_WRITE_REG(DACOverlayAddr, tmp);
if (!bLinear) {
u32 uvSize =
(inWidth & 0x1) ? (inWidth + 1 / 2) : (inWidth / 2);
u32 uvStride;
u32 ulOffset;
/* Y component is 8bits so num 32 byte words is width/32 */
if ((uvSize & 0xf) == 0) { /* inWidth % 16 */
uvStride = (uvSize / 16);
} else {
/* Round up to next 32byte boundary */
uvStride = ((uvSize + 16) / 16);
}
ulOffset = ulOverlayOffset + (inHeight * (ulStride * 16));
/* Align U,V data to 32byte boundary */
if ((ulOffset & 0x1f) != 0)
ulOffset = (ulOffset + 32L) & 0xffffffE0L;
tmp = STG_READ_REG(DACOverlayUAddr);
CLEAR_BITS_FRM_TO(0, 20);
tmp |= (ulOffset >> 4);
STG_WRITE_REG(DACOverlayUAddr, tmp);
ulOffset += (inHeight / 2) * (uvStride * 16);
/* Align U,V data to 32byte boundary */
if ((ulOffset & 0x1f) != 0)
ulOffset = (ulOffset + 32L) & 0xffffffE0L;
tmp = STG_READ_REG(DACOverlayVAddr);
CLEAR_BITS_FRM_TO(0, 20);
tmp |= (ulOffset >> 4);
STG_WRITE_REG(DACOverlayVAddr, tmp);
*retUVStride = uvStride * 16;
}
int InitialiseRamdac(volatile STG4000REG __iomem * pSTGReg,
u32 displayDepth,
u32 displayWidth,
u32 displayHeight,
s32 HSyncPolarity,
s32 VSyncPolarity, u32 * pixelClock)
{
u32 tmp = 0;
u32 F = 0, R = 0, P = 0;
u32 stride = 0;
u32 ulPdiv = 0;
u32 physicalPixelDepth = 0;
tmp = STG_READ_REG(SoftwareReset);
if (tmp & 0x1) {
CLEAR_BIT(1);
STG_WRITE_REG(SoftwareReset, tmp);
}
tmp = STG_READ_REG(DACPixelFormat);
CLEAR_BITS_FRM_TO(0, 2);
CLEAR_BITS_FRM_TO(8, 9);
switch (displayDepth) {
case 16:
{
physicalPixelDepth = 16;
tmp |= _16BPP;
break;
}
case 32:
{
physicalPixelDepth = 32;
tmp |= _32BPP;
break;
}
default:
return -EINVAL;
}
STG_WRITE_REG(DACPixelFormat, tmp);
ulPdiv = STG_PIXEL_BUS_WIDTH / physicalPixelDepth;
stride = displayWidth;
tmp = STG_READ_REG(DACPrimSize);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(12, 31);
tmp |=
((((displayHeight - 1) << 12) | (((displayWidth / ulPdiv) -
1) << 23))
| (stride / ulPdiv));
STG_WRITE_REG(DACPrimSize, tmp);
*pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P);
tmp = STG_READ_REG(DACPLLMode);
CLEAR_BITS_FRM_TO(0, 15);
tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
STG_WRITE_REG(DACPLLMode, tmp);
tmp = STG_READ_REG(DACPrimAddress);
CLEAR_BITS_FRM_TO(0, 20);
CLEAR_BITS_FRM_TO(20, 31);
STG_WRITE_REG(DACPrimAddress, tmp);
tmp = STG_READ_REG(DACCursorCtrl);
tmp &= ~SET_BIT(31);
STG_WRITE_REG(DACCursorCtrl, tmp);
tmp = STG_READ_REG(DACCursorAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACCursorAddr, tmp);
tmp = STG_READ_REG(DACVidWinStart);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(16, 26);
STG_WRITE_REG(DACVidWinStart, tmp);
tmp = STG_READ_REG(DACVidWinEnd);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(16, 26);
STG_WRITE_REG(DACVidWinEnd, tmp);
tmp = STG_READ_REG(DACBorderColor);
CLEAR_BITS_FRM_TO(0, 23);
STG_WRITE_REG(DACBorderColor, tmp);
STG_WRITE_REG(DACBurstCtrl, 0x0404);
tmp = STG_READ_REG(DACCrcTrigger);
CLEAR_BIT(0);
STG_WRITE_REG(DACCrcTrigger, tmp);
tmp = STG_READ_REG(DigVidPortCtrl);
CLEAR_BIT(8);
CLEAR_BITS_FRM_TO(16, 27);
CLEAR_BITS_FRM_TO(1, 3);
CLEAR_BITS_FRM_TO(10, 11);
STG_WRITE_REG(DigVidPortCtrl, tmp);
return 0;
}
int InitialiseRamdac(volatile STG4000REG __iomem * pSTGReg,
u32 displayDepth,
u32 displayWidth,
u32 displayHeight,
s32 HSyncPolarity,
s32 VSyncPolarity, u32 * pixelClock)
{
u32 tmp = 0;
u32 F = 0, R = 0, P = 0;
u32 stride = 0;
u32 ulPdiv = 0;
u32 physicalPixelDepth = 0;
/* Make sure DAC is in Reset */
tmp = STG_READ_REG(SoftwareReset);
if (tmp & 0x1) {
CLEAR_BIT(1);
STG_WRITE_REG(SoftwareReset, tmp);
}
/* Set Pixel Format */
tmp = STG_READ_REG(DACPixelFormat);
CLEAR_BITS_FRM_TO(0, 2);
/* Set LUT not used from 16bpp to 32 bpp ??? */
CLEAR_BITS_FRM_TO(8, 9);
switch (displayDepth) {
case 16:
{
physicalPixelDepth = 16;
tmp |= _16BPP;
break;
}
case 32:
{
/* Set for 32 bits per pixel */
physicalPixelDepth = 32;
tmp |= _32BPP;
break;
}
default:
return -EINVAL;
}
STG_WRITE_REG(DACPixelFormat, tmp);
/* Workout Bus transfer bandwidth according to pixel format */
ulPdiv = STG_PIXEL_BUS_WIDTH / physicalPixelDepth;
/* Get Screen Stride in pixels */
stride = displayWidth;
/* Set Primary size info */
tmp = STG_READ_REG(DACPrimSize);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(12, 31);
tmp |=
((((displayHeight - 1) << 12) | (((displayWidth / ulPdiv) -
1) << 23))
| (stride / ulPdiv));
STG_WRITE_REG(DACPrimSize, tmp);
/* Set Pixel Clock */
*pixelClock = ProgramClock(REF_CLOCK, *pixelClock, &F, &R, &P);
/* Set DAC PLL Mode */
tmp = STG_READ_REG(DACPLLMode);
CLEAR_BITS_FRM_TO(0, 15);
/* tmp |= ((P-1) | ((F-2) << 2) | ((R-2) << 11)); */
tmp |= ((P) | ((F - 2) << 2) | ((R - 2) << 11));
STG_WRITE_REG(DACPLLMode, tmp);
/* Set Prim Address */
tmp = STG_READ_REG(DACPrimAddress);
CLEAR_BITS_FRM_TO(0, 20);
CLEAR_BITS_FRM_TO(20, 31);
STG_WRITE_REG(DACPrimAddress, tmp);
/* Set Cursor details with HW Cursor disabled */
tmp = STG_READ_REG(DACCursorCtrl);
tmp &= ~SET_BIT(31);
STG_WRITE_REG(DACCursorCtrl, tmp);
tmp = STG_READ_REG(DACCursorAddr);
CLEAR_BITS_FRM_TO(0, 20);
STG_WRITE_REG(DACCursorAddr, tmp);
/* Set Video Window */
tmp = STG_READ_REG(DACVidWinStart);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(16, 26);
STG_WRITE_REG(DACVidWinStart, tmp);
tmp = STG_READ_REG(DACVidWinEnd);
CLEAR_BITS_FRM_TO(0, 10);
CLEAR_BITS_FRM_TO(16, 26);
STG_WRITE_REG(DACVidWinEnd, tmp);
/* Set DAC Border Color to default */
tmp = STG_READ_REG(DACBorderColor);
CLEAR_BITS_FRM_TO(0, 23);
STG_WRITE_REG(DACBorderColor, tmp);
/* Set Graphics and Overlay Burst Control */
STG_WRITE_REG(DACBurstCtrl, 0x0404);
/* Set CRC Trigger to default */
tmp = STG_READ_REG(DACCrcTrigger);
CLEAR_BIT(0);
STG_WRITE_REG(DACCrcTrigger, tmp);
/* Set Video Port Control to default */
tmp = STG_READ_REG(DigVidPortCtrl);
CLEAR_BIT(8);
CLEAR_BITS_FRM_TO(16, 27);
CLEAR_BITS_FRM_TO(1, 3);
CLEAR_BITS_FRM_TO(10, 11);
STG_WRITE_REG(DigVidPortCtrl, tmp);
return 0;
}
