void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for IRC22M clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external 12MHz XTAL, internal 22.1184MHz */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC22M_EN_Msk);
/* Enable PLL and Set PLL frequency */
CLK_SetCoreClock(PLLCON_SETTING);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Enable PWM module clock */
CLK_EnableModuleClock(PWM01_MODULE);
CLK_EnableModuleClock(PWM23_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
/* Select PWM module clock source */
CLK_SetModuleClock(PWM01_MODULE, CLK_CLKSEL1_PWM01_S_HXT, 0);
CLK_SetModuleClock(PWM23_MODULE, CLK_CLKSEL1_PWM23_S_HXT, 0);
/* Reset PWMA channel0~channel3 */
SYS_ResetModule(PWM03_RST);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP = SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0;
/* Set P2 multi-function pins for PWMA Channel0~3 */
SYS->P2_MFP = SYS_MFP_P20_PWM0 | SYS_MFP_P21_PWM1 | SYS_MFP_P22_PWM2 | SYS_MFP_P23_PWM3;
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
/* Waiting for Internal RC clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk));
/* Switch HCLK clock source to Internal RC and and HCLK source divide 1 */
CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;
CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
CLK->CLKDIV |= CLK_CLKDIV_HCLK(1);
/* Enable external XTAL 12MHz clock */
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
/* Waiting for external XTAL clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk));
/* Set core clock as PLL_CLOCK from PLL */
CLK->PLLCON = PLLCON_SETTING;
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));
CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_PLL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/* Enable UART module clock */
CLK->APBCLK |= (CLK_APBCLK_UART0_EN_Msk | CLK_APBCLK_UART1_EN_Msk);
/* Select UART module clock source */
CLK->CLKSEL1 &= ~CLK_CLKSEL1_UART_S_Msk;
CLK->CLKSEL1 |= CLK_CLKSEL1_UART_S_HXT;
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk);
SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0);
/* Set P1 multi-function pins for UART1 RXD and TXD */
SYS->P1_MFP &= ~(SYS_MFP_P12_Msk | SYS_MFP_P13_Msk);
SYS->P1_MFP |= (SYS_MFP_P12_RXD1 | SYS_MFP_P13_TXD1);
/* Set P0 multi-function pins for UART1 RTS */
SYS->P0_MFP = SYS->P0_MFP & (~SYS_MFP_P01_Msk) | SYS_MFP_P01_RTS1;
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external XTAL 12MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
/* Enable Timer 0~3 module clock */
CLK_EnableModuleClock(TMR0_MODULE);
CLK_EnableModuleClock(TMR2_MODULE);
CLK_EnableModuleClock(TMR3_MODULE);
/* Select Timer 0~3 module clock source */
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, NULL);
CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2_S_HCLK, NULL);
CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3_S_HXT, NULL);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB multi-function pins for UART0 RXD, TXD */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);
/* Set PB multi-function pins for TM0, TM2, TM3 and TM2_EXT */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB8_Msk | SYS_GPB_MFP_PB10_Msk |
SYS_GPB_MFP_PB11_Msk | SYS_GPB_MFP_PB2_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB8_TM0 | SYS_GPB_MFP_PB10_TM2 |
SYS_GPB_MFP_PB11_TM3 | SYS_GPB_MFP_PB2_TM2_EXT);
SYS->ALT_MFP &= ~( SYS_ALT_MFP_PB8_Msk | SYS_ALT_MFP_PB10_Msk | SYS_ALT_MFP_PB11_Msk |
SYS_ALT_MFP_PB2_Msk);
SYS->ALT_MFP |= (SYS_ALT_MFP_PB8_TM0 | SYS_ALT_MFP_PB10_TM2 |SYS_ALT_MFP_PB11_TM3 |
SYS_ALT_MFP_PB2_TM2_EXT);
SYS->ALT_MFP2 &= ~SYS_ALT_MFP2_PB2_TM2_Msk;
SYS->ALT_MFP2 |= SYS_ALT_MFP2_PB2_TM2_EXT;
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
/* Waiting for Internal RC clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk));
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_HIRC;
CLK->CLKDIV = (CLK->CLKDIV & (~CLK_CLKDIV_HCLK_N_Msk)) | CLK_CLKDIV_HCLK(1);
/* Set PLL to Power-down mode */
CLK->PLLCON |= CLK_PLLCON_PD_Msk;
/* Enable external XTAL 12MHz clock */
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
/* Waiting for external XTAL clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk));
/* Set core clock as PLL_CLOCK from PLL */
CLK->PLLCON = PLLCON_SETTING;
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLK_S_Msk)) | CLK_CLKSEL0_HCLK_S_PLL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For CLK_SysTickDelay()
/* Enable UART module clock */
CLK->APBCLK |= (CLK_APBCLK_UART0_EN_Msk | CLK_APBCLK_UART1_EN_Msk);
/* Select UART module clock source */
CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_UART_S_Msk)) | CLK_CLKSEL1_UART_S_HXT;
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
/* Set GPB multi-function pins for UART1 RXD and TXD */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk |
SYS_GPB_MFP_PB4_Msk | SYS_GPB_MFP_PB5_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD |
SYS_GPB_MFP_PB4_UART1_RXD | SYS_GPB_MFP_PB5_UART1_TXD);
}
/*--------------------------------------------------------------------------*/
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184 MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
#if (!CRYSTAL_LESS)
/* Enable external XTAL 12 MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
/* Waiting for external XTAL clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
/* Set core clock */
CLK_SetCoreClock(72000000);
/* Select module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_CLKDIV_UART(1));
CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USB_S_PLL, CLK_CLKDIV_USB(3));
#else
/* Enable Internal RC 48MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC48M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC48M_STB_Msk);
/* Select module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_CLKDIV_UART(1));
CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USB_S_RC48M, CLK_CLKDIV_USB(1));
#endif
/* Enable module clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(USBD_MODULE);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD, and Clock Output */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk | SYS_GPB_MFP_PB8_Msk);
SYS->ALT_MFP &= ~SYS_ALT_MFP_PB8_Msk;
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD | SYS_GPB_MFP_PB8_CLKO);
SYS->ALT_MFP |= SYS_ALT_MFP_PB8_CLKO;
/* Enable CLKO (PB.8) for monitor HCLK. CLKO = HCLK/8 Hz*/
EnableCLKO((2 << CLK_CLKSEL2_FRQDIV_S_Pos), 2);
}
void SYS_PLL_Test(void)
{
int32_t i;
/*---------------------------------------------------------------------------------------------------------*/
/* PLL clock configuration test */
/*---------------------------------------------------------------------------------------------------------*/
printf("\n-------------------------[ Test PLL ]-----------------------------\n");
for(i = 0; i < sizeof(g_au32PllSetting) / sizeof(g_au32PllSetting[0]) ; i++) {
/* Switch HCLK clock source to HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_CLKDIV_HCLK(1));
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware. */
CLK_DisablePLL();
/* Set PLL frequency */
CLK->PLLCON = g_au32PllSetting[i];
/* Waiting for PLL clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));
printf(" Change system clock to %d Hz ...................... ", SystemCoreClock);
/* Output selected clock to CKO, CKO Clock = HCLK / 2^(1 + 1) */
CLK_EnableCKO(CLK_CLKSEL2_FRQDIV_S_HCLK, 1, 0);
/* The delay loop is used to check if the CPU speed is increasing */
Delay(0x400000);
if(pi()) {
printf("[FAIL]\n");
} else {
printf("[OK]\n");
}
/* Disable CKO clock */
CLK_DisableCKO();
}
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Set P5 multi-function pins for XTAL1 and XTAL2 */
SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk);
SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT);
/* Enable external 12MHz XTAL (UART), HIRC */
CLK->PWRCTL = CLK_PWRCTL_XTL12M | CLK_PWRCTL_HIRCEN_Msk;
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_STATUS_XTLSTB_Msk | CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to XTL */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_XTAL,CLK_CLKDIV_HCLK(1));
/* Enable IP clock */
CLK->APBCLK = CLK_APBCLK_UART0CKEN_Msk | CLK_APBCLK_ADCCKEN_Msk | CLK_APBCLK_PWMCH01CKEN_Msk;
/* Select UART clock source from external crystal */
CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_UARTSEL_Msk) | CLK_CLKSEL1_UARTSEL_XTAL;
/* Select ADC clock source from external crystal */
CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_ADCSEL_Msk) | CLK_CLKSEL1_ADCSEL_XTAL;
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UARTSEL_XTAL,CLK_CLKDIV_UART(1));
CLK_SetModuleClock(ADC_MODULE,CLK_CLKSEL1_ADCSEL_XTAL,CLK_CLKDIV_ADC(6));
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock and CycylesPerUs automatically. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P1 multi-function pins for UART RXD, TXD and ADC channel 5 input */
SYS->P1_MFP = SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD | SYS_MFP_P15_ADC_CH5;
/* Analog pin OFFD to prevent leakage */
P1->DINOFF |= (1 << 5) << GP_DINOFF_DINOFF0_Pos;
/* Set P2 multi-function pins for PWM Channel 0. */
SYS->P2_MFP = SYS_MFP_P22_PWM0_CH0;
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable HIRC clock (Internal RC 22.1184MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK source divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV_HCLK(1));
/* Set P5 multi-function pins for crystal output/input */
SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk);
SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT);
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_XTLEN_HXT);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_XTLSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_XTAL, CLK_CLKDIV_UART(1));
/* Lock protected registers */
SYS_LockReg();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P0 multi-function pins for UART RXD and TXD */
SYS->P1_MFP &= ~(SYS_MFP_P12_Msk | SYS_MFP_P13_Msk);
SYS->P1_MFP |= (SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD);
//SYS->P0_MFP &= ~(SYS_MFP_P01_Msk | SYS_MFP_P00_Msk);
//SYS->P0_MFP |= (SYS_MFP_P01_UART0_RXD | SYS_MFP_P00_UART0_TXD);
/* Set P3 multi-function pins for Clock Output */
SYS->P3_MFP = SYS_MFP_P36_CLKO;
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external XTAL 12MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
/* Waiting for external XTAL clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(UART1_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
/* Set GPB multi-function pins for UART1 RXD, TXD, nRTS and nCTS */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk |
SYS_GPB_MFP_PB4_Msk | SYS_GPB_MFP_PB5_Msk |
SYS_GPB_MFP_PB6_Msk | SYS_GPB_MFP_PB7_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD |
SYS_GPB_MFP_PB4_UART1_RXD | SYS_GPB_MFP_PB5_UART1_TXD |
SYS_GPB_MFP_PB6_UART1_nRTS | SYS_GPB_MFP_PB7_UART1_nCTS);
SYS->ALT_MFP &= ~(SYS_ALT_MFP_PB6_Msk | SYS_ALT_MFP_PB7_Msk);
SYS->ALT_MFP |= SYS_ALT_MFP_PB6_UART1_nRTS | SYS_ALT_MFP_PB7_UART1_nCTS;
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable external 12MHz XTAL (UART), HIRC */
CLK->PWRCTL = CLK_PWRCTL_XTL12M | CLK_PWRCTL_HIRCEN_Msk;
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_STATUS_XTLSTB_Msk | CLK_STATUS_HIRCSTB_Msk);
/* Switch HCLK clock source to PLL */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL,CLK_CLKDIV_HCLK(1));
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable IP clock */
CLK->APBCLK = CLK_APBCLK_UART0CKEN_Msk | CLK_APBCLK_PWMCH01CKEN_Msk | CLK_APBCLK_PWMCH23CKEN_Msk | CLK_APBCLK_PWMCH45CKEN_Msk;
/* Select UART clock source from external crystal*/
CLK->CLKSEL1 = (CLK->CLKSEL1 & ~CLK_CLKSEL1_UARTSEL_Msk) | CLK_CLKSEL1_UARTSEL_XTAL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock and CycylesPerUs automatically. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P1 multi-function pins for UART RXD, TXD */
SYS->P1_MFP = SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD;
/* Set P0 multi-function pins for PWM Channel 5 */
SYS->P0_MFP |= SYS_MFP_P04_PWM0_CH5;
/* Set P2 multi-function pins for PWM Channel 0~4 */
SYS->P2_MFP = SYS_MFP_P22_PWM0_CH0 | SYS_MFP_P23_PWM0_CH1 |
SYS_MFP_P24_PWM0_CH2 | SYS_MFP_P25_PWM0_CH3 | SYS_MFP_P26_PWM0_CH4;
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external XTAL 12MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
/* Waiting for external XTAL clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART0 and UART1 module clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(UART1_MODULE);
CLK_EnableModuleClock(TMR0_MODULE);
/* Select UART0 and UART1 module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P3 multi-function pins for UART0 RXD and TXD */
SYS->P3_MFP &= ~(SYS_MFP_P30_Msk | SYS_MFP_P31_Msk);
SYS->P3_MFP |= (SYS_MFP_P30_RXD0 | SYS_MFP_P31_TXD0);
/* Set P0 multi-function pins for UART1 RXD and TXD */
SYS->P0_MFP &= ~(SYS_MFP_P00_Msk | SYS_MFP_P01_Msk);
SYS->P0_MFP |= (SYS_MFP_P00_TXD1 | SYS_MFP_P01_RXD1);
}
/**
* @brief This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz
* @param u32Hclk is HCLK frequency
* @return HCLK frequency
*/
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
{
if(u32Hclk > FREQ_50MHZ)
u32Hclk = FREQ_50MHZ;
else if(u32Hclk < FREQ_25MHZ)
u32Hclk = FREQ_25MHZ;
if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk);
else
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, u32Hclk);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));
return u32Hclk;
}
/**
* @brief Set HCLK frequency
* @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 25 MHz ~ 50 MHz.
* @return HCLK frequency
* @details This function is used to set HCLK frequency. The frequency unit is Hz.
* It would configure PLL frequency to 50MHz ~ 100MHz,
* set HCLK clock divider as 2 and switch HCLK clock source to PLL.
* The register write-protection function should be disabled before using this function.
*/
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
{
uint32_t u32HIRCSTB;
/* Read HIRC clock source stable flag */
u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
/* The range of u32Hclk is 25 MHz ~ 50 MHz */
if(u32Hclk > FREQ_50MHZ)
u32Hclk = FREQ_50MHZ;
if(u32Hclk < FREQ_25MHZ)
u32Hclk = FREQ_25MHZ;
/* Switch HCLK clock source to HIRC clock for safe */
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_Msk;
CLK->CLKDIV &= (~CLK_CLKDIV_HCLK_N_Msk);
/* Configure PLL setting if HXT clock is enabled */
if(CLK->PWRCON & CLK_PWRCON_XTL12M_EN_Msk)
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, (u32Hclk << 1));
/* Configure PLL setting if HXT clock is not enabled */
else
{
u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, (u32Hclk << 1));
/* Read HIRC clock source stable flag */
u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;
}
/* Select HCLK clock source to PLL,
Select HCLK clock source divider as 2
and update system core clock
*/
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));
/* Disable HIRC if HIRC is disabled before setting core clock */
if( u32HIRCSTB == 0 )
CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk;
/* Return actually HCLK frequency is PLL frequency divide 2 */
return u32Hclk >> 1;
}
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P5 multi-function pins for XTAL1 and XTAL2 */
SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk);
SYS->P5_MFP |= (SYS_MFP_P50_XTAL1 | SYS_MFP_P51_XTAL2);
/* Enable external 12MHz XTAL, internal 22.1184MHz */
CLK_EnableXtalRC(CLK_PWRCON_HXT|CLK_PWRCON_HIRC_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL_STB_Msk | CLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to XTL */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_XTAL,CLK_CLKDIV_HCLK(1));
/* STCLK to XTL STCLK to XTL */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_XTAL);
/* Enable IP clock */
CLK_EnableModuleClock(UART_MODULE);
CLK_EnableModuleClock(I2C_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART_MODULE,CLK_CLKSEL1_UART_S_XTAL,CLK_CLKDIV_UART(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P0 multi-function pins for UART RXD and TXD */
SYS->P0_MFP &= ~(SYS_MFP_P01_Msk | SYS_MFP_P00_Msk);
SYS->P0_MFP |= (SYS_MFP_P01_RXD | SYS_MFP_P00_TXD);
/* Lock protected registers */
SYS_LockReg();
/* Update System Core Clock */
SystemCoreClockUpdate();
}
void setupSystemClock(void)
{
SYS_UnlockReg();
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCON_HIRC_EN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* To update the variable SystemCoreClock */
SystemCoreClockUpdate();
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external XTAL 12MHz clock and internal 10 kHz */
CLK_EnableXtalRC((CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC10K_EN_Msk));
/* Waiting for clock ready */
CLK_WaitClockReady((CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC10K_STB_Msk));
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
/* Enable WDT module clock */
CLK_EnableModuleClock(WDT_MODULE);
/* Select WDT module clock source */
CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDT_S_LIRC, NULL);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB multi-function pins for UART0 RXD, TXD */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);
}
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable Internal RC clock */
CLK->PWRCON |= CLK_PWRCON_XTL12M | CLK_PWRCON_OSC10K_EN_Msk | CLK_PWRCON_IRC22M_EN_Msk;
CLK_SysTickDelay(1200);
/* Waiting for IRC22M clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL_STB_Msk | CLK_CLKSTATUS_IRC22M_STB_Msk);
/* IP clock divider */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_XTAL);
/* Switch HCLK clock source to XTL */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_XTAL,CLK_CLKDIV_HCLK(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART_MODULE);
CLK_EnableModuleClock(TMR1_MODULE);
/* IP clock source */
CLK->CLKSEL1 = ( CLK->CLKSEL1 & (~CLK_CLKSEL1_UART_S_Msk) ) | CLK_CLKSEL1_UART_S_XTAL | CLK_CLKSEL1_TMR1_S_HCLK;
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P0 multi-function pins for UART RXD and TXD */
SYS->P0_MFP &= ~(SYS_MFP_P01_Msk | SYS_MFP_P00_Msk);
SYS->P0_MFP |= (SYS_MFP_P01_RXD | SYS_MFP_P00_TXD);
/* To update the variable SystemCoreClock */
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Set P5 multi-function pins for XTAL1 and XTAL2 */
SYS->P5_MFP &= ~(SYS_MFP_P50_Msk | SYS_MFP_P51_Msk);
SYS->P5_MFP |= (SYS_MFP_P50_XT1_IN | SYS_MFP_P51_XT1_OUT);
/* Enable external 12MHz XTAL (UART), and HIRC */
CLK->PWRCTL = CLK_PWRCTL_XTL12M | CLK_PWRCTL_HIRCEN_Msk;
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk | CLK_STATUS_XTLSTB_Msk);
/* Switch HCLK clock source to XTL */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_XTAL, CLK_CLKDIV_HCLK(1));
/* STCLK to XTL STCLK to XTL */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLKSEL_XTAL);
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_XTAL, CLK_CLKDIV_UART(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set P1 multi-function pins for UART RXD, TXD */
SYS->P1_MFP = SYS_MFP_P12_UART0_RXD | SYS_MFP_P13_UART0_TXD;
/* To update the variable SystemCoreClock */
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock */
CLK_EnableXtalRC(CLK_PWRCON_IRC22M_EN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_IRC22M_STB_Msk);
/* Switch HCLK clock source to HIRC */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable HXT and LIRC */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_IRC10K_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_IRC10K_STB_Msk);
/* Set core clock as PLL_CLOCK from PLL and SysTick source to HCLK/2*/
CLK_SetCoreClock(PLL_CLOCK);
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_HCLK_DIV2);
/* Enable peripheral clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(WDT_MODULE);
/* Peripheral clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_PLL, CLK_CLKDIV_UART(1));
CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDT_S_LIRC, 0);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB multi-function pins for UART0 RXD, TXD */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);
}
static void rt_hw_system_init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
SYS_UnlockReg();
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(BOARD_PLL_CLOCK);
/* Set SysTick clock source to HCLK source divide 2 */
CLK_SetSysTickClockSrc(CLK_CLKSEL0_STCLK_S_HCLK_DIV2);
SYS_LockReg();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for IRC22M clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external 12MHz XTAL, internal 22.1184MHz */
CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk | CLK_PWRCON_OSC22M_EN_Msk);
/* Enable PLL and Set PLL frequency */
CLK_SetCoreClock(PLL_CLOCK);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk | CLK_CLKSTATUS_XTL12M_STB_Msk | CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to PLL, STCLK to HCLK/2 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(2));
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_CLKDIV_UART(1));
/* Enable PWM0 clock source */
CLK_EnableModuleClock(PWM0_MODULE);
/* Select PWM module clock source */
//CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL3_PWM0_S_HClK, 0);
CLK_SetModuleClock(PWM0_MODULE, CLK_CLKSEL3_PWM0_S_PLL, 0);
/* Reset PWM0 */
SYS_ResetModule(PWM0_RST);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);
/* Set GPA multi-function pins for PWM0 Channel 0 */
SYS->GPA_MFP &= ~(SYS_GPA_MFP_PA12_Msk);
SYS->GPA_MFP |= (SYS_GPA_MFP_PA12_PWM0_CH0);
SYS->ALT_MFP4 &= ~(SYS_ALT_MFP4_PA12_Msk);
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint32_t u32data;
/* In end of main function, program issued CPU reset and write-protection will be disabled. */
if(SYS_IsRegLocked() == 0)
SYS_LockReg();
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Change system clock depended on different PLL settings
5. Output system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+--------------------------------------------+\n");
printf("| NUC029xEE System Driver Sample Code |\n");
printf("+--------------------------------------------+\n");
if(M32(FLAG_ADDR) == SIGNATURE) {
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
getchar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS_ReadPDID());
/* Get reset source from last operation */
u32data = SYS_GetResetSrc();
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS_ClearResetSrc(u32data);
/* Unlock protected registers for Brown-Out Detector settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if(SYS_IsRegLocked() == 0) {
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector, and set Brown-Out Detector voltage 2.7V */
SYS_EnableBOD(SYS_BODCR_BOD_INTERRUPT_EN, SYS_BODCR_BOD_VL_2_7V);
/* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn);
/* Enable Low Voltage Reset function */
SYS_ENABLE_LVR();
/* Run PLL Test */
SYS_PLL_Test();
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Waiting for message send out */
UART_WAIT_TX_EMPTY(UART0);
/* Switch HCLK clock source to Internal RC 22.1184MHz clock and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Set PLL to Power down mode and HW will also clear PLL_STB bit in CLKSTATUS register */
CLK_DisablePLL();
/* Reset CPU */
SYS_ResetCPU();
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable XT1_OUT(PF0) and XT1_IN(PF1) */
// SYS->GPF_MFP |= SYS_GPF_MFP_PF0_XT1_OUT | SYS_GPF_MFP_PF1_XT1_IN;
/* Enable Internal RC 22.1184MHz clock */
CLK_EnableXtalRC(CLK_PWRCON_OSC22M_EN_Msk);
/* Waiting for Internal RC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Enable external XTAL 12MHz clock */
// CLK_EnableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
//check if external xtal is working, if not, disable it
// if(CLK_WaitClockReady(CLK_CLKSTATUS_XTL12M_STB_Msk) == 0) {
// CLK_DisableXtalRC(CLK_PWRCON_XTL12M_EN_Msk);
// }
/* Set core clock */
CLK_SetCoreClock(HCLK_CLOCK);
/* Enable module clocks */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(SPI0_MODULE);
CLK_EnableModuleClock(SPI1_MODULE);
CLK_EnableModuleClock(TMR0_MODULE);
CLK_EnableModuleClock(TMR1_MODULE);
CLK_EnableModuleClock(TMR2_MODULE);
CLK_EnableModuleClock(TMR3_MODULE);
CLK_EnableModuleClock(USBD_MODULE);
CLK_EnableModuleClock(WDT_MODULE);
/* Select HCLK as the clock source of SPI0 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, UART_CLKDIV);
CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL1_SPI0_S_HCLK, MODULE_NoMsk);
CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL1_SPI1_S_HCLK, MODULE_NoMsk);
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HCLK, 0);
CLK_SetModuleClock(TMR1_MODULE, CLK_CLKSEL1_TMR1_S_HCLK, 0);
CLK_SetModuleClock(TMR2_MODULE, CLK_CLKSEL1_TMR2_S_HCLK, 0);
CLK_SetModuleClock(TMR3_MODULE, CLK_CLKSEL1_TMR3_S_HCLK, 0);
CLK_SetModuleClock(USBD_MODULE, 0, USB_CLKDIV);
CLK_SetModuleClock(WDT_MODULE, CLK_CLKSEL1_WDT_S_LIRC, 0);
/* Select UART module clock source */
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD(PB.0) and TXD(PB.1) */
SYS->GPC_MFP &= ~(SYS_GPC_MFP_PC4_Msk | SYS_GPC_MFP_PC5_Msk);
SYS->GPC_MFP = SYS_GPC_MFP_PC4_UART0_RXD | SYS_GPC_MFP_PC5_UART0_TXD;
SYS->ALT_MFP = SYS_ALT_MFP_PC4_UART0_RXD | SYS_ALT_MFP_PC5_UART0_TXD;
/* Setup SPI0 multi-function pins */
SYS->GPC_MFP |= SYS_GPC_MFP_PC0_SPI0_SS0 | SYS_GPC_MFP_PC1_SPI0_CLK | SYS_GPC_MFP_PC2_SPI0_MISO0 | SYS_GPC_MFP_PC3_SPI0_MOSI0;
SYS->ALT_MFP |= SYS_ALT_MFP_PC0_SPI0_SS0 | SYS_ALT_MFP_PC1_SPI0_CLK | SYS_ALT_MFP_PC2_SPI0_MISO0 | SYS_ALT_MFP_PC3_SPI0_MOSI0;
/* Setup SPI1 multi-function pins */
SYS->GPC_MFP |= SYS_GPC_MFP_PC8_SPI1_SS0 | SYS_GPC_MFP_PC9_SPI1_CLK | SYS_GPC_MFP_PC10_SPI1_MISO0 | SYS_GPC_MFP_PC11_SPI1_MOSI0;
SYS->ALT_MFP |= SYS_ALT_MFP_PC8_SPI1_SS0 | SYS_ALT_MFP_PC9_SPI1_CLK | SYS_ALT_MFP_PC10_SPI1_MISO0 | SYS_ALT_MFP_PC11_SPI1_MOSI0;
//enable PF3 gpio mode
SYS->GPF_MFP = SYS_GPF_MFP_PF3_GPIO;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock and cyclesPerUs automatically. */
SystemCoreClockUpdate();
/* Enable interrupt de-bounce function and select de-bounce sampling cycle time is 1024 clocks of LIRC clock */
GPIO_SET_DEBOUNCE_TIME(GPIO_DBCLKSRC_HCLK, GPIO_DBCLKSEL_128);
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
/* Waiting for Internal RC clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk));
/* Switch HCLK clock source to Internal RC and HCLK source divide 1 */
CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;
CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
CLK->CLKDIV |= CLK_CLKDIV_HCLK(1);
/* Enable external XTAL 12MHz clock */
CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
/* Waiting for external XTAL clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk));
/* System optimization when CPU runs at 72MHz */
FMC->FATCON |= 0x50;
/* Set core clock as PLL_CLOCK from PLL */
CLK->PLLCON = PLLCON_SETTING;
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));
CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_PLL;
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
//SystemCoreClockUpdate();
PllClock = PLL_CLOCK; // PLL
SystemCoreClock = PLL_CLOCK / 1; // HCLK
CyclesPerUs = PLL_CLOCK / 1000000; // For SYS_SysTickDelay()
/* Enable UART module clock */
CLK->APBCLK |= CLK_APBCLK_UART0_EN_Msk | CLK_APBCLK_PWM01_EN_Msk | CLK_APBCLK_PWM23_EN_Msk;
/* Select UART module clock source */
CLK->CLKSEL1 &= ~CLK_CLKSEL1_UART_S_Msk;
CLK->CLKSEL1 |= CLK_CLKSEL1_UART_S_HXT;
/* Select PWM clock source */
CLK->CLKSEL1 = (CLK->CLKSEL1 & ~(CLK_CLKSEL1_PWM01_S_Msk | CLK_CLKSEL1_PWM23_S_Msk)) | \
(CLK_CLKSEL1_PWM01_S_HXT | CLK_CLKSEL1_PWM23_S_HXT);
CLK->CLKSEL2 = (CLK->CLKSEL2 & ~(CLK_CLKSEL2_PWM01_S_E_Msk | CLK_CLKSEL2_PWM23_S_E_Msk)) | \
(CLK->CLKSEL2 |= CLK_CLKSEL2_PWM01_EXT_HXT | CLK_CLKSEL2_PWM23_EXT_HXT);
/* User can select PWM module clock source from LIRC as below */
//CLK->CLKSEL1 = (CLK->CLKSEL1 & ~(CLK_CLKSEL1_PWM01_S_Msk | CLK_CLKSEL1_PWM23_S_Msk)) | \
// (CLK_CLKSEL1_PWM01_S_LIRC | CLK_CLKSEL1_PWM23_S_LIRC);
//CLK->CLKSEL2 = (CLK->CLKSEL2 & ~(CLK_CLKSEL2_PWM01_S_E_Msk | CLK_CLKSEL2_PWM23_S_E_Msk)) | \
// (CLK->CLKSEL2 |= CLK_CLKSEL2_PWM01_EXT_LIRC | CLK_CLKSEL2_PWM23_EXT_LIRC);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
SYS->GPB_MFP &= ~(SYS_GPB_MFP_PB0_Msk | SYS_GPB_MFP_PB1_Msk);
SYS->GPB_MFP |= (SYS_GPB_MFP_PB0_UART0_RXD | SYS_GPB_MFP_PB1_UART0_TXD);
/* Set GPA multi-function pins for PWMA Channel0 */
SYS->GPA_MFP &= ~(SYS_GPA_MFP_PA12_Msk);
SYS->GPA_MFP |= SYS_GPA_MFP_PA12_PWM0;
SYS->ALT_MFP &= ~(SYS_ALT_MFP_PA12_Msk);
SYS->ALT_MFP |= SYS_ALT_MFP_PA12_PWM0;
}
