/*--------------------------------------------------------------------------*/
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable external 12MHz HXT */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, 96000000);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_PLL_STB_Msk);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(3));
/* Select IP clock source */
CLK_SetModuleClock(USBD_MODULE, 0, CLK_USB_CLK_DIVIDER(2));
/* Enable IP clock */
CLK_EnableModuleClock(USBD_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_UART_CLK_DIVIDER(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for UART0 RXD and TXD */
SYS->PA_H_MFP &= ~( SYS_PA_H_MFP_PA15_MFP_Msk | SYS_PA_H_MFP_PA14_MFP_Msk);
SYS->PA_H_MFP |= (SYS_PA_H_MFP_PA15_MFP_UART0_TX|SYS_PA_H_MFP_PA14_MFP_UART0_RX);
/* Lock protected registers */
SYS_LockReg();
}
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));
/* Enable external 12MHz HXT, 32KHz LXT and HIRC */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);
/* Set HCLK frequency 12MHz */
CLK_SetCoreClock(12000000);
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HIRC,CLK_UART_CLK_DIVIDER(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for UART0 RXD and TXD */
SYS->PA_H_MFP &= ~( SYS_PA_H_MFP_PA15_MFP_Msk | SYS_PA_H_MFP_PA14_MFP_Msk);
SYS->PA_H_MFP |= (SYS_PA_H_MFP_PA15_MFP_UART0_TX|SYS_PA_H_MFP_PA14_MFP_UART0_RX);
/* Set PB multi-function pins for Clock Output */
SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) | SYS_PB_H_MFP_PB12_MFP_CKO;
/* Lock protected registers */
SYS_LockReg();
}
/*---------------------------------------------------------------------------------------------------------*/
void SysInit(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));
/* Enable external 12MHz HXT, 32KHz LXT and HIRC */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);
#if 1
SYS->PB_H_MFP &= ~( SYS_PB_H_MFP_PB14_MFP_Msk | SYS_PB_H_MFP_PB13_MFP_Msk);
SYS->PB_H_MFP |= (SYS_PB_H_MFP_PB14_MFP_UART0_TX | SYS_PB_H_MFP_PB13_MFP_UART0_RX );
UART0->BAUD = 0x67; /* Baud Rate:115200 OSC:12MHz */
//UART0->BAUD = 0x60; /* Baud Rate:115200 OSC:11.0592 MHz */
UART0->TLCTL = (UART0->TLCTL & ~0x3) | 0x3; /* character len is 8 bits */
UART0->TLCTL |= (1<<2);
#endif
/* Set HCLK frequency 32MHz */
CLK_SetCoreClock(32000000);
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Enable PWM clock */
CLK_EnableModuleClock(PWM0_CH01_MODULE);
CLK_EnableModuleClock(PWM0_CH23_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HIRC,CLK_UART_CLK_DIVIDER(1));
/* Set HCLK as PWM clock source */
CLK_SetModuleClock(PWM0_CH01_MODULE, CLK_CLKSEL1_PWM0_CH01_S_HCLK, 0);
CLK_SetModuleClock(PWM0_CH23_MODULE, CLK_CLKSEL1_PWM0_CH23_S_HCLK, 0);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for UART0 RXD and TXD */
SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);
SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX );
/* Set PB multi-function pins for Clock Output */
SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) | SYS_PB_H_MFP_PB12_MFP_CKO0;
/* Set PB and PE multi-function pins for PWM */
SYS->PB_H_MFP = (SYS->PB_H_MFP & ~(SYS_PB_H_MFP_PB8_MFP_Msk | SYS_PB_H_MFP_PB9_MFP_Msk)) | SYS_PB_H_MFP_PB8_MFP_PWM0_CH0 | SYS_PB_H_MFP_PB9_MFP_PWM0_CH1;
SYS->PE_H_MFP = (SYS->PE_H_MFP & ~(SYS_PE_H_MFP_PE8_MFP_Msk | SYS_PE_H_MFP_PE9_MFP_Msk)) | SYS_PE_H_MFP_PE8_MFP_PWM0_CH2 | SYS_PE_H_MFP_PE9_MFP_PWM0_CH3;
/* Lock protected registers */
SYS_LockReg();
}
/*---------------------------------------------------------------------------------------------------------*/
void SysInit(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));
/* Enable external 12MHz HXT, 32KHz LXT and HIRC */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);
#if 1
SYS->PB_H_MFP &= ~( SYS_PB_H_MFP_PB14_MFP_Msk | SYS_PB_H_MFP_PB13_MFP_Msk);
SYS->PB_H_MFP |= (SYS_PB_H_MFP_PB14_MFP_UART0_TX | SYS_PB_H_MFP_PB13_MFP_UART0_RX );
UART0->BAUD = 0x67; /* Baud Rate:115200 OSC:12MHz */
//UART0->BAUD = 0x60; /* Baud Rate:115200 OSC:11.0592 MHz */
UART0->TLCTL = (UART0->TLCTL & ~0x3) | 0x3; /* character len is 8 bits */
UART0->TLCTL |= (1<<2);
#endif
/* Set HCLK frequency 32MHz */
CLK_SetCoreClock(32000000);
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HIRC,CLK_UART_CLK_DIVIDER(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for UART0 RXD and TXD */
SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);
SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX );
/* Set PB multi-function pins for Clock Output */
SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) | SYS_PB_H_MFP_PB12_MFP_CKO0;
/* Set PA multi-function pins for ADC */
SYS->PA_L_MFP &= ~(SYS_PA_L_MFP_PA0_MFP_Msk | SYS_PA_L_MFP_PA1_MFP_Msk | SYS_PA_L_MFP_PA2_MFP_Msk);
SYS->PA_L_MFP |= SYS_PA_L_MFP_PA0_MFP_ADC_CH0 | SYS_PA_L_MFP_PA1_MFP_ADC_CH1 | SYS_PA_L_MFP_PA2_MFP_ADC_CH2;
/* Disable digital input path */
PA->OFFD = PA->OFFD | ((ADC_CH_0_MASK | ADC_CH_1_MASK | ADC_CH_2_MASK)<< 16);
/* Enable ADC clock */
CLK_EnableModuleClock(ADC_MODULE);
/* Lock protected registers */
SYS_LockReg();
}
/**
* @brief This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz
* @param u32Hclk is HCLK frequency
* @return None
*/
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
{
if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN) {
CLK_EnablePLL( CLK_PLLCTL_PLL_SRC_HXT,u32Hclk);
} else {
CLK_EnablePLL( CLK_PLLCTL_PLL_SRC_HIRC,u32Hclk);
}
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL,CLK_HCLK_CLK_DIVIDER(1));
return SystemCoreClock;
}
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));
/* Enable external 12MHz HXT, 32KHz LXT and HIRC */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);
/* Set HCLK frequency 32MHz */
CLK_SetCoreClock(32000000);
CLK->AHBCLK |= CLK_AHBCLK_DMA_EN_Msk;
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Enable ADC clock */
CLK_EnableModuleClock(ADC_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_UART_CLK_DIVIDER(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for UART0 RXD and TXD */
SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);
SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_RX | SYS_PB_L_MFP_PB1_MFP_UART0_TX );
/* Set PB multi-function pins for Clock Output */
SYS->PB_H_MFP = ( SYS->PB_H_MFP & ~SYS_PB_H_MFP_PB12_MFP_Msk ) | SYS_PB_H_MFP_PB12_MFP_CKO;
/* Set PA.0,PA.1,PA.2,PA.3 multi-function pin for ADC channel 0,1,2,3 */
SYS->PA_L_MFP = (SYS->PA_L_MFP & ~SYS_PA_L_MFP_PA0_MFP_Msk) | SYS_PA_L_MFP_PA0_MFP_ADC_CH0;
SYS->PA_L_MFP = (SYS->PA_L_MFP & ~SYS_PA_L_MFP_PA1_MFP_Msk) | SYS_PA_L_MFP_PA1_MFP_ADC_CH1;
SYS->PA_L_MFP = (SYS->PA_L_MFP & ~SYS_PA_L_MFP_PA2_MFP_Msk) | SYS_PA_L_MFP_PA2_MFP_ADC_CH2;
SYS->PA_L_MFP = (SYS->PA_L_MFP & ~SYS_PA_L_MFP_PA3_MFP_Msk) | SYS_PA_L_MFP_PA3_MFP_ADC_CH3;
/* Disable PA.0 digital input path */
PA->OFFD |= ((1 << 0) << GP_OFFD_OFFD_Pos);
/* Lock protected registers */
SYS_LockReg();
}
void SysInit(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable External XTAL (4~24 MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);
/* Waiting for 12MHz clock ready */
CLK_WaitClockReady( CLK_CLKSTATUS_HXT_STB_Msk);
/* Switch HCLK clock source to HXT */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(TMR0_MODULE);
CLK_EnableModuleClock(TMR1_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HXT, CLK_UART_CLK_DIVIDER(1));
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, CLK_TMR0_CLK_DIVIDER(1));
CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR1_S_HXT, CLK_TMR1_CLK_DIVIDER(1));
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set GPB multi-function pins for UART0 RXD and TXD */
SYS->PB_L_MFP &= ~(SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);
SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX);
/* Set Timer0 event counting/toggle out pin */
SYS->PB_H_MFP &= ~SYS_PB_H_MFP_PB8_MFP_Msk;
SYS->PB_H_MFP |= SYS_PB_H_MFP_PB8_MFP_TMR0_EXT;
/* Lock protected registers */
SYS_LockReg();
}
void SysInit(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));
/* Enable external 12MHz HXT, 32KHz LXT and HIRC */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);
/* Set HCLK frequency 32MHz */
CLK_SetCoreClock(32000000);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART_S_HIRC, CLK_UART_CLK_DIVIDER(1));
CLK_SetModuleClock(I2C0_MODULE, 0, 0);
CLK_SetModuleClock(I2C1_MODULE, 0, 0);
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(I2C0_MODULE);
CLK_EnableModuleClock(I2C1_MODULE);
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate PllClock, SystemCoreClock and CycylesPerUs automatically. */
SystemCoreClockUpdate();
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PB multi-function pins for UART0 RXD and TXD */
SYS->PB_L_MFP &= ~(SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);
SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_TX | SYS_PB_L_MFP_PB1_MFP_UART0_RX);
/* Set multi function pin for I2C0/I2C1 */
SYS->PC_L_MFP = (SYS_PC_L_MFP_PC0_MFP_I2C0_SCL | SYS_PC_L_MFP_PC1_MFP_I2C0_SDA | SYS_PC_L_MFP_PC2_MFP_I2C1_SCL | SYS_PC_L_MFP_PC3_MFP_I2C1_SDA);
/* Lock protected registers */
SYS_LockReg();
}
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT,CLK_HCLK_CLK_DIVIDER(1));
/* Enable external 12MHz HXT, 32KHz LXT and HIRC */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk | CLK_PWRCTL_LXT_EN_Msk | CLK_PWRCTL_HIRC_EN_Msk);
/* Waiting for clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk | CLK_CLKSTATUS_LXT_STB_Msk | CLK_CLKSTATUS_HIRC_STB_Msk);
/* Set HCLK frequency 42MHz */
CLK_SetCoreClock(42000000);
/* Enable IP clock */
CLK_EnableModuleClock(UART0_MODULE);
CLK_EnableModuleClock(TMR0_MODULE);
/* Enable DAC clock */
CLK->APBCLK |= CLK_APBCLK_DAC_EN_Msk;
/* Enable DMA clock */
CLK->AHBCLK |= CLK_AHBCLK_DMA_EN_Msk;
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE,CLK_CLKSEL1_UART_S_HXT,CLK_UART_CLK_DIVIDER(1));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PA multi-function pins for UART0 RXD and TXD */
SYS->PB_L_MFP &= ~( SYS_PB_L_MFP_PB0_MFP_Msk | SYS_PB_L_MFP_PB1_MFP_Msk);
SYS->PB_L_MFP |= (SYS_PB_L_MFP_PB0_MFP_UART0_RX | SYS_PB_L_MFP_PB1_MFP_UART0_TX );
/* Set PC.6 multi-function pin for DAC channel 0 */
SYS->PC_L_MFP &= ~(SYS_PC_L_MFP_PC6_MFP_Msk);
SYS->PC_L_MFP |= SYS_PC_L_MFP_PC6_MFP_DA_OUT0;
/* Disable digital input path for both PC.6 */
GPIO_DISABLE_DIGITAL_PATH(PC, 1 << 6);
/* Lock protected registers */
SYS_LockReg();
}
int32_t main (void)
{
uint32_t u32data;
/* HCLK will be set to 42MHz in SYS_Init(void)*/
if(SYS->RegLockAddr == 1) // In end of main function, program issued CPU reset and write-protection will be disabled.
SYS_LockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init(); //In the end of SYS_Init() will issue SYS_LockReg() to lock protected register. If user want to write protected register, please issue SYS_UnlockReg() to unlock protected register.
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Output system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+----------------------------------------+\n");
printf("| Nano100 System Driver Sample Code |\n");
printf("+----------------------------------------+\n");
if (M32(FLAG_ADDR) == SIGNATURE)
{
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
GetChar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS->PDID);
/* Get reset source from last operation */
u32data = SYS_GetResetSrc();
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS_ClearResetSrc(u32data);
/* Unlock protected registers for Brown-Out Detector and power down settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if (SYS->RegLockAddr != 0)
{
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector and Low Voltage Reset function, and set Brown-Out Detector voltage 2.5V ,
Enable Brown-Out Interrupt function */
SYS_EnableBOD(SYS_BODCTL_BOD25_INT_EN_Msk,SYS_BODCTL_BOD25_EN_Msk);
/* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn);
/* Waiting for message send out */
// _UART_WAIT_TX_EMPTY(UART0);
/* Enable CKO and output frequency = system clock / 4 */
CLK_EnableCKO(CLK_CLKSEL2_FRQDIV_S_HCLK,1);
/* Switch HCLK clock source to Internal 11.0592MHz */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC,CLK_HCLK_CLK_DIVIDER(1));
/* Enable WDT clock */
CLK_EnableModuleClock(WDT_MODULE);
/* Enable WDT and interrupt */
WDT->CTL = 0x00000050 | 0x00000004 | 0x00000008;
WDT->IER |= 0x00000001;
NVIC_EnableIRQ(WDT_IRQn);
CLK->PWRCTL |= CLK_PWRCTL_WAKEINT_EN; /* Enable wake up interrupt source */
NVIC_EnableIRQ(PDWU_IRQn); /* Enable IRQ request for PDWU interrupt */
printf("u32PWDU_WakeFlag = %x\n",u32PWDU_WakeFlag);
printf("Enter Power Down Mode >>>>>>>>>>>\n");
u32PWDU_WakeFlag = 0; /* clear software semaphore */
while(!(UART0->FSR & UART_FSR_TX_EMPTY_F_Msk)) ; /* waits for message send out */
CLK_PowerDown();
/* CPU Reset test */
printf("Waits for 5 times WDT interrupts.....\n");
while (u32WDT_Ticks <= 5);
printf("<<<<<<<<<< Program resumes execution.\n");
printf("u32PWDU_WakeFlag = %x\n",u32PWDU_WakeFlag);
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Reset CPU */
SYS_ResetCPU();
}
void mbed_sdk_init(void)
{
// NOTE: Support singleton semantics to be called from other init functions
static int inited = 0;
if (inited) {
return;
}
inited = 1;
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
/* Enable HIRC clock (internal OSC 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRC_EN_Msk);
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXT_EN_Msk);
/* Enable LIRC clock (OSC 10KHz) for lp_ticker */
CLK_EnableXtalRC(CLK_PWRCTL_LIRC_EN_Msk);
/* Enable LXT clock (XTAL 32KHz) for RTC */
CLK_EnableXtalRC(CLK_PWRCTL_LXT_EN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HIRC_STB_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_HXT_STB_Msk);
/* Wait for LIRC clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_LIRC_STB_Msk);
/* Wait for LXT clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_LXT_STB_Msk);
/* Set HCLK source form HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_HCLK_CLK_DIVIDER(1));
/* Select HXT/HIRC to clock PLL
*
* Comparison between HXT/HIRC-clocked PLL:
* 1. Spare HXT on board if only HIRC is used.
* 2. HIRC has shorter stable time.
* 3. HXT has better accuracy. USBD requires HXT-clocked PLL.
* 4. HIRC has shorter wake-up time from power-down mode.
* Per test, wake-up time from power-down mode would take:
* T1. 1~13 ms (proportional to deep sleep time) with HXT-clocked PLL as HCLK clock source
* T2. <1 ms with HIRC-clocked PLL as HCLK clock source
* T1 will fail Greentea test which requires max 10 ms wake-up time.
*
* If we just call CLK_SetCoreClock(FREQ_42MHZ) to configure HCLK to 42 MHz,
* it will go T1 with HXT already enabled in front. So we manually configure
* it to choose HXT/HIRC-clocked PLL.
*/
#define NU_HXT_PLL 1
#define NU_HIRC_PLL 2
#ifndef NU_CLOCK_PLL
#define NU_CLOCK_PLL NU_HIRC_PLL
#endif
#if (NU_CLOCK_PLL == NU_HXT_PLL)
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HXT, FREQ_42MHZ*2);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
#elif (NU_CLOCK_PLL == NU_HIRC_PLL)
CLK_EnablePLL(CLK_PLLCTL_PLL_SRC_HIRC, FREQ_42MHZ*2);
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_HCLK_CLK_DIVIDER(2));
#endif
/* Update System Core Clock */
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
SystemCoreClockUpdate();
/* Lock protected registers */
SYS_LockReg();
}