/*
* Initialize the CMP for operation, interrupts, clock select, input select
*
*
* NOTE: Since the Comparators are pinned out in multiple locations on most
* Kinetis devices, this driver does not enable CMP pin functions.
* The desired pins should be enabled before calling this init function.
*
* Parameters:
* cmpch - CMP channel to initialize
* rising_falling - equal to bit mask in the CMP_SCR Register
* CMP_SCR_IER_MASK or CMP_SCR_IEF_MASK
* the reset of these inputs are not yet implemented
* clk - CMP module Clock
* inp cmp pos input selection
* inn cmp neg input selection
* outen cmp output enable
* dacval cmp dac input setting.
*/
void cmp_init ( unsigned char rising_falling )
{
// Filter and digital hysteresis disabled
CMP0_CR0 = 0x00;
// no sample(continuous), no window, -, HS mode,
// no invert, COUTA(unfiltered), output pin enable, moduledisable
CMP0_CR1 = CMP_CR1_PMODE_MASK | CMP_CR1_COS_MASK | CMP_CR1_OPE_MASK; //0x16;
// Filter disabled
CMP0_FPR = 0x00;
// Enable rising or falling edge interrupts, clear flags
CMP0_SCR = //CMP_SCR_IER_MASK |
rising_falling |
//CMP_SCR_IEF_MASK |
CMP_SCR_CFR_MASK |
CMP_SCR_CFF_MASK; //0x1E
// 6-bit DAC enabled, output set to 1/2-scale, Vdd reference
CMP0_DACCR = CMP_DACCR_DACEN_MASK |
CMP_DACCR_VRSEL_MASK |
CMP_DACCR_VOSEL(0x20); //0xE0;
// P-input as external channel 0, M-input as 6b DAC
CMP0_MUXCR = CMP_MUXCR_PSEL(0) |
CMP_MUXCR_MSEL(7); //0x07;
// enable CMP
CMP0_CR1 |= CMP_CR1_EN_MASK;
}
int cmp_init(void){
//Clock to the comparator
SIM->SCGC4|=SIM_SCGC4_CMP_MASK;
CMP1->CR1=CMP_CR1_EN_MASK; // Enable the comparator
//Enable Dac, VIn1, Voltage 19/32*Vref
CMP1->DACCR=CMP_DACCR_DACEN(1)|CMP_DACCR_VRSEL(0)|CMP_DACCR_VOSEL(40);
CMP1->MUXCR=CMP_MUXCR_PSEL(1)|CMP_MUXCR_MSEL(7); //+=Sense -=DAC
}
void CMP_SetDACConfig(CMP_Type *base, const cmp_dac_config_t *config)
{
uint8_t tmp8 = 0U;
if (NULL == config)
{
/* Passing "NULL" as input parameter means no available configuration. So the DAC feature is disabled.*/
base->DACCR = 0U;
return;
}
/* CMPx_DACCR. */
tmp8 |= CMP_DACCR_DACEN_MASK; /* Enable the internal DAC. */
if (kCMP_VrefSourceVin2 == config->referenceVoltageSource)
{
tmp8 |= CMP_DACCR_VRSEL_MASK;
}
tmp8 |= CMP_DACCR_VOSEL(config->DACValue);
base->DACCR = tmp8;
}
_mqx_int _bsp_serial_irda_rx_init(uint32_t device_index, bool enable)
{
PORT_MemMapPtr pctl;
SIM_MemMapPtr sim = SIM_BASE_PTR;
CMP_MemMapPtr cmp = CMP0_BASE_PTR;
if (TRUE == enable)
{
/* Enable comparator module */
sim->SCGC4 |= SIM_SCGC4_CMP_MASK;
/* Select RX source for UART */
switch (device_index) {
case 0:
sim->SOPT5 &= ~SIM_SOPT5_UART0RXSRC_MASK;
/* Select CMP0 as RX source for UART0*/
sim->SOPT5 |= SIM_SOPT5_UART0RXSRC(1);
break;
case 1:
sim->SOPT5 &= ~SIM_SOPT5_UART1RXSRC_MASK
/* Select CMP0 as RX source for UART1*/;
sim->SOPT5 |= SIM_SOPT5_UART1RXSRC(1);
default:
/* Do not support source select for other UART module*/
return -1;
}
/* Setting Comparator module: Minus pin is DAC source, Plus pin is IrDA RX*/
cmp->MUXCR = CMP_MUXCR_MSEL(7) | CMP_MUXCR_PSEL(1);
/* Enable DAC input comparator */
cmp->DACCR = CMP_DACCR_DACEN_MASK | CMP_DACCR_VOSEL(BSP_SERIAL_IRDA_DAC_VREF)
| CMP_DACCR_VRSEL_MASK;
/* PTC7 as CPM IN function (Alt.0) */
pctl = (PORT_MemMapPtr) PORTC_BASE_PTR;
pctl->PCR[7] = PORT_PCR_MUX(0);
/* Enable Comparator module */
cmp->CR1 |= CMP_CR1_EN_MASK | CMP_CR1_COS_MASK
| CMP_CR1_OPE_MASK | CMP_CR1_PMODE_MASK;
}
else
{
switch (device_index) {
case 0:
sim->SOPT5 &= ~SIM_SOPT5_UART0RXSRC_MASK;
/* Select UART0_RX pin as RX source for UART0*/
sim->SOPT5 |= SIM_SOPT5_UART0RXSRC(0);
break;
case 1:
sim->SOPT5 &= ~SIM_SOPT5_UART1RXSRC_MASK
/* Select UART1_RX pin as RX source for UART1*/;
sim->SOPT5 |= SIM_SOPT5_UART1RXSRC(0);
default:
/* Do not support source select for other UART module*/
return -1;
}
/* Disable comparator module */
sim->SCGC4 &= ~SIM_SCGC4_CMP_MASK;
}
return MQX_OK;
}
/*******************************************************************************
* Enable Driver
*******************************************************************************/
void SnoozeCompare::enableDriver( void ) {
if ( mode == RUN_LP ) { return; }
if ( mode == VLPW || mode == VLPS ) {
IRQ_NUMBER_t IRQ_CMP;
switch (pin) {
case 11:
IRQ_CMP = IRQ_CMP0;
break;
#if defined(KINETISK)
case 9:
IRQ_CMP = IRQ_CMP1;
break;
case 4:
IRQ_CMP = IRQ_CMP2;
break;
#endif
default:
IRQ_CMP = IRQ_CMP;
return;
}
return_priority = NVIC_GET_PRIORITY( IRQ_CMP );//get current priority
int priority = nvic_execution_priority( );// get current priority
// if running from handler mode set priority higher than current handler
priority = ( priority < 256 ) && ( ( priority - 16 ) > 0 ) ? priority - 16 : 128;
NVIC_SET_PRIORITY( IRQ_CMP, priority );//set priority to new level
__disable_irq( );
return_cmp_irq = _VectorsRam[IRQ_CMP+16];// save prev isr
attachInterruptVector( IRQ_CMP, wakeupIsr );
__enable_irq( );
}
if ( SIM_SCGC4 & SIM_SCGC4_CMP ) SIM_SCGC4_clock_active = true;
else SIM_SCGC4 |= SIM_SCGC4_CMP;
CR0 = *cmpx_cr0;
CR1 = *cmpx_cr1;
SCR = *cmpx_scr;
FPR = *cmpx_fpr;
MUXCR = *cmpx_muxcr;
DACCR = *cmpx_daccr;
uint8_t _pin = 0;
*cmpx_cr0 = 0;
*cmpx_cr1 = 0;
*cmpx_scr = 0;
#if defined(__MKL26Z64__) || defined(__MK66FX1M0__)
if ( SIM_SCGC5 & SIM_SCGC5_LPTIMER ) SIM_SCGC5_clock_active = true;
else SIM_SCGC5 |= SIM_SCGC5_LPTIMER;
PSR = LPTMR0_PSR;
CMR = LPTMR0_CMR;
CSR = LPTMR0_CSR;
#endif
if ( pin == 11 ) {
if ( mode >= LLS ) llwu_configure_modules_mask( LLWU_CMP0_MOD );
return_core_pin_config[0] = CORE_PIN11_CONFIG;
CORE_PIN11_CONFIG = PORT_PCR_MUX( 0 );
_pin = 0x00;
}
else if ( pin == 4 ) {
#if defined(KINETISK)
if ( mode >= LLS ) llwu_configure_modules_mask( LLWU_CMP2_MOD );
return_core_pin_config[1] = CORE_PIN4_CONFIG;
CORE_PIN4_CONFIG = PORT_PCR_MUX( 0 );
_pin = 0x01;
#else
return;
#endif
}
else if ( pin == 9 ) {
#if defined(KINETISK)
if ( mode >= LLS ) llwu_configure_modules_mask( LLWU_CMP1_MOD );
return_core_pin_config[2] = CORE_PIN9_CONFIG;
CORE_PIN9_CONFIG = PORT_PCR_MUX( 0 );
_pin = 0x01;
#else
return;
#endif
}
// save if isr is already enabled and enable isr if not
if ( mode == VLPW || mode == VLPS ) {
IRQ_NUMBER_t IRQ_CMP;
switch (pin) {
case 11:
IRQ_CMP = IRQ_CMP0;
break;
#if defined(KINETISK)
case 9:
IRQ_CMP = IRQ_CMP1;
break;
case 4:
IRQ_CMP = IRQ_CMP2;
break;
#endif
default:
IRQ_CMP = IRQ_CMP;
return;
}
return_isr_enabled = NVIC_IS_ENABLED( IRQ_CMP );
if ( return_isr_enabled == 0 ) NVIC_ENABLE_IRQ( IRQ_CMP );
}
// setup compare
*cmpx_cr0 = CMP_CR0_FILTER_CNT( 0x07 );
if ( type == CHANGE ) *cmpx_scr = CMP_SCR_CFF | CMP_SCR_CFR | CMP_SCR_IEF | CMP_SCR_IER;
else if ( type == RISING || type == HIGH ) *cmpx_scr = CMP_SCR_CFF | CMP_SCR_CFR | CMP_SCR_IER;
else if ( type == FALLING || type == LOW ) *cmpx_scr = CMP_SCR_CFF | CMP_SCR_CFR | CMP_SCR_IEF;
else return;
uint8_t tap = ( threshold_crossing/0.0515625 ) - 1;
*cmpx_fpr = 0x00;
*cmpx_muxcr = CMP_MUXCR_MSEL( 0x07 ) | CMP_MUXCR_PSEL( _pin );
*cmpx_daccr = CMP_DACCR_DACEN | CMP_DACCR_VRSEL | CMP_DACCR_VOSEL( tap );
#if defined(__MKL26Z64__) || defined(__MK66FX1M0__)
// compare needs lptmr to operate in low power with LC, 3.6
*cmpx_cr1 = CMP_CR1_EN | CMP_CR1_TRIGM;
SIM_SCGC5 |= SIM_SCGC5_LPTIMER;
LPTMR0_CSR = 0;
LPTMR0_PSR = LPTMR_PSR_PBYP | LPTMR_PSR_PCS( LPTMR_LPO );//LPO Clock
LPTMR0_CMR = 1;
LPTMR0_CSR = LPTMR_CSR_TEN | LPTMR_CSR_TCF;
#else
*cmpx_cr1 = CMP_CR1_EN;
#endif
}
