vertex shader
VFETCH: ADDR(4) CNT(1) VALID_PIX
FETCH R0
EXP_DONE POS0, R0.XY01
EXT_DONE PARAM0, R0.ZW01
*/
uint32_t R600_video_vs[] =
{
/* 0 */
CF_DWORD0(ADDR(4)),
CF_DWORD1(POP_COUNT(0),
CF_CONST(0),
COND(SQ_CF_COND_ACTIVE),
/* I_COUNT(1),*/ 0,
CALL_COUNT(0),
END_OF_PROGRAM(0),
VALID_PIXEL_MODE(0),
CF_INST(SQ_CF_INST_VTX),
WHOLE_QUAD_MODE(0),
BARRIER(1)),
/* 1 */
CF_ALLOC_IMP_EXP_DWORD0(
ARRAY_BASE(CF_POS0),
TYPE(SQ_EXPORT_POS),
RW_GPR(0),
RW_REL(ABSOLUTE),
INDEX_GPR(0),
ELEM_SIZE(0)),
void
etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
const struct rs_state *rs)
{
memset(cs, 0, sizeof(*cs));
/* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2);
unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2);
/* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */
int source_multi = COND(rs->source_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
int dest_multi = COND(rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
/* Vivante RS needs widths to be a multiple of 16 or bad things
* happen, such as scribbing over memory, or the GPU hanging,
* even for non-tiled formats. As this is serious, use abort().
*/
if (rs->width & ETNA_RS_WIDTH_MASK)
abort();
/* TODO could just pre-generate command buffer, would simply submit to one memcpy */
cs->RS_CONFIG = VIVS_RS_CONFIG_SOURCE_FORMAT(rs->source_format) |
COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) |
COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) |
COND(rs->source_tiling & 1, VIVS_RS_CONFIG_SOURCE_TILED) |
VIVS_RS_CONFIG_DEST_FORMAT(rs->dest_format) |
COND(rs->dest_tiling & 1, VIVS_RS_CONFIG_DEST_TILED) |
COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) |
COND(rs->flip, VIVS_RS_CONFIG_FLIP);
cs->RS_SOURCE_STRIDE = (rs->source_stride << source_stride_shift) |
COND(rs->source_tiling & 2, VIVS_RS_SOURCE_STRIDE_TILING) |
COND(source_multi, VIVS_RS_SOURCE_STRIDE_MULTI);
/* Initially all pipes are set to the base address of the source and
* destination buffer respectively. This will be overridden below as
* necessary for the multi-pipe, multi-tiled case.
*/
for (unsigned pipe = 0; pipe < ctx->specs.pixel_pipes; ++pipe) {
cs->source[pipe].bo = rs->source;
cs->source[pipe].offset = rs->source_offset;
cs->source[pipe].flags = ETNA_RELOC_READ;
cs->dest[pipe].bo = rs->dest;
cs->dest[pipe].offset = rs->dest_offset;
cs->dest[pipe].flags = ETNA_RELOC_WRITE;
cs->RS_PIPE_OFFSET[pipe] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0);
}
cs->RS_DEST_STRIDE = (rs->dest_stride << dest_stride_shift) |
COND(rs->dest_tiling & 2, VIVS_RS_DEST_STRIDE_TILING) |
COND(dest_multi, VIVS_RS_DEST_STRIDE_MULTI);
if (ctx->specs.pixel_pipes == 1 || ctx->specs.single_buffer) {
cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height);
} else if (ctx->specs.pixel_pipes == 2) {
assert((rs->height & 7) == 0); /* GPU hangs happen if height not 8-aligned */
if (source_multi)
cs->source[1].offset = rs->source_offset + rs->source_stride * rs->source_padded_height / 2;
if (dest_multi)
cs->dest[1].offset = rs->dest_offset + rs->dest_stride * rs->dest_padded_height / 2;
cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2);
cs->RS_PIPE_OFFSET[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs->height / 2);
} else {
abort();
}
cs->RS_DITHER[0] = rs->dither[0];
cs->RS_DITHER[1] = rs->dither[1];
cs->RS_CLEAR_CONTROL = VIVS_RS_CLEAR_CONTROL_BITS(rs->clear_bits) | rs->clear_mode;
cs->RS_FILL_VALUE[0] = rs->clear_value[0];
cs->RS_FILL_VALUE[1] = rs->clear_value[1];
cs->RS_FILL_VALUE[2] = rs->clear_value[2];
cs->RS_FILL_VALUE[3] = rs->clear_value[3];
cs->RS_EXTRA_CONFIG = VIVS_RS_EXTRA_CONFIG_AA(rs->aa) |
VIVS_RS_EXTRA_CONFIG_ENDIAN(rs->endian_mode);
/* If source the same as destination, and the hardware supports this,
* do an in-place resolve to fill in unrendered tiles.
*/
if (ctx->specs.single_buffer && rs->source == rs->dest &&
rs->source_offset == rs->dest_offset &&
rs->source_format == rs->dest_format &&
rs->source_tiling == rs->dest_tiling &&
(rs->source_tiling & ETNA_LAYOUT_BIT_SUPER) &&
rs->source_stride == rs->dest_stride &&
!rs->downsample_x && !rs->downsample_y &&
!rs->swap_rb && !rs->flip &&
!rs->clear_mode && rs->source_padded_width) {
/* Total number of tiles (same as for autodisable) */
cs->RS_KICKER_INPLACE = rs->tile_count;
}
cs->source_ts_valid = rs->source_ts_valid;
}
void
fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit,
int nr, struct pipe_surface **bufs)
{
struct stage s[MAX_STAGES];
uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
uint32_t face_regid, coord_regid, zwcoord_regid;
int constmode;
int i, j, k;
debug_assert(nr <= ARRAY_SIZE(color_regid));
setup_stages(emit, s);
/* blob seems to always use constmode currently: */
constmode = 1;
pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
if (s[FS].v->color0_mrt) {
color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
} else {
color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
}
/* TODO get these dynamically: */
face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
/* we could probably divide this up into things that need to be
* emitted if frag-prog is dirty vs if vert-prog is dirty..
*/
OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
OUT_RING(ring, 0x00000003);
OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
/* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
* flush some caches? I think we only need to set those
* bits if we have updated const or shader..
*/
A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
0x3f3f000 | /* XXX */
A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(s[FS].v->pos_regid) |
0xfcfcfc00);
OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
OUT_RING(ring, A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
OUT_RING(ring, A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
OUT_RING(ring, A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
OUT_RING(ring, A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
OUT_RING(ring, 0x140010 | /* XXX */
COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
OUT_RING(ring, 0x7f | /* XXX */
COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
COND(s[VS].instrlen && s[FS].instrlen,
A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
OUT_RING(ring, A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
OUT_RING(ring, A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(s[FS].v->total_in, 4) / 4));
for (i = 0, j = -1; (i < 16) && (j < (int)s[FS].v->inputs_count); i++) {
uint32_t reg = 0;
OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
j = ir3_next_varying(s[FS].v, j);
if (j < s[FS].v->inputs_count) {
k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].slot);
reg |= A4XX_SP_VS_OUT_REG_A_REGID(s[VS].v->outputs[k].regid);
reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(s[FS].v->inputs[j].compmask);
}
j = ir3_next_varying(s[FS].v, j);
if (j < s[FS].v->inputs_count) {
k = ir3_find_output(s[VS].v, s[FS].v->inputs[j].slot);
reg |= A4XX_SP_VS_OUT_REG_B_REGID(s[VS].v->outputs[k].regid);
reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(s[FS].v->inputs[j].compmask);
}
OUT_RING(ring, reg);
}
for (i = 0, j = -1; (i < 8) && (j < (int)s[FS].v->inputs_count); i++) {
uint32_t reg = 0;
OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
j = ir3_next_varying(s[FS].v, j);
if (j < s[FS].v->inputs_count)
reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(s[FS].v->inputs[j].inloc);
j = ir3_next_varying(s[FS].v, j);
if (j < s[FS].v->inputs_count)
reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(s[FS].v->inputs[j].inloc);
j = ir3_next_varying(s[FS].v, j);
if (j < s[FS].v->inputs_count)
reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(s[FS].v->inputs[j].inloc);
j = ir3_next_varying(s[FS].v, j);
if (j < s[FS].v->inputs_count)
reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(s[FS].v->inputs[j].inloc);
OUT_RING(ring, reg);
}
OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
OUT_RING(ring, A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
A4XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
OUT_RING(ring, A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
0x80000000 | /* XXX */
COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
COND(s[FS].v->frag_coord, A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
OUT_RING(ring, A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
if (emit->key.binning_pass)
OUT_RING(ring, 0x00000000);
else
OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
OUT_RING(ring, A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
COND(s[FS].v->total_in > 0, A4XX_RB_RENDER_CONTROL2_VARYING) |
COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
COND(s[FS].v->frag_coord, A4XX_RB_RENDER_CONTROL2_XCOORD |
A4XX_RB_RENDER_CONTROL2_YCOORD |
// TODO enabling gl_FragCoord.z is causing lockups on 0ad (but seems
// to work everywhere else).
// A4XX_RB_RENDER_CONTROL2_ZCOORD |
A4XX_RB_RENDER_CONTROL2_WCOORD));
OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
OUT_RING(ring, A4XX_RB_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
OUT_RING(ring, A4XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr)) |
COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
for (i = 0; i < 8; i++) {
enum a4xx_color_fmt format = 0;
bool srgb = false;
if (i < nr) {
format = fd4_emit_format(bufs[i]);
if (bufs[i] && !emit->no_decode_srgb)
srgb = util_format_is_srgb(bufs[i]->format);
}
OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
COND(emit->key.half_precision,
A4XX_SP_FS_MRT_REG_HALF_PRECISION));
}
if (emit->key.binning_pass) {
OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) |
0x40000000 | /* XXX */
COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
OUT_RING(ring, 0x00000000);
} else {
uint32_t vinterp[8], vpsrepl[8];
memset(vinterp, 0, sizeof(vinterp));
memset(vpsrepl, 0, sizeof(vpsrepl));
/* looks like we need to do int varyings in the frag
* shader on a4xx (no flatshad reg? or a420.0 bug?):
*
* (sy)(ss)nop
* (sy)ldlv.u32 r0.x,l[r0.x], 1
* ldlv.u32 r0.y,l[r0.x+1], 1
* (ss)bary.f (ei)r63.x, 0, r0.x
* (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
* (rpt5)nop
* sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
*
* Possibly on later a4xx variants we'll be able to use
* something like the code below instead of workaround
* in the shader:
*/
/* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
/* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
* instead.. rather than -8 everywhere else..
*/
uint32_t inloc = s[FS].v->inputs[j].inloc - 8;
/* currently assuming varyings aligned to 4 (not
* packed):
*/
debug_assert((inloc % 4) == 0);
if ((s[FS].v->inputs[j].interpolate == INTERP_QUALIFIER_FLAT) ||
(s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
uint32_t loc = inloc;
for (i = 0; i < 4; i++, loc++) {
vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
//flatshade[loc / 32] |= 1 << (loc % 32);
}
}
gl_varying_slot slot = s[FS].v->inputs[j].slot;
/* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
if (slot >= VARYING_SLOT_VAR0) {
unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
/* Replace the .xy coordinates with S/T from the point sprite. Set
* interpolation bits for .zw such that they become .01
*/
if (emit->sprite_coord_enable & texmask) {
vpsrepl[inloc / 16] |= (emit->sprite_coord_mode ? 0x0d : 0x09)
<< ((inloc % 16) * 2);
vinterp[(inloc + 2) / 16] |= 2 << (((inloc + 2) % 16) * 2);
vinterp[(inloc + 3) / 16] |= 3 << (((inloc + 3) % 16) * 2);
}
}
}
OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
A4XX_VPC_ATTR_THRDASSIGN(1) |
COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
0x40000000 | /* XXX */
COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
for (i = 0; i < 8; i++)
OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
for (i = 0; i < 8; i++)
OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
}
if (s[VS].instrlen)
emit_shader(ring, s[VS].v);
if (!emit->key.binning_pass)
if (s[FS].instrlen)
emit_shader(ring, s[FS].v);
}
void fd_program_emit_state(struct fd_program *program, uint32_t first,
struct fd_parameters *uniforms, struct fd_parameters *attr,
struct fd_ringbuffer *ring)
{
struct fd_shader *vs = get_shader(program, FD_SHADER_VERTEX);
struct fd_shader *fs = get_shader(program, FD_SHADER_FRAGMENT);
struct ir3_shader_info *vsi = &vs->info;
struct ir3_shader_info *fsi = &fs->info;
uint32_t vsconstlen = constlen(vs);
uint32_t fsconstlen = constlen(fs);
uint32_t i, outloc;
uint32_t posregid = getpos(vs, "gl_Position", 0);
uint32_t psizeregid = getpos(vs, "gl_PointSize", (63 << 2));
uint32_t colorregid = getpos(fs, "gl_FragColor", 0);
uint32_t numvar = totalvar(fs);
assert (vs->ir->varyings_count == fs->ir->varyings_count);
OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE);
OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
OUT_RING(ring, 0x00000000); /* HLSQ_CONTROL_3_REG */
OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vsconstlen) |
A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(instrlen(vs)));
OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fsconstlen) |
A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(instrlen(fs)));
OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(0) |
A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
// XXX "resolve" (?) bit set on gmem->mem pass..
COND(!uniforms, A3XX_SP_SP_CTRL_REG_RESOLVE) |
// XXX sometimes 0, sometimes 1:
A3XX_SP_SP_CTRL_REG_LOMODE(1));
/* emit unknown sequence of writes to 0x0ec4/0x0ec8 that the blob
* emits as part of the program state (it seems)..
*/
for (i = 0; i < 6; i++) {
OUT_PKT0(ring, REG_A3XX_SP_PERFCOUNTER0_SELECT, 1);
OUT_RING(ring, 0x00000000); /* SP_PERFCOUNTER0_SELECT */
OUT_PKT0(ring, REG_A3XX_SP_PERFCOUNTER3_SELECT, 1);
OUT_RING(ring, 0x00000000); /* SP_PERFCOUNTER3_SELECT */
}
OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(instrlen(vs)));
OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
A3XX_SP_VS_CTRL_REG0_LENGTH(instrlen(vs)));
OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vsconstlen) |
A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(totalattr(vs)) |
A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(max(vsi->max_const, 0)));
OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(posregid) |
A3XX_SP_VS_PARAM_REG_PSIZEREGID(psizeregid) |
A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fs->ir->varyings_count));
for (i = 0; i < vs->ir->varyings_count; ) {
struct ir3_varying *v;
uint32_t reg = 0;
OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i/2), 1);
v = vs->ir->varyings[i++];
if (v) {
reg |= A3XX_SP_VS_OUT_REG_A_REGID(v->rstart->num);
reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(regmask(v->num));
}
v = vs->ir->varyings[i++];
if (v) {
reg |= A3XX_SP_VS_OUT_REG_B_REGID(v->rstart->num);
reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(regmask(v->num));
}
OUT_RING(ring, reg);
}
outloc = 8; /* I assume 0 and 4 are gl_Position/gl_PointSize? */
for (i = 0; i < vs->ir->varyings_count; ) {
struct ir3_varying *v;
uint32_t reg = 0;
OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i/4), 1);
/* note: if we supported anything other than vec4 varyings, we'd
* actually be incrementing outloc by the actual varying size in
* units of scalar registers (ie. vec3 -> 3)
*/
v = vs->ir->varyings[i++];
if (v) {
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(outloc);
outloc += v->num;
}
v = vs->ir->varyings[i++];
if (v) {
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(outloc);
outloc += v->num;
}
v = vs->ir->varyings[i++];
if (v) {
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(outloc);
outloc += v->num;
}
v = vs->ir->varyings[i++];
if (v) {
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(outloc);
outloc += v->num;
}
OUT_RING(ring, reg);
}
// TODO SP_VS_OBJ_OFFSET_REG / SP_VS_OBJ_START_REG
OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(instrlen(fs)));
OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER) |
A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
COND(fs->ir->samplers_count > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
A3XX_SP_FS_CTRL_REG0_LENGTH(instrlen(fs)));
OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fsconstlen) |
A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(0) |
A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(max(fsi->max_const, 0)) |
A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
// TODO SP_FS_OBJ_OFFSET_REG / SP_FS_OBJ_START_REG
OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
OUT_RING(ring, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
OUT_RING(ring, 0x00000000); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
OUT_RING(ring, 0x00000000); /* SP_FS_OUTPUT_REG */
OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(colorregid) | /* SP_FS_MRT[0].REG */
A3XX_SP_FS_MRT_REG_HALF_PRECISION);
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0)); /* SP_FS_MRT[1].REG */
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0)); /* SP_FS_MRT[2].REG */
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0)); /* SP_FS_MRT[3].REG */
OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(numvar) |
A3XX_VPC_ATTR_THRDASSIGN(1) |
A3XX_VPC_ATTR_LMSIZE(1));
OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(numvar) |
A3XX_VPC_PACK_NUMNONPOSVSVAR(numvar));
OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
OUT_RING(ring, 0x00000000); /* VPC_VARYING_INTERP[0].MODE */
OUT_RING(ring, 0x00000000); /* VPC_VARYING_INTERP[1].MODE */
OUT_RING(ring, 0x00000000); /* VPC_VARYING_INTERP[2].MODE */
OUT_RING(ring, 0x00000000); /* VPC_VARYING_INTERP[3].MODE */
OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[0].MODE */
OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[1].MODE */
OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[2].MODE */
OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[3].MODE */
OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
emit_shader(ring, vs, SB_VERT_SHADER);
OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
emit_shader(ring, fs, SB_FRAG_SHADER);
OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(totalattr(vs)) |
A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(vs->ir->attributes_count) |
A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(vs->ir->attributes_count));
OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
A3XX_VFD_CONTROL_1_REGID4VTX(63 << 2) |
A3XX_VFD_CONTROL_1_REGID4INST(63 << 2));
emit_vtx_fetch(ring, vs, attr, first);
/* we have this sometimes, not others.. perhaps we could be clever
* and figure out actually when we need to invalidate cache:
*/
OUT_PKT0(ring, REG_A3XX_UCHE_CACHE_INVALIDATE0_REG, 2);
OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(INVALIDATE) |
A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE);
/* for RB_RESOLVE_PASS, I think the consts are not needed: */
if (uniforms) {
emit_uniconst(ring, vs, uniforms, SB_VERT_SHADER);
emit_uniconst(ring, fs, uniforms, SB_FRAG_SHADER);
}
}
int main(int argc, char **argv)
{
long count;
static unsigned char buf[BUFSIZE];
static DES_cblock key ={0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0};
static DES_cblock key2={0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12};
static DES_cblock key3={0x56,0x78,0x9a,0xbc,0xde,0xf0,0x12,0x34};
DES_key_schedule sch,sch2,sch3;
double a,b,c,d,e;
#ifndef SIGALRM
long ca,cb,cc,cd,ce;
#endif
#ifndef TIMES
TINYCLR_SSL_PRINTF("To get the most accurate results, try to run this\n");
TINYCLR_SSL_PRINTF("program when this computer is idle.\n");
#endif
DES_set_key_unchecked(&key2,&sch2);
DES_set_key_unchecked(&key3,&sch3);
#ifndef SIGALRM
TINYCLR_SSL_PRINTF("First we calculate the approximate speed ...\n");
DES_set_key_unchecked(&key,&sch);
count=10;
do {
long i;
DES_LONG data[2];
count*=2;
Time_F(START);
for (i=count; i; i--)
DES_encrypt1(data,&sch,DES_ENCRYPT);
d=Time_F(STOP);
} while (d < 3.0);
ca=count;
cb=count*3;
cc=count*3*8/BUFSIZE+1;
cd=count*8/BUFSIZE+1;
ce=count/20+1;
TINYCLR_SSL_PRINTF("Doing set_key %ld times\n",ca);
#define COND(d) (count != (d))
#define COUNT(d) (d)
#else
#define COND(c) (run)
#define COUNT(d) (count)
signal(SIGALRM,sig_done);
TINYCLR_SSL_PRINTF("Doing set_key for 10 seconds\n");
alarm(10);
#endif
Time_F(START);
for (count=0,run=1; COND(ca); count++)
DES_set_key_unchecked(&key,&sch);
d=Time_F(STOP);
TINYCLR_SSL_PRINTF("%ld set_key's in %.2f seconds\n",count,d);
a=((double)COUNT(ca))/d;
#ifdef SIGALRM
TINYCLR_SSL_PRINTF("Doing DES_encrypt's for 10 seconds\n");
alarm(10);
#else
TINYCLR_SSL_PRINTF("Doing DES_encrypt %ld times\n",cb);
#endif
Time_F(START);
for (count=0,run=1; COND(cb); count++)
{
DES_LONG data[2];
DES_encrypt1(data,&sch,DES_ENCRYPT);
}
d=Time_F(STOP);
TINYCLR_SSL_PRINTF("%ld DES_encrypt's in %.2f second\n",count,d);
b=((double)COUNT(cb)*8)/d;
#ifdef SIGALRM
TINYCLR_SSL_PRINTF("Doing DES_cbc_encrypt on %ld byte blocks for 10 seconds\n",
BUFSIZE);
alarm(10);
#else
TINYCLR_SSL_PRINTF("Doing DES_cbc_encrypt %ld times on %ld byte blocks\n",cc,
BUFSIZE);
#endif
Time_F(START);
for (count=0,run=1; COND(cc); count++)
DES_ncbc_encrypt(buf,buf,BUFSIZE,&sch,
&key,DES_ENCRYPT);
d=Time_F(STOP);
TINYCLR_SSL_PRINTF("%ld DES_cbc_encrypt's of %ld byte blocks in %.2f second\n",
count,BUFSIZE,d);
c=((double)COUNT(cc)*BUFSIZE)/d;
#ifdef SIGALRM
TINYCLR_SSL_PRINTF("Doing DES_ede_cbc_encrypt on %ld byte blocks for 10 seconds\n",
BUFSIZE);
alarm(10);
#else
TINYCLR_SSL_PRINTF("Doing DES_ede_cbc_encrypt %ld times on %ld byte blocks\n",cd,
BUFSIZE);
#endif
Time_F(START);
for (count=0,run=1; COND(cd); count++)
DES_ede3_cbc_encrypt(buf,buf,BUFSIZE,
&sch,
&sch2,
&sch3,
&key,
DES_ENCRYPT);
d=Time_F(STOP);
TINYCLR_SSL_PRINTF("%ld DES_ede_cbc_encrypt's of %ld byte blocks in %.2f second\n",
count,BUFSIZE,d);
d=((double)COUNT(cd)*BUFSIZE)/d;
#ifdef SIGALRM
TINYCLR_SSL_PRINTF("Doing crypt for 10 seconds\n");
alarm(10);
#else
TINYCLR_SSL_PRINTF("Doing crypt %ld times\n",ce);
#endif
Time_F(START);
for (count=0,run=1; COND(ce); count++)
crypt("testing1","ef");
e=Time_F(STOP);
TINYCLR_SSL_PRINTF("%ld crypts in %.2f second\n",count,e);
e=((double)COUNT(ce))/e;
TINYCLR_SSL_PRINTF("set_key per sec = %12.2f (%9.3fuS)\n",a,1.0e6/a);
TINYCLR_SSL_PRINTF("DES raw ecb bytes per sec = %12.2f (%9.3fuS)\n",b,8.0e6/b);
TINYCLR_SSL_PRINTF("DES cbc bytes per sec = %12.2f (%9.3fuS)\n",c,8.0e6/c);
TINYCLR_SSL_PRINTF("DES ede cbc bytes per sec = %12.2f (%9.3fuS)\n",d,8.0e6/d);
TINYCLR_SSL_PRINTF("crypt per sec = %12.2f (%9.3fuS)\n",e,1.0e6/e);
TINYCLR_SSL_EXIT(0);
#if defined(LINT) || defined(OPENSSL_SYS_MSDOS)
return(0);
#endif
}
void
fd5_program_emit(struct fd_ringbuffer *ring, struct fd5_emit *emit,
int nr, struct pipe_surface **bufs)
{
struct stage s[MAX_STAGES];
uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
uint32_t face_regid, coord_regid, zwcoord_regid;
uint32_t vcoord_regid, vertex_regid, instance_regid;
int i, j;
debug_assert(nr <= ARRAY_SIZE(color_regid));
if (emit->key.binning_pass)
nr = 0;
setup_stages(emit, s);
pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
vertex_regid = ir3_find_output_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
instance_regid = ir3_find_output_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
if (s[FS].v->color0_mrt) {
color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
} else {
color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
}
/* TODO get these dynamically: */
face_regid = s[FS].v->frag_face ? regid(0,0) : regid(63,0);
coord_regid = s[FS].v->frag_coord ? regid(0,0) : regid(63,0);
zwcoord_regid = s[FS].v->frag_coord ? regid(0,2) : regid(63,0);
vcoord_regid = (s[FS].v->total_in > 0) ? regid(0,0) : regid(63,0);
/* we could probably divide this up into things that need to be
* emitted if frag-prog is dirty vs if vert-prog is dirty..
*/
OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONTROL_REG, 5);
OUT_RING(ring, A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff) |
COND(s[VS].v, A5XX_HLSQ_VS_CONTROL_REG_ENABLED));
OUT_RING(ring, A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff) |
COND(s[FS].v, A5XX_HLSQ_FS_CONTROL_REG_ENABLED));
OUT_RING(ring, A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff) |
COND(s[HS].v, A5XX_HLSQ_HS_CONTROL_REG_ENABLED));
OUT_RING(ring, A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff) |
COND(s[DS].v, A5XX_HLSQ_DS_CONTROL_REG_ENABLED));
OUT_RING(ring, A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff) |
COND(s[GS].v, A5XX_HLSQ_GS_CONTROL_REG_ENABLED));
OUT_PKT4(ring, REG_A5XX_HLSQ_CS_CONFIG, 1);
OUT_RING(ring, 0x00000000);
OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CNTL, 5);
OUT_RING(ring, A5XX_HLSQ_VS_CNTL_INSTRLEN(s[VS].instrlen));
OUT_RING(ring, A5XX_HLSQ_FS_CNTL_INSTRLEN(s[FS].instrlen));
OUT_RING(ring, A5XX_HLSQ_HS_CNTL_INSTRLEN(s[HS].instrlen));
OUT_RING(ring, A5XX_HLSQ_DS_CNTL_INSTRLEN(s[DS].instrlen));
OUT_RING(ring, A5XX_HLSQ_GS_CNTL_INSTRLEN(s[GS].instrlen));
OUT_PKT4(ring, REG_A5XX_SP_VS_CONTROL_REG, 5);
OUT_RING(ring, A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff) |
COND(s[VS].v, A5XX_SP_VS_CONTROL_REG_ENABLED));
OUT_RING(ring, A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff) |
COND(s[FS].v, A5XX_SP_FS_CONTROL_REG_ENABLED));
OUT_RING(ring, A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff) |
COND(s[HS].v, A5XX_SP_HS_CONTROL_REG_ENABLED));
OUT_RING(ring, A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff) |
COND(s[DS].v, A5XX_SP_DS_CONTROL_REG_ENABLED));
OUT_RING(ring, A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff) |
COND(s[GS].v, A5XX_SP_GS_CONTROL_REG_ENABLED));
OUT_PKT4(ring, REG_A5XX_SP_CS_CONFIG, 1);
OUT_RING(ring, 0x00000000);
OUT_PKT4(ring, REG_A5XX_HLSQ_VS_CONSTLEN, 2);
OUT_RING(ring, s[VS].constlen); /* HLSQ_VS_CONSTLEN */
OUT_RING(ring, s[VS].instrlen); /* HLSQ_VS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_FS_CONSTLEN, 2);
OUT_RING(ring, s[FS].constlen); /* HLSQ_FS_CONSTLEN */
OUT_RING(ring, s[FS].instrlen); /* HLSQ_FS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_HS_CONSTLEN, 2);
OUT_RING(ring, s[HS].constlen); /* HLSQ_HS_CONSTLEN */
OUT_RING(ring, s[HS].instrlen); /* HLSQ_HS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_DS_CONSTLEN, 2);
OUT_RING(ring, s[DS].constlen); /* HLSQ_DS_CONSTLEN */
OUT_RING(ring, s[DS].instrlen); /* HLSQ_DS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_GS_CONSTLEN, 2);
OUT_RING(ring, s[GS].constlen); /* HLSQ_GS_CONSTLEN */
OUT_RING(ring, s[GS].instrlen); /* HLSQ_GS_INSTRLEN */
OUT_PKT4(ring, REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3, 2);
OUT_RING(ring, 0x00000000); /* HLSQ_CONTEXT_SWITCH_CS_SW_3 */
OUT_RING(ring, 0x00000000); /* HLSQ_CONTEXT_SWITCH_CS_SW_4 */
OUT_PKT4(ring, REG_A5XX_SP_VS_CTRL_REG0, 1);
OUT_RING(ring, A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
0x6 | /* XXX seems to be always set? */
A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
COND(s[VS].v->has_samp, A5XX_SP_VS_CTRL_REG0_PIXLODENABLE));
struct ir3_shader_linkage l = {0};
ir3_link_shaders(&l, s[VS].v, s[FS].v);
BITSET_DECLARE(varbs, 128) = {0};
uint32_t *varmask = (uint32_t *)varbs;
for (i = 0; i < l.cnt; i++)
for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
BITSET_SET(varbs, l.var[i].loc + j);
OUT_PKT4(ring, REG_A5XX_VPC_VAR_DISABLE(0), 4);
OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
/* a5xx appends pos/psize to end of the linkage map: */
if (pos_regid != regid(63,0))
ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
if (psize_regid != regid(63,0))
ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
uint32_t reg = 0;
OUT_PKT4(ring, REG_A5XX_SP_VS_OUT_REG(i), 1);
reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
reg |= A5XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
j++;
reg |= A5XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
reg |= A5XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
j++;
OUT_RING(ring, reg);
}
for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
uint32_t reg = 0;
OUT_PKT4(ring, REG_A5XX_SP_VS_VPC_DST_REG(i), 1);
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
reg |= A5XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
OUT_RING(ring, reg);
}
OUT_PKT4(ring, REG_A5XX_SP_VS_OBJ_START_LO, 2);
OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
if (s[VS].instrlen)
emit_shader(ring, s[VS].v);
// TODO depending on other bits in this reg (if any) set somewhere else?
OUT_PKT4(ring, REG_A5XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, COND(s[VS].v->writes_psize, A5XX_PC_PRIM_VTX_CNTL_PSIZE));
if (emit->key.binning_pass) {
OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
} else {
uint32_t stride_in_vpc = align(s[FS].v->total_in, 4) + 4;
if (s[VS].v->writes_psize)
stride_in_vpc++;
// TODO if some of these other bits depend on something other than
// program state we should probably move these next three regs:
OUT_PKT4(ring, REG_A5XX_SP_PRIMITIVE_CNTL, 1);
OUT_RING(ring, A5XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
OUT_PKT4(ring, REG_A5XX_VPC_CNTL_0, 1);
OUT_RING(ring, A5XX_VPC_CNTL_0_STRIDE_IN_VPC(stride_in_vpc) |
COND(s[FS].v->total_in > 0, A5XX_VPC_CNTL_0_VARYING) |
0x10000); // XXX
OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);
OUT_RING(ring, A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(stride_in_vpc) |
0x400); // XXX
OUT_PKT4(ring, REG_A5XX_SP_FS_OBJ_START_LO, 2);
OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
}
OUT_PKT4(ring, REG_A5XX_HLSQ_CONTROL_0_REG, 5);
OUT_RING(ring, 0x00000881); /* XXX HLSQ_CONTROL_0 */
OUT_RING(ring, A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(63));
OUT_RING(ring, A5XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
0xfcfcfc00); /* XXX */
OUT_RING(ring, A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
0xfcfcfc00); /* XXX */
OUT_RING(ring, A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
0x0000fcfc); /* XXX */
OUT_PKT4(ring, REG_A5XX_SP_FS_CTRL_REG0, 1);
OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_SP_FS_CTRL_REG0_VARYING) |
0x4000e | /* XXX set pretty much everywhere */
A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
COND(s[FS].v->has_samp, A5XX_SP_FS_CTRL_REG0_PIXLODENABLE));
OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);
OUT_RING(ring, 0x020fffff); /* XXX */
OUT_PKT4(ring, REG_A5XX_VPC_GS_SIV_CNTL, 1);
OUT_RING(ring, 0x0000ffff); /* XXX */
OUT_PKT4(ring, REG_A5XX_SP_SP_CNTL, 1);
OUT_RING(ring, 0x00000010); /* XXX */
OUT_PKT4(ring, REG_A5XX_GRAS_CNTL, 1);
OUT_RING(ring, COND(s[FS].v->total_in > 0, A5XX_GRAS_CNTL_VARYING) |
COND(s[FS].v->frag_coord, A5XX_GRAS_CNTL_XCOORD |
A5XX_GRAS_CNTL_YCOORD |
A5XX_GRAS_CNTL_ZCOORD |
A5XX_GRAS_CNTL_WCOORD |
A5XX_GRAS_CNTL_UNK3) |
COND(s[FS].v->frag_face, A5XX_GRAS_CNTL_UNK3));
OUT_PKT4(ring, REG_A5XX_RB_RENDER_CONTROL0, 3);
OUT_RING(ring,
COND(s[FS].v->total_in > 0, A5XX_RB_RENDER_CONTROL0_VARYING) |
COND(s[FS].v->frag_coord, A5XX_RB_RENDER_CONTROL0_XCOORD |
A5XX_RB_RENDER_CONTROL0_YCOORD |
A5XX_RB_RENDER_CONTROL0_ZCOORD |
A5XX_RB_RENDER_CONTROL0_WCOORD |
A5XX_RB_RENDER_CONTROL0_UNK3) |
COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL0_UNK3));
OUT_RING(ring,
COND(s[FS].v->frag_face, A5XX_RB_RENDER_CONTROL1_FACENESS));
OUT_RING(ring, A5XX_RB_FS_OUTPUT_CNTL_MRT(nr) |
COND(s[FS].v->writes_pos, A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z));
OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 9);
OUT_RING(ring, A5XX_SP_FS_OUTPUT_CNTL_MRT(nr) |
A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(regid(63, 0)));
for (i = 0; i < 8; i++) {
OUT_RING(ring, A5XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
COND(emit->key.half_precision,
A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
}
if (emit->key.binning_pass) {
OUT_PKT4(ring, REG_A5XX_VPC_PACK, 1);
OUT_RING(ring, A5XX_VPC_PACK_NUMNONPOSVAR(0));
} else {
uint32_t vinterp[8], vpsrepl[8];
memset(vinterp, 0, sizeof(vinterp));
memset(vpsrepl, 0, sizeof(vpsrepl));
/* looks like we need to do int varyings in the frag
* shader on a5xx (no flatshad reg? or a420.0 bug?):
*
* (sy)(ss)nop
* (sy)ldlv.u32 r0.x,l[r0.x], 1
* ldlv.u32 r0.y,l[r0.x+1], 1
* (ss)bary.f (ei)r63.x, 0, r0.x
* (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
* (rpt5)nop
* sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
*
* Possibly on later a5xx variants we'll be able to use
* something like the code below instead of workaround
* in the shader:
*/
/* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
/* NOTE: varyings are packed, so if compmask is 0xb
* then first, third, and fourth component occupy
* three consecutive varying slots:
*/
unsigned compmask = s[FS].v->inputs[j].compmask;
uint32_t inloc = s[FS].v->inputs[j].inloc;
if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
(s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
uint32_t loc = inloc;
for (i = 0; i < 4; i++) {
if (compmask & (1 << i)) {
vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
//flatshade[loc / 32] |= 1 << (loc % 32);
loc++;
}
}
}
gl_varying_slot slot = s[FS].v->inputs[j].slot;
/* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
if (slot >= VARYING_SLOT_VAR0) {
unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
/* Replace the .xy coordinates with S/T from the point sprite. Set
* interpolation bits for .zw such that they become .01
*/
if (emit->sprite_coord_enable & texmask) {
/* mask is two 2-bit fields, where:
* '01' -> S
* '10' -> T
* '11' -> 1 - T (flip mode)
*/
unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
uint32_t loc = inloc;
if (compmask & 0x1) {
vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
loc++;
}
if (compmask & 0x2) {
vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
loc++;
}
if (compmask & 0x4) {
/* .z <- 0.0f */
vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
loc++;
}
if (compmask & 0x8) {
/* .w <- 1.0f */
vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
loc++;
}
}
void
fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit)
{
const struct ir3_shader_variant *vp, *fp;
const struct ir3_info *vsi, *fsi;
enum a3xx_instrbuffermode fpbuffer, vpbuffer;
uint32_t fpbuffersz, vpbuffersz, fsoff;
uint32_t pos_regid, posz_regid, psize_regid, color_regid;
int constmode;
int i, j, k;
vp = fd3_emit_get_vp(emit);
if (emit->key.binning_pass) {
/* use dummy stateobj to simplify binning vs non-binning: */
static const struct ir3_shader_variant binning_fp = {};
fp = &binning_fp;
} else {
fp = fd3_emit_get_fp(emit);
}
vsi = &vp->info;
fsi = &fp->info;
fpbuffer = BUFFER;
vpbuffer = BUFFER;
fpbuffersz = fp->instrlen;
vpbuffersz = vp->instrlen;
/*
* Decide whether to use BUFFER or CACHE mode for VS and FS. It
* appears like 256 is the hard limit, but when the combined size
* exceeds 128 then blob will try to keep FS in BUFFER mode and
* switch to CACHE for VS until VS is too large. The blob seems
* to switch FS out of BUFFER mode at slightly under 128. But
* a bit fuzzy on the decision tree, so use slightly conservative
* limits.
*
* TODO check if these thresholds for BUFFER vs CACHE mode are the
* same for all a3xx or whether we need to consider the gpuid
*/
if ((fpbuffersz + vpbuffersz) > 128) {
if (fpbuffersz < 112) {
/* FP:BUFFER VP:CACHE */
vpbuffer = CACHE;
vpbuffersz = 256 - fpbuffersz;
} else if (vpbuffersz < 112) {
/* FP:CACHE VP:BUFFER */
fpbuffer = CACHE;
fpbuffersz = 256 - vpbuffersz;
} else {
/* FP:CACHE VP:CACHE */
vpbuffer = fpbuffer = CACHE;
vpbuffersz = fpbuffersz = 192;
}
}
if (fpbuffer == BUFFER) {
fsoff = 128 - fpbuffersz;
} else {
fsoff = 256 - fpbuffersz;
}
/* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
pos_regid = find_output_regid(vp,
ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
posz_regid = find_output_regid(fp,
ir3_semantic_name(TGSI_SEMANTIC_POSITION, 0));
psize_regid = find_output_regid(vp,
ir3_semantic_name(TGSI_SEMANTIC_PSIZE, 0));
color_regid = find_output_regid(fp,
ir3_semantic_name(TGSI_SEMANTIC_COLOR, 0));
/* we could probably divide this up into things that need to be
* emitted if frag-prog is dirty vs if vert-prog is dirty..
*/
OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
/* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
* flush some caches? I think we only need to set those
* bits if we have updated const or shader..
*/
A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_ZWCOORD));
OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
A3XX_SP_SP_CTRL_REG_L0MODE(0));
OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
A3XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
COND(vp->has_samp, A3XX_SP_VS_CTRL_REG0_PIXLODENABLE) |
A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(align(fp->total_in, 4) / 4));
for (i = 0, j = -1; (i < 8) && (j < (int)fp->inputs_count); i++) {
uint32_t reg = 0;
OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
j = next_varying(fp, j);
if (j < fp->inputs_count) {
k = find_output(vp, fp->inputs[j].semantic);
reg |= A3XX_SP_VS_OUT_REG_A_REGID(vp->outputs[k].regid);
reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(fp->inputs[j].compmask);
}
j = next_varying(fp, j);
if (j < fp->inputs_count) {
k = find_output(vp, fp->inputs[j].semantic);
reg |= A3XX_SP_VS_OUT_REG_B_REGID(vp->outputs[k].regid);
reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(fp->inputs[j].compmask);
}
OUT_RING(ring, reg);
}
for (i = 0, j = -1; (i < 4) && (j < (int)fp->inputs_count); i++) {
uint32_t reg = 0;
OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
j = next_varying(fp, j);
if (j < fp->inputs_count)
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(fp->inputs[j].inloc);
j = next_varying(fp, j);
if (j < fp->inputs_count)
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(fp->inputs[j].inloc);
j = next_varying(fp, j);
if (j < fp->inputs_count)
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(fp->inputs[j].inloc);
j = next_varying(fp, j);
if (j < fp->inputs_count)
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(fp->inputs[j].inloc);
OUT_RING(ring, reg);
}
OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
if (emit->key.binning_pass) {
OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
OUT_RING(ring, 0x00000000);
OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
OUT_RING(ring, 0x00000000);
OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
} else {
OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
MAX2(128, vp->constlen)) |
A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
}
OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
if (fp->writes_pos) {
OUT_RING(ring, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE |
A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
} else {
OUT_RING(ring, 0x00000000);
}
OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(color_regid) |
COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION));
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
OUT_RING(ring, A3XX_SP_FS_MRT_REG_REGID(0));
if (emit->key.binning_pass) {
OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
A3XX_VPC_ATTR_LMSIZE(1) |
COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
OUT_RING(ring, 0x00000000);
} else {
uint32_t vinterp[4] = {0}, flatshade[2] = {0};
/* figure out VARYING_INTERP / FLAT_SHAD register values: */
for (j = -1; (j = next_varying(fp, j)) < (int)fp->inputs_count; ) {
uint32_t interp = fp->inputs[j].interpolate;
if ((interp == TGSI_INTERPOLATE_CONSTANT) ||
((interp == TGSI_INTERPOLATE_COLOR) && emit->rasterflat)) {
/* TODO might be cleaner to just +8 in SP_VS_VPC_DST_REG
* instead.. rather than -8 everywhere else..
*/
uint32_t loc = fp->inputs[j].inloc - 8;
/* currently assuming varyings aligned to 4 (not
* packed):
*/
debug_assert((loc % 4) == 0);
for (i = 0; i < 4; i++, loc++) {
vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
flatshade[loc / 32] |= 1 << (loc % 32);
}
}
}
OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
A3XX_VPC_ATTR_THRDASSIGN(1) |
A3XX_VPC_ATTR_LMSIZE(1) |
COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
OUT_RING(ring, vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
OUT_RING(ring, vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
OUT_RING(ring, vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
OUT_RING(ring, vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
OUT_RING(ring, fp->shader->vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
OUT_RING(ring, fp->shader->vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
OUT_RING(ring, fp->shader->vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
OUT_RING(ring, fp->shader->vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
OUT_RING(ring, flatshade[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
OUT_RING(ring, flatshade[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
}
OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
OUT_RING(ring, A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(252));
if (vpbuffer == BUFFER)
emit_shader(ring, vp);
OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
if (!emit->key.binning_pass) {
if (fpbuffer == BUFFER)
emit_shader(ring, fp);
OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
}
}
int main(int argc, char **argv)
{
long count;
static unsigned char buf[BUFSIZE];
static unsigned char key[] ={
0x12,0x34,0x56,0x78,0x9a,0xbc,0xde,0xf0,
0xfe,0xdc,0xba,0x98,0x76,0x54,0x32,0x10,
};
RC5_32_KEY sch;
double a,b,c,d;
#ifndef SIGALRM
long ca,cb,cc;
#endif
#ifndef TIMES
printf("To get the most accurate results, try to run this\n");
printf("program when this computer is idle.\n");
#endif
#ifndef SIGALRM
printf("First we calculate the approximate speed ...\n");
RC5_32_set_key(&sch,16,key,12);
count=10;
do {
long i;
unsigned long data[2];
count*=2;
Time_F(START);
for (i=count; i; i--)
RC5_32_encrypt(data,&sch);
d=Time_F(STOP);
} while (d < 3.0);
ca=count/512;
cb=count;
cc=count*8/BUFSIZE+1;
printf("Doing RC5_32_set_key %ld times\n",ca);
#define COND(d) (count != (d))
#define COUNT(d) (d)
#else
#define COND(c) (run)
#define COUNT(d) (count)
signal(SIGALRM,sig_done);
printf("Doing RC5_32_set_key for 10 seconds\n");
alarm(10);
#endif
Time_F(START);
for (count=0,run=1; COND(ca); count+=4)
{
RC5_32_set_key(&sch,16,key,12);
RC5_32_set_key(&sch,16,key,12);
RC5_32_set_key(&sch,16,key,12);
RC5_32_set_key(&sch,16,key,12);
}
d=Time_F(STOP);
printf("%ld RC5_32_set_key's in %.2f seconds\n",count,d);
a=((double)COUNT(ca))/d;
#ifdef SIGALRM
printf("Doing RC5_32_encrypt's for 10 seconds\n");
alarm(10);
#else
printf("Doing RC5_32_encrypt %ld times\n",cb);
#endif
Time_F(START);
for (count=0,run=1; COND(cb); count+=4)
{
unsigned long data[2];
RC5_32_encrypt(data,&sch);
RC5_32_encrypt(data,&sch);
RC5_32_encrypt(data,&sch);
RC5_32_encrypt(data,&sch);
}
d=Time_F(STOP);
printf("%ld RC5_32_encrypt's in %.2f second\n",count,d);
b=((double)COUNT(cb)*8)/d;
#ifdef SIGALRM
printf("Doing RC5_32_cbc_encrypt on %ld byte blocks for 10 seconds\n",
BUFSIZE);
alarm(10);
#else
printf("Doing RC5_32_cbc_encrypt %ld times on %ld byte blocks\n",cc,
BUFSIZE);
#endif
Time_F(START);
for (count=0,run=1; COND(cc); count++)
RC5_32_cbc_encrypt(buf,buf,BUFSIZE,&sch,
&(key[0]),RC5_ENCRYPT);
d=Time_F(STOP);
printf("%ld RC5_32_cbc_encrypt's of %ld byte blocks in %.2f second\n",
count,BUFSIZE,d);
c=((double)COUNT(cc)*BUFSIZE)/d;
printf("RC5_32/12/16 set_key per sec = %12.2f (%9.3fuS)\n",a,1.0e6/a);
printf("RC5_32/12/16 raw ecb bytes per sec = %12.2f (%9.3fuS)\n",b,8.0e6/b);
printf("RC5_32/12/16 cbc bytes per sec = %12.2f (%9.3fuS)\n",c,8.0e6/c);
exit(0);
#if defined(LINT) || defined(OPENSSL_SYS_MSDOS)
return(0);
#endif
}
static int mdp4_plane_mode_set(struct drm_plane *plane,
struct drm_crtc *crtc, struct drm_framebuffer *fb,
int crtc_x, int crtc_y,
unsigned int crtc_w, unsigned int crtc_h,
uint32_t src_x, uint32_t src_y,
uint32_t src_w, uint32_t src_h)
{
struct drm_device *dev = plane->dev;
struct mdp4_plane *mdp4_plane = to_mdp4_plane(plane);
struct mdp4_kms *mdp4_kms = get_kms(plane);
enum mdp4_pipe pipe = mdp4_plane->pipe;
const struct mdp_format *format;
uint32_t op_mode = 0;
uint32_t phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
uint32_t phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
enum mdp4_frame_format frame_type;
if (!(crtc && fb)) {
DBG("%s: disabled!", mdp4_plane->name);
return 0;
}
frame_type = mdp4_get_frame_format(fb);
/* src values are in Q16 fixed point, convert to integer: */
src_x = src_x >> 16;
src_y = src_y >> 16;
src_w = src_w >> 16;
src_h = src_h >> 16;
DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", mdp4_plane->name,
fb->base.id, src_x, src_y, src_w, src_h,
crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
format = to_mdp_format(msm_framebuffer_format(fb));
if (src_w > (crtc_w * DOWN_SCALE_MAX)) {
dev_err(dev->dev, "Width down scaling exceeds limits!\n");
return -ERANGE;
}
if (src_h > (crtc_h * DOWN_SCALE_MAX)) {
dev_err(dev->dev, "Height down scaling exceeds limits!\n");
return -ERANGE;
}
if (crtc_w > (src_w * UP_SCALE_MAX)) {
dev_err(dev->dev, "Width up scaling exceeds limits!\n");
return -ERANGE;
}
if (crtc_h > (src_h * UP_SCALE_MAX)) {
dev_err(dev->dev, "Height up scaling exceeds limits!\n");
return -ERANGE;
}
if (src_w != crtc_w) {
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEX_EN;
if (MDP_FORMAT_IS_YUV(format)) {
if (crtc_w > src_w)
sel_unit = SCALE_PIXEL_RPT;
else if (crtc_w <= (src_w / 4))
sel_unit = SCALE_MN_PHASE;
op_mode |= MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(sel_unit);
phasex_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
src_w, crtc_w);
}
}
if (src_h != crtc_h) {
uint32_t sel_unit = SCALE_FIR;
op_mode |= MDP4_PIPE_OP_MODE_SCALEY_EN;
if (MDP_FORMAT_IS_YUV(format)) {
if (crtc_h > src_h)
sel_unit = SCALE_PIXEL_RPT;
else if (crtc_h <= (src_h / 4))
sel_unit = SCALE_MN_PHASE;
op_mode |= MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(sel_unit);
phasey_step = mult_frac(MDP4_VG_PHASE_STEP_DEFAULT,
src_h, crtc_h);
}
}
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_SIZE(pipe),
MDP4_PIPE_SRC_SIZE_WIDTH(src_w) |
MDP4_PIPE_SRC_SIZE_HEIGHT(src_h));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_XY(pipe),
MDP4_PIPE_SRC_XY_X(src_x) |
MDP4_PIPE_SRC_XY_Y(src_y));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_SIZE(pipe),
MDP4_PIPE_DST_SIZE_WIDTH(crtc_w) |
MDP4_PIPE_DST_SIZE_HEIGHT(crtc_h));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_DST_XY(pipe),
MDP4_PIPE_DST_XY_X(crtc_x) |
MDP4_PIPE_DST_XY_Y(crtc_y));
mdp4_plane_set_scanout(plane, fb);
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_FORMAT(pipe),
MDP4_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
MDP4_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
MDP4_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
MDP4_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
COND(format->alpha_enable, MDP4_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
MDP4_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(format->fetch_type) |
MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample) |
MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(frame_type) |
COND(format->unpack_tight, MDP4_PIPE_SRC_FORMAT_UNPACK_TIGHT));
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SRC_UNPACK(pipe),
MDP4_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
MDP4_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
MDP4_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
MDP4_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
if (MDP_FORMAT_IS_YUV(format)) {
struct csc_cfg *csc = mdp_get_default_csc_cfg(CSC_YUV2RGB);
op_mode |= MDP4_PIPE_OP_MODE_SRC_YCBCR;
op_mode |= MDP4_PIPE_OP_MODE_CSC_EN;
mdp4_write_csc_config(mdp4_kms, pipe, csc);
}
mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(pipe), op_mode);
mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEX_STEP(pipe), phasex_step);
mdp4_write(mdp4_kms, REG_MDP4_PIPE_PHASEY_STEP(pipe), phasey_step);
if (frame_type != FRAME_LINEAR)
mdp4_write(mdp4_kms, REG_MDP4_PIPE_SSTILE_FRAME_SIZE(pipe),
MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(src_w) |
MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(src_h));
return 0;
}
void
fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit,
int nr, struct pipe_surface **bufs)
{
const struct ir3_shader_variant *vp, *fp;
const struct ir3_info *vsi, *fsi;
enum a3xx_instrbuffermode fpbuffer, vpbuffer;
uint32_t fpbuffersz, vpbuffersz, fsoff;
uint32_t pos_regid, posz_regid, psize_regid;
uint32_t vcoord_regid, face_regid, coord_regid, zwcoord_regid;
uint32_t color_regid[4] = {0};
int constmode;
int i, j;
debug_assert(nr <= ARRAY_SIZE(color_regid));
vp = fd3_emit_get_vp(emit);
fp = fd3_emit_get_fp(emit);
vsi = &vp->info;
fsi = &fp->info;
fpbuffer = BUFFER;
vpbuffer = BUFFER;
fpbuffersz = fp->instrlen;
vpbuffersz = vp->instrlen;
/*
* Decide whether to use BUFFER or CACHE mode for VS and FS. It
* appears like 256 is the hard limit, but when the combined size
* exceeds 128 then blob will try to keep FS in BUFFER mode and
* switch to CACHE for VS until VS is too large. The blob seems
* to switch FS out of BUFFER mode at slightly under 128. But
* a bit fuzzy on the decision tree, so use slightly conservative
* limits.
*
* TODO check if these thresholds for BUFFER vs CACHE mode are the
* same for all a3xx or whether we need to consider the gpuid
*/
if ((fpbuffersz + vpbuffersz) > 128) {
if (fpbuffersz < 112) {
/* FP:BUFFER VP:CACHE */
vpbuffer = CACHE;
vpbuffersz = 256 - fpbuffersz;
} else if (vpbuffersz < 112) {
/* FP:CACHE VP:BUFFER */
fpbuffer = CACHE;
fpbuffersz = 256 - vpbuffersz;
} else {
/* FP:CACHE VP:CACHE */
vpbuffer = fpbuffer = CACHE;
vpbuffersz = fpbuffersz = 192;
}
}
if (fpbuffer == BUFFER) {
fsoff = 128 - fpbuffersz;
} else {
fsoff = 256 - fpbuffersz;
}
/* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
if (fp->color0_mrt) {
color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
} else {
color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
}
face_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRONT_FACE);
coord_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD);
zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
vcoord_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
/* adjust regids for alpha output formats. there is no alpha render
* format, so it's just treated like red
*/
for (i = 0; i < nr; i++)
if (util_format_is_alpha(pipe_surface_format(bufs[i])))
color_regid[i] += 3;
/* we could probably divide this up into things that need to be
* emitted if frag-prog is dirty vs if vert-prog is dirty..
*/
OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
/* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
* flush some caches? I think we only need to set those
* bits if we have updated const or shader..
*/
A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(coord_regid) |
A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(zwcoord_regid));
OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31) |
A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(face_regid));
OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(vcoord_regid));
OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
COND(emit->binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
A3XX_SP_SP_CTRL_REG_L0MODE(0));
OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
OUT_RING(ring, A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
OUT_RING(ring, A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen + 1, 0)));
OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));
struct ir3_shader_linkage l = {0};
ir3_link_shaders(&l, vp, fp);
for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
uint32_t reg = 0;
OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
j++;
reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
j++;
OUT_RING(ring, reg);
}
for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
uint32_t reg = 0;
OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
OUT_RING(ring, reg);
}
OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
if (emit->binning_pass) {
OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
OUT_RING(ring, 0x00000000);
OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
OUT_RING(ring, 0x00000000);
OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
} else {
OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
COND(fp->num_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->total_in) |
A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(MAX2(fp->constlen + 1, 0)) |
A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
MAX2(128, vp->constlen)) |
A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
}
OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
OUT_RING(ring,
COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
for (i = 0; i < 4; i++) {
uint32_t mrt_reg = A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
if (i < nr) {
enum pipe_format fmt = pipe_surface_format(bufs[i]);
mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
}
OUT_RING(ring, mrt_reg);
}
if (emit->binning_pass) {
OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) |
A3XX_VPC_ATTR_LMSIZE(1) |
COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
OUT_RING(ring, 0x00000000);
} else {
uint32_t vinterp[4], flatshade[2], vpsrepl[4];
memset(vinterp, 0, sizeof(vinterp));
memset(flatshade, 0, sizeof(flatshade));
memset(vpsrepl, 0, sizeof(vpsrepl));
/* figure out VARYING_INTERP / FLAT_SHAD register values: */
for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count; ) {
/* NOTE: varyings are packed, so if compmask is 0xb
* then first, third, and fourth component occupy
* three consecutive varying slots:
*/
unsigned compmask = fp->inputs[j].compmask;
uint32_t inloc = fp->inputs[j].inloc;
if ((fp->inputs[j].interpolate == INTERP_MODE_FLAT) ||
(fp->inputs[j].rasterflat && emit->rasterflat)) {
uint32_t loc = inloc;
for (i = 0; i < 4; i++) {
if (compmask & (1 << i)) {
vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
flatshade[loc / 32] |= 1 << (loc % 32);
loc++;
}
}
}
gl_varying_slot slot = fp->inputs[j].slot;
/* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
if (slot >= VARYING_SLOT_VAR0) {
unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
/* Replace the .xy coordinates with S/T from the point sprite. Set
* interpolation bits for .zw such that they become .01
*/
if (emit->sprite_coord_enable & texmask) {
/* mask is two 2-bit fields, where:
* '01' -> S
* '10' -> T
* '11' -> 1 - T (flip mode)
*/
unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
uint32_t loc = inloc;
if (compmask & 0x1) {
vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
loc++;
}
if (compmask & 0x2) {
vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
loc++;
}
if (compmask & 0x4) {
/* .z <- 0.0f */
vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
loc++;
}
if (compmask & 0x8) {
/* .w <- 1.0f */
vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
loc++;
}
}
