Exemplo n.º 1
0
void _psp_set_kernel_disable_level
   (
      void
   )
{
    KERNEL_DATA_STRUCT_PTR kernel_data;
    MQX_INITIALIZATION_STRUCT_PTR init_ptr;
   // NVIC_MemMapPtr nvic = NVIC_BASE_PTR;
    uint_32 temp;
    _mqx_int i;

    _GET_KERNEL_DATA(kernel_data);

    init_ptr = (MQX_INITIALIZATION_STRUCT_PTR)&kernel_data->INIT;

    // Compute the enable and disable interrupt values for the kernel.
    temp = init_ptr->MQX_HARDWARE_INTERRUPT_LEVEL_MAX;
    if (temp > 7) {
        temp = 7;
        init_ptr->MQX_HARDWARE_INTERRUPT_LEVEL_MAX = 7;
    } else if (temp == 0) {
        temp = 1;
        init_ptr->MQX_HARDWARE_INTERRUPT_LEVEL_MAX = 1;
    }
    
    kernel_data->DISABLE_SR = CORTEX_PRIOR(temp);
    
    /* Set all (till now unused) interrupts level to the disable level */
    for (i = 0; i < sizeof(NVIC_BASE_PTR->IP) / sizeof(NVIC_BASE_PTR->IP[0]); i++)
        NVIC_BASE_PTR->IP[i] = CORTEX_PRIOR((1 << CORTEX_PRIOR_IMPL) - 2);
    /* Disable interrupts by default */
    for (i = 0; i < sizeof(NVIC_BASE_PTR->ICER) / sizeof(NVIC_BASE_PTR->ICER[0]); i++)
        NVIC_BASE_PTR->ICER[i] = 0xFFFFFFFF; /* disable 32 interrupts in a row */
}
Exemplo n.º 2
0
/*!
 * \cond DOXYGEN_PRIVATE
 *
 * \brief This function check validation of input LPT module
 *
 * \param dev_num[in]   Number of LPT module.
 * \param isr_prior[in] ISR priority.
 *
 * \return MQX_OK Valid.
 */
_mqx_int lpt_validate_module
(
    uint32_t dev_num,
    uint32_t isr_prior
)
{
    if (dev_num >= ELEMENTS_OF(lpt_address)) 
    {
        return MQX_INVALID_DEVICE;
    }
    
    /* Check ISR priority */
    if (0 == CORTEX_PRIOR(isr_prior))
    {
        return MQX_INVALID_PARAMETER;
    }
    
    return MQX_OK;
}
Exemplo n.º 3
0
static void systick_init
(
        void
)
{

    /* Get system clock for active clock configuration */
    uint32_t system_clock = _cm_get_clock(_cm_get_clock_configuration(), CM_CLOCK_SOURCE_CORE);

#if BSP_ALARM_FREQUENCY == 0
    #error Wrong definition of BSP_ALARM_FREQUENCY
#endif

    systick_config(system_clock, BSP_ALARM_FREQUENCY);

    SYST_CSR = 7;

    /* SVCall priority*/
    SCB_SHPR2 |= 0x10000000;
    /* SysTick priority*/
    SCB_SHPR3 |= SCB_SHPR3_PRI_15(CORTEX_PRIOR(BSP_TIMER_INTERRUPT_PRIORITY));
}
Exemplo n.º 4
0
uint_32 _psp_init_readyqs
   (
      void
   )
{ /* Body */
   KERNEL_DATA_STRUCT_PTR kernel_data;
   READY_Q_STRUCT_PTR     q_ptr;
   uint_32                priority_levels;
   uint_32                n;

   _GET_KERNEL_DATA(kernel_data);
   kernel_data->READY_Q_LIST = (READY_Q_STRUCT_PTR) NULL;
   priority_levels = kernel_data->LOWEST_TASK_PRIORITY + 2;

   q_ptr = (READY_Q_STRUCT_PTR)_mem_alloc_zero(sizeof(READY_Q_STRUCT) * priority_levels);
#if MQX_CHECK_MEMORY_ALLOCATION_ERRORS
   if ( q_ptr == NULL ) {
      return (MQX_OUT_OF_MEMORY);
   } /* Endif */
#endif
   _mem_set_type(q_ptr, MEM_TYPE_READYQ);

   n = priority_levels;
   while (n--) {
      q_ptr->HEAD_READY_Q  = (TD_STRUCT_PTR)q_ptr;
      q_ptr->TAIL_READY_Q  = (TD_STRUCT_PTR)q_ptr;
      q_ptr->PRIORITY      = (uint_16)n;

      if (n + kernel_data->INIT.MQX_HARDWARE_INTERRUPT_LEVEL_MAX < ((1 << CORTEX_PRIOR_IMPL) - 1))
        q_ptr->ENABLE_SR   = CORTEX_PRIOR(n + kernel_data->INIT.MQX_HARDWARE_INTERRUPT_LEVEL_MAX);
      else
        q_ptr->ENABLE_SR   = CORTEX_PRIOR((1 << CORTEX_PRIOR_IMPL) - 2);

      q_ptr->NEXT_Q        = kernel_data->READY_Q_LIST;
      kernel_data->READY_Q_LIST = q_ptr++;
   }


   /*
   ** Set the current ready q (where the ready queue searches start) to
   ** the head of the list of ready queues.
   */
   kernel_data->CURRENT_READY_Q = kernel_data->READY_Q_LIST;

#if 0
   /* Initialize the ENABLE_SR fields in the ready queues */
   sr = 0;
   n  = priority_levels;
   q_ptr =  kernel_data->READY_Q_LIST;
   while (n--) {
      q_ptr->ENABLE_SR = CORTEX_PRIOR(sr);
      if (sr < kernel_data->INIT.MQX_HARDWARE_INTERRUPT_LEVEL_MAX) {
         sr++;
      }
      q_ptr = q_ptr->NEXT_Q;
   }
#endif

   return MQX_OK;

} /* Endbody */