void arm_Reset()
{
Arm7Enabled = false;
// clean registers
memset(&arm_Reg[0], 0, sizeof(arm_Reg));
IE = 0x0000;
IF = 0x0000;
IME = 0x0000;
armMode = 0x1F;
reg[13].I = 0x03007F00;
reg[15].I = 0x0000000;
reg[16].I = 0x00000000;
reg[R13_IRQ].I = 0x03007FA0;
reg[R13_SVC].I = 0x03007FE0;
armIrqEnable = true;
armFiqEnable = false;
//armState = true;
C_FLAG = V_FLAG = N_FLAG = Z_FLAG = false;
// disable FIQ
reg[16].I |= 0x40;
CPUUpdateCPSR();
armNextPC = reg[15].I;
reg[15].I += 4;
//arm_FiqPending = false;
}
void virt_arm_reset()
{
// clean registers
memset(&arm_Reg[0], 0, sizeof(arm_Reg));
armMode = 0x0;
reg[13].I = 0x03007F00;
reg[15].I = 0x0000000;
reg[16].I = 0x00000000;
// disable FIQ
reg[16].I |= 0x40;
CPUUpdateCPSR();
armNextPC = reg[15].I;
reg[15].I += 4;
//arm_FiqPending = false;
}
void CPUSwitchMode(int mode, bool saveState, bool breakLoop)
{
CPUUpdateCPSR();
switch(armMode) {
case 0x10:
case 0x1F:
reg[R13_USR].I = reg[13].I;
reg[R14_USR].I = reg[14].I;
reg[17].I = reg[16].I;
break;
case 0x11:
CPUSwap(®[R8_FIQ].I, ®[8].I);
CPUSwap(®[R9_FIQ].I, ®[9].I);
CPUSwap(®[R10_FIQ].I, ®[10].I);
CPUSwap(®[R11_FIQ].I, ®[11].I);
CPUSwap(®[R12_FIQ].I, ®[12].I);
reg[R13_FIQ].I = reg[13].I;
reg[R14_FIQ].I = reg[14].I;
reg[SPSR_FIQ].I = reg[17].I;
break;
case 0x12:
reg[R13_IRQ].I = reg[13].I;
reg[R14_IRQ].I = reg[14].I;
reg[SPSR_IRQ].I = reg[17].I;
break;
case 0x13:
reg[R13_SVC].I = reg[13].I;
reg[R14_SVC].I = reg[14].I;
reg[SPSR_SVC].I = reg[17].I;
break;
case 0x17:
reg[R13_ABT].I = reg[13].I;
reg[R14_ABT].I = reg[14].I;
reg[SPSR_ABT].I = reg[17].I;
break;
case 0x1b:
reg[R13_UND].I = reg[13].I;
reg[R14_UND].I = reg[14].I;
reg[SPSR_UND].I = reg[17].I;
break;
}
u32 CPSR = reg[16].I;
u32 SPSR = reg[17].I;
switch(mode) {
case 0x10:
case 0x1F:
reg[13].I = reg[R13_USR].I;
reg[14].I = reg[R14_USR].I;
reg[16].I = SPSR;
break;
case 0x11:
CPUSwap(®[8].I, ®[R8_FIQ].I);
CPUSwap(®[9].I, ®[R9_FIQ].I);
CPUSwap(®[10].I, ®[R10_FIQ].I);
CPUSwap(®[11].I, ®[R11_FIQ].I);
CPUSwap(®[12].I, ®[R12_FIQ].I);
reg[13].I = reg[R13_FIQ].I;
reg[14].I = reg[R14_FIQ].I;
if(saveState)
reg[17].I = CPSR;
else
reg[17].I = reg[SPSR_FIQ].I;
break;
case 0x12:
reg[13].I = reg[R13_IRQ].I;
reg[14].I = reg[R14_IRQ].I;
reg[16].I = SPSR;
if(saveState)
reg[17].I = CPSR;
else
reg[17].I = reg[SPSR_IRQ].I;
break;
case 0x13:
reg[13].I = reg[R13_SVC].I;
reg[14].I = reg[R14_SVC].I;
reg[16].I = SPSR;
if(saveState)
reg[17].I = CPSR;
else
reg[17].I = reg[SPSR_SVC].I;
break;
case 0x17:
reg[13].I = reg[R13_ABT].I;
reg[14].I = reg[R14_ABT].I;
reg[16].I = SPSR;
if(saveState)
reg[17].I = CPSR;
else
reg[17].I = reg[SPSR_ABT].I;
break;
case 0x1b:
reg[13].I = reg[R13_UND].I;
reg[14].I = reg[R14_UND].I;
reg[16].I = SPSR;
if(saveState)
reg[17].I = CPSR;
else
reg[17].I = reg[SPSR_UND].I;
break;
default:
printf("Unsupported ARM mode %02x\n", mode);
//gli die("Arm error..");
break;
}
armMode = mode;
CPUUpdateFlags(breakLoop);
CPUUpdateCPSR();
}
void Disassemble::refresh()
{
if(rom == NULL)
return;
bool arm = armState;
if(mode != 0) {
if(mode == 1)
arm = true;
else
arm = false;
}
int h = m_list.GetItemHeight(0);
RECT r;
m_list.GetClientRect(&r);
count = (r.bottom - r.top+1)/h;
m_list.ResetContent();
if(!emulating && theApp.cartridgeType == 0)
return;
char buffer[80];
u32 addr = address;
int i;
int sel = -1;
for(i = 0; i < count; i++) {
if(addr == armNextPC)
sel = i;
if(arm) {
addr += disArm(addr, buffer, 3);
} else {
addr += disThumb(addr, buffer, 3);
}
m_list.InsertString(-1, buffer);
}
if(sel != -1)
m_list.SetCurSel(sel);
CPUUpdateCPSR();
for(i = 0; i < 17; i++) {
sprintf(buffer, "%08x", reg[i].I);
GetDlgItem(IDC_R0+i)->SetWindowText(buffer);
}
m_n = (reg[16].I & 0x80000000) != 0;
m_z = (reg[16].I & 0x40000000) != 0;
m_c = (reg[16].I & 0x20000000) != 0;
m_v = (reg[16].I & 0x10000000) != 0;
m_i = (reg[16].I & 0x80) != 0;
m_f = (reg[16].I & 0x40) != 0;
m_t = (reg[16].I & 0x20) != 0;
UpdateData(FALSE);
int v = reg[16].I & 0x1f;
sprintf(buffer, "%02x", v);
GetDlgItem(IDC_MODE)->SetWindowText(buffer);
}
