void SAMA5D3X_MmuInit()
{
MMU_Initialize((uint32_t *)c_Bootstrap_BaseOfTTBs);
CPU_EnableMMU(c_Bootstrap_BaseOfTTBs);
CPU_EnableCaches();
}
void BootstrapCode_MMU()
{
// Fill Translation table with faults.
ARM9_MMU::InitializeL1(c_Bootstrap_BaseOfTTBs);
// Direct map for the APB registers (0xFFF00000 ~ 0xFFFFFFFF)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
c_Bootstrap_Register_Begin, // mapped address
c_Bootstrap_Register_Begin, // physical address
c_Bootstrap_Register_End - c_Bootstrap_Register_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
FALSE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Direct map SDRAM (cachable)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
c_Bootstrap_SDRAM_Begin, // mapped address
c_Bootstrap_SDRAM_Begin, // physical address
c_Bootstrap_SDRAM_End - c_Bootstrap_SDRAM_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
TRUE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Remap SRAM @0x000000000 (cachable)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
0x00000000, // mapped address
c_Bootstrap_SRAM_Begin, // physical address
c_Bootstrap_SRAM_End - c_Bootstrap_SRAM_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
TRUE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Direct map SRAM (cachable)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
c_Bootstrap_SRAM_Begin, // mapped address
c_Bootstrap_SRAM_Begin, // physical address
c_Bootstrap_SRAM_End - c_Bootstrap_SRAM_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
TRUE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Direct map for the LCD registers(0x00600000~0x006FFFFF)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
AT91C_BASE_LCDC, // mapped address
AT91C_BASE_LCDC, // physical address
ARM9_MMU::c_MMU_L1_size, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
FALSE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
// Direct map for the FLASH (uncachable)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
c_Bootstrap_FLASH_Begin, // mapped address
c_Bootstrap_FLASH_Begin, // physical address
c_Bootstrap_FLASH_End - c_Bootstrap_FLASH_Begin, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
FALSE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
#ifdef PLATFORM_ARM_SAM9RL64_ANY
// Direct map for the USBHS buffer registers(0x00600000~0x006FFFFF)
ARM9_MMU::GenerateL1_Sections(
c_Bootstrap_BaseOfTTBs, // base of TTBs
AT91C_BASE_UDP_DMA, // mapped address
AT91C_BASE_UDP_DMA, // physical address
ARM9_MMU::c_MMU_L1_size, // length to be mapped
ARM9_MMU::c_AP__Manager, // AP
0, // Domain
FALSE, // Cacheable
FALSE, // Buffered
FALSE); // Extended
#endif
// TODO: UNCOMMENT if FLASH is added on external bus
//
// Direct map for the FLASH (cachable)
// ARM9_MMU::GenerateL1_Sections(
// c_Bootstrap_BaseOfTTBs, // base of TTBs
// c_Bootstrap_FLASH_Begin, // mapped address
// c_Bootstrap_FLASH_Begin, // physical address
// c_Bootstrap_FLASH_End - c_Bootstrap_FLASH_Begin, // length to be mapped
// ARM9_MMU::c_AP__Manager, // AP
// 0, // Domain
// TRUE, // Cacheable
// FALSE, // Buffered
// FALSE); // Extended
// Direct map for the FLASH (uncachable)
// ARM9_MMU::GenerateL1_Sections(
// c_Bootstrap_BaseOfTTBs, // base of TTBs
// CPU_GetUncachableAddress(c_Bootstrap_FLASH_Begin), // mapped address
// c_Bootstrap_FLASH_Begin, // physical address
// c_Bootstrap_FLASH_End - c_Bootstrap_FLASH_Begin, // length to be mapped
// ARM9_MMU::c_AP__Manager, // AP
// 0, // Domain
// FALSE, // Cacheable
// FALSE, // Buffered
// FALSE); // Extended
//
CPU_FlushCaches();
CPU_EnableMMU( c_Bootstrap_BaseOfTTBs );
}
