static void i80286_trap2(i80286_state *cpustate,UINT32 error) { int error_code = error & 0xffff; UINT16 number = error >> 16; if(error_code == 0xffff) error_code = -1; cpustate->pc = cpustate->prevpc; try { switch(number) { case DIVIDE_BY_ZERO: case INVALID_TSS: case SEG_NOT_PRESENT: case STACK_FAULT: case GENERAL_PROTECTION_FAULT: cpustate->trap_level++; if(cpustate->trap_level == 2) throw TRAP(DOUBLE_FAULT,0); if(cpustate->trap_level == 3) break; i80286_interrupt_descriptor(cpustate,number,1,error_code); break; case DOUBLE_FAULT: i80286_interrupt_descriptor(cpustate,number,1,0); break; default: i80286_interrupt_descriptor(cpustate,number,1,-1); } } catch(UINT32 e) { i80286_trap2(cpustate, e); } if(cpustate->trap_level == 3) { // this is supposed to triggered by support hardware // create a shutdown output line that causes a reset // NMI can wake processor without reset CPU_RESET_CALL(CPU_MODEL); } cpustate->trap_level = 0; }
static CPU_RESET( m65c02 ) { m6502_Regs *cpustate = get_safe_token(device); CPU_RESET_CALL(m6502); P &=~F_D; }
static CPU_RESET( m6510 ) { m6502_Regs *cpustate = get_safe_token(device); CPU_RESET_CALL(m6502); cpustate->port = 0xff; cpustate->ddr = 0x00; }
void HUC6280::reset() { h6280_Regs *cpustate = (h6280_Regs *)opaque; CPU_RESET_CALL(h6280); cpustate->program = d_mem; cpustate->io = d_io; }
static CPU_RESET( m68705 ) { m6805_Regs *cpustate = get_safe_token(device); CPU_RESET_CALL(m6805); /* Overide default 6805 type */ cpustate->subtype = SUBTYPE_M68705; RM16( cpustate, 0xfffe, &cpustate->pc ); }
static CPU_RESET( m68hc05eg ) { m6805_Regs *cpustate = get_safe_token(device); CPU_RESET_CALL(m6805); /* Overide default 6805 type */ cpustate->subtype = SUBTYPE_M68HC05EG; SP_MASK = 0xff; SP_LOW = 0xc0; RM16( cpustate, 0x1ffe, &cpustate->pc ); }
static CPU_RESET( hd63705 ) { m6805_Regs *cpustate = get_safe_token(device); CPU_RESET_CALL(m6805); /* Overide default 6805 types */ cpustate->subtype = SUBTYPE_HD63705; SP_MASK = 0x17f; SP_LOW = 0x100; RM16( cpustate, 0x1ffe, &cpustate->pc ); S = 0x17f; }
static CPU_RESET( deco16 ) { m6502_Regs *cpustate = get_safe_token(device); CPU_RESET_CALL(m6502); cpustate->subtype = SUBTYPE_DECO16; cpustate->insn = insndeco16; PCL = RDMEM(DECO16_RST_VEC+1); PCH = RDMEM(DECO16_RST_VEC); cpustate->sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */ cpustate->p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */ cpustate->pending_irq = 0; /* nonzero if an IRQ is pending */ cpustate->after_cli = 0; /* pending IRQ and last insn cleared I */ }
void HUC6280::reset() { h6280_Regs *cpustate = (h6280_Regs *)opaque; CPU_RESET_CALL(h6280); cpustate->program = d_mem; cpustate->io = d_io; #ifdef USE_DEBUGGER cpustate->emu = emu; cpustate->debugger = d_debugger; cpustate->program_stored = d_mem; cpustate->io_stored = d_io; #endif icount = 0; busreq = false; }
void I386::reset() { i386_state *cpustate = (i386_state *)opaque; CPU_RESET_CALL(CPU_MODEL); }