/**************************************************************************//**
\brief Application network info command handler.
\param[in] pCommand - pointer to application command.
\return true if deletion is needed, false otherwise.
******************************************************************************/
bool appRouterNwkInfoCmdHandler(AppCommand_t *pCommand)
{
APS_DataReq_t *pMsgParams = NULL;
if (appCreateTxFrame(&pMsgParams, &pCommand, NULL))
{
memset(pMsgParams, 0, sizeof(APS_DataReq_t));
pMsgParams->profileId = CCPU_TO_LE16(WSNDEMO_PROFILE_ID);
pMsgParams->dstAddrMode = APS_SHORT_ADDRESS;
pMsgParams->dstAddress.shortAddress = CPU_TO_LE16(0);
pMsgParams->dstEndpoint = 1;
pMsgParams->clusterId = CPU_TO_LE16(1);
pMsgParams->srcEndpoint = WSNDEMO_ENDPOINT;
pMsgParams->asduLength = sizeof(AppNwkInfoCmdPayload_t) + sizeof(pCommand->id);
pMsgParams->txOptions.acknowledgedTransmission = 1;
#ifdef _APS_FRAGMENTATION_
pMsgParams->txOptions.fragmentationPermitted = 1;
#endif
#ifdef _LINK_SECURITY_
pMsgParams->txOptions.securityEnabledTransmission = 1;
#endif
pMsgParams->radius = 0x0;
}
return true;
}
void RNDIS_Device_USBTask(USB_ClassInfo_RNDIS_Device_t* const RNDISInterfaceInfo)
{
if (USB_DeviceState != DEVICE_STATE_Configured)
return;
Endpoint_SelectEndpoint(RNDISInterfaceInfo->Config.NotificationEndpoint.Address);
if (Endpoint_IsINReady() && RNDISInterfaceInfo->State.ResponseReady)
{
USB_Request_Header_t Notification = (USB_Request_Header_t)
{
.bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE),
.bRequest = RNDIS_NOTIF_ResponseAvailable,
.wValue = CPU_TO_LE16(0),
.wIndex = CPU_TO_LE16(0),
.wLength = CPU_TO_LE16(0),
};
Endpoint_Write_Stream_LE(&Notification, sizeof(USB_Request_Header_t), NULL);
Endpoint_ClearIN();
RNDISInterfaceInfo->State.ResponseReady = false;
}
}
static bool Bluetooth_L2CAP_SendSignalPacket(BT_StackConfig_t* const StackState,
const uint16_t ConnectionHandle,
const uint8_t SignalCode,
const uint8_t SignalIdentifier,
const uint16_t Length,
void* Data)
{
/* Construct a temporary channel object with the signalling channel indexes */
BT_L2CAP_Channel_t SignalChannel;
SignalChannel.ConnectionHandle = cpu_to_le16(ConnectionHandle);
SignalChannel.State = L2CAP_CHANSTATE_Open;
SignalChannel.LocalNumber = CPU_TO_LE16(BT_CHANNEL_SIGNALING);
SignalChannel.RemoteNumber = CPU_TO_LE16(BT_CHANNEL_SIGNALING);
struct
{
BT_Signal_Header_t SignalCommandHeader;
uint8_t Data[Length];
} ATTR_PACKED SignalPacket;
/* Fill out the Signal Command header in the response packet */
SignalPacket.SignalCommandHeader.Code = SignalCode;
SignalPacket.SignalCommandHeader.Identifier = SignalIdentifier;
SignalPacket.SignalCommandHeader.Length = cpu_to_le16(Length);
memcpy(SignalPacket.Data, Data, Length);
return Bluetooth_L2CAP_SendPacket(StackState, &SignalChannel, sizeof(SignalPacket), &SignalPacket);
}
void CDC_Device_SendControlLineStateChange(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo)
{
if ((USB_DeviceState != DEVICE_STATE_Configured) || !(CDCInterfaceInfo->State.LineEncoding.BaudRateBPS))
return;
Endpoint_SelectEndpoint(CDCInterfaceInfo->Config.NotificationEndpointNumber);
USB_Request_Header_t Notification = (USB_Request_Header_t)
{
.bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_CLASS | REQREC_INTERFACE),
.bRequest = CDC_NOTIF_SerialState,
.wValue = CPU_TO_LE16(0),
.wIndex = CPU_TO_LE16(0),
.wLength = CPU_TO_LE16(sizeof(CDCInterfaceInfo->State.ControlLineStates.DeviceToHost)),
};
Endpoint_Write_Stream_LE(&Notification, sizeof(USB_Request_Header_t), NULL);
Endpoint_Write_Stream_LE(&CDCInterfaceInfo->State.ControlLineStates.DeviceToHost,
sizeof(CDCInterfaceInfo->State.ControlLineStates.DeviceToHost),
NULL);
Endpoint_ClearIN();
}
#if defined(FDEV_SETUP_STREAM)
void CDC_Device_CreateStream(USB_ClassInfo_CDC_Device_t* const CDCInterfaceInfo,
FILE* const Stream)
{
*Stream = (FILE)FDEV_SETUP_STREAM(CDC_Device_putchar, CDC_Device_getchar, _FDEV_SETUP_RW);
fdev_set_udata(Stream, CDCInterfaceInfo);
}
static bool udi_cdc_comm_enable_common(uint8_t port)
{
// Initialize control signal management
udi_cdc_state[PORT] = CPU_TO_LE16(0);
uid_cdc_state_msg[PORT].header.bmRequestType =
USB_REQ_DIR_IN | USB_REQ_TYPE_CLASS |
USB_REQ_RECIP_INTERFACE,
uid_cdc_state_msg[PORT].header.bNotification = USB_REQ_CDC_NOTIFY_SERIAL_STATE,
uid_cdc_state_msg[PORT].header.wValue = LE16(0),
uid_cdc_state_msg[PORT].header.wIndex = LE16(UDI_CDC_COMM_IFACE_NUMBER),
uid_cdc_state_msg[PORT].header.wLength = LE16(2),
uid_cdc_state_msg[PORT].value = CPU_TO_LE16(0);
udi_cdc_line_coding[PORT].dwDTERate = CPU_TO_LE32(UDI_CDC_DEFAULT_RATE);
udi_cdc_line_coding[PORT].bCharFormat = UDI_CDC_DEFAULT_STOPBITS;
udi_cdc_line_coding[PORT].bParityType = UDI_CDC_DEFAULT_PARITY;
udi_cdc_line_coding[PORT].bDataBits = UDI_CDC_DEFAULT_DATABITS;
// Call application callback
// to initialize memories or indicate that interface is enabled
#if UDI_CDC_PORT_NB == 1
UDI_CDC_SET_CODING_EXT((&udi_cdc_line_coding[0]));
return UDI_CDC_ENABLE_EXT();
#else
UDI_CDC_SET_CODING_EXT(port,(&udi_cdc_line_coding[port]));
return UDI_CDC_ENABLE_EXT(port);
#endif
}
uint8_t PTP_Transaction(uint16_t opCode, uint8_t receive_data, uint8_t paramCount, uint32_t *params, uint8_t dataBytes, uint8_t *data)
{
if(PTP_Error) return PTP_RETURN_ERROR;
if(PTP_Bytes_Remaining > 0) return PTP_FetchData(0);
uint8_t err;
PTP_Run_Task = 0; // Pause task while we're busy with the transaction
if(paramCount > 0 && params)
err = SI_Host_SendCommand(&DigitalCamera_SI_Interface, CPU_TO_LE16(opCode), paramCount, params);
else
err = SI_Host_SendCommand(&DigitalCamera_SI_Interface, CPU_TO_LE16(opCode), 0, NULL);
if(!err && dataBytes > 0 && data) // send data
{
DigitalCamera_SI_Interface.State.TransactionID--;
PIMA_Block = (PIMA_Container_t)
{
.DataLength = CPU_TO_LE32(PIMA_DATA_SIZE(dataBytes)),
.Type = CPU_TO_LE16(PIMA_CONTAINER_DataBlock),
.Code = CPU_TO_LE16(opCode)
};
memcpy(&PIMA_Block.Params, data, dataBytes);
err = SI_Host_SendBlockHeader(&DigitalCamera_SI_Interface, &PIMA_Block);
}
/**
* i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
* @desc: pointer to the temp descriptor (non DMA mem)
* @opcode: the opcode can be used to decide which flags to turn off or on
*
* Fill the desc with default values
**/
void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
u16 opcode)
{
/* zero out the desc */
i40e_memset((void *)desc, 0, sizeof(struct i40e_aq_desc),
I40E_NONDMA_MEM);
desc->opcode = CPU_TO_LE16(opcode);
desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_SI);
}
/** Manages the existing L2CAP layer connections of a Bluetooth adapter.
*
* \param[in, out] StackState Pointer to a Bluetooth Stack state table.
*
* \return Boolean \c true if more L2CAP management tasks are pending, \c false otherwise.
*/
bool Bluetooth_L2CAP_Manage(BT_StackConfig_t* const StackState)
{
/* Check if there are any pending events in the L2CAP event queue */
if (StackState->State.L2CAP.PendingEvents)
{
BT_L2CAP_Event_t* Event = &StackState->State.L2CAP.Events[0];
bool DequeueEvent = true;
/* Look up the event's associated channel (if one exists) by the local channel number */
BT_L2CAP_Channel_t* L2CAPChannel = Bluetooth_L2CAP_FindChannel(StackState, Event->ConnectionHandle, Event->LocalNumber, 0);
/* Determine and process the next queued L2CAP event in the event queue, sending command packets as needed */
if (Event->Event == L2CAP_EVENT_EchoReq)
{
DequeueEvent = Bluetooth_L2CAP_SendSignalPacket(StackState, Event->ConnectionHandle, BT_SIGNAL_ECHO_RESPONSE, Event->Identifier, 0, NULL);
}
else if (Event->Event == L2CAP_EVENT_InformationReq)
{
struct
{
BT_Signal_InformationResp_t InformationResponse;
uint8_t Data[4];
} ATTR_PACKED ResponsePacket;
uint8_t DataLen = 0;
/* Retrieve the requested information and store it in the outgoing packet, if found */
switch (Event->Result)
{
case BT_INFOREQ_MTU:
ResponsePacket.InformationResponse.Result = CPU_TO_LE16(BT_INFORMATION_SUCCESSFUL);
DataLen = 2;
ResponsePacket.Data[0] = (BT_DEFAULT_L2CAP_CHANNEL_MTU & 0xFF);
ResponsePacket.Data[1] = (BT_DEFAULT_L2CAP_CHANNEL_MTU >> 8);
break;
case BT_INFOREQ_EXTENDEDFEATURES:
ResponsePacket.InformationResponse.Result = CPU_TO_LE16(BT_INFORMATION_SUCCESSFUL);
DataLen = 4;
ResponsePacket.Data[0] = (0UL & 0xFF);
ResponsePacket.Data[1] = (0UL >> 8);
ResponsePacket.Data[2] = (0UL >> 16);
ResponsePacket.Data[3] = (0UL >> 24);
break;
default:
ResponsePacket.InformationResponse.Result = CPU_TO_LE16(BT_INFORMATION_NOTSUPPORTED);
break;
}
ResponsePacket.InformationResponse.InfoType = cpu_to_le16(Event->Result);
DequeueEvent = Bluetooth_L2CAP_SendSignalPacket(StackState, Event->ConnectionHandle, BT_SIGNAL_INFORMATION_RESPONSE, Event->Identifier,
(sizeof(ResponsePacket.InformationResponse) + DataLen), &ResponsePacket);
}
else if (Event->Event == L2CAP_EVENT_SendRejectReq)
bool udi_cdc_comm_enable(void)
{
uint8_t port;
uint8_t iface_comm_num;
#if UDI_CDC_PORT_NB == 1 // To optimize code
port = 0;
udi_cdc_nb_comm_enabled = 0;
#else
if (udi_cdc_nb_comm_enabled > UDI_CDC_PORT_NB) {
udi_cdc_nb_comm_enabled = 0;
}
port = udi_cdc_nb_comm_enabled;
#endif
// Initialize control signal management
udi_cdc_state[port] = CPU_TO_LE16(0);
uid_cdc_state_msg[port].header.bmRequestType =
USB_REQ_DIR_IN | USB_REQ_TYPE_CLASS |
USB_REQ_RECIP_INTERFACE;
uid_cdc_state_msg[port].header.bNotification = USB_REQ_CDC_NOTIFY_SERIAL_STATE;
uid_cdc_state_msg[port].header.wValue = LE16(0);
switch (port) {
#define UDI_CDC_PORT_TO_IFACE_COMM(index, unused) \
case index: \
iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_##index; \
break;
MREPEAT(UDI_CDC_PORT_NB, UDI_CDC_PORT_TO_IFACE_COMM, ~)
#undef UDI_CDC_PORT_TO_IFACE_COMM
default:
iface_comm_num = UDI_CDC_COMM_IFACE_NUMBER_0;
break;
}
uid_cdc_state_msg[port].header.wIndex = LE16(iface_comm_num);
uid_cdc_state_msg[port].header.wLength = LE16(2);
uid_cdc_state_msg[port].value = CPU_TO_LE16(0);
udi_cdc_line_coding[port].dwDTERate = CPU_TO_LE32(UDI_CDC_DEFAULT_RATE);
udi_cdc_line_coding[port].bCharFormat = UDI_CDC_DEFAULT_STOPBITS;
udi_cdc_line_coding[port].bParityType = UDI_CDC_DEFAULT_PARITY;
udi_cdc_line_coding[port].bDataBits = UDI_CDC_DEFAULT_DATABITS;
// Call application callback
// to initialize memories or indicate that interface is enabled
UDI_CDC_SET_CODING_EXT(port,(&udi_cdc_line_coding[port]));
if (!UDI_CDC_ENABLE_EXT(port)) {
return false;
}
udi_cdc_nb_comm_enabled++;
return true;
}
bool udi_cdc_comm_enable(void)
{
// Initialize control signal management
udi_cdc_state = CPU_TO_LE16(0);
uid_cdc_state_msg.value = CPU_TO_LE16(0);
udi_cdc_line_coding.dwDTERate = CPU_TO_LE32(UDI_CDC_DEFAULT_RATE);
udi_cdc_line_coding.bCharFormat = UDI_CDC_DEFAULT_STOPBITS;
udi_cdc_line_coding.bParityType = UDI_CDC_DEFAULT_PARITY;
udi_cdc_line_coding.bDataBits = UDI_CDC_DEFAULT_DATABITS;
UDI_CDC_SET_CODING_EXT((&udi_cdc_line_coding));
// Call application callback
// to initialize memories or indicate that interface is enabled
return UDI_CDC_ENABLE_EXT();
}
static uint16_t getDeviceDescriptor(void const **const outDescriptor) {
static USB_StdDescriptor_Device_t const PROGMEM kDeviceDescriptor = {
.bLength = sizeof kDeviceDescriptor,
.bDescriptorType = DTYPE_Device,
.bcdUSB = VERSION_BCD(2.0),
.bDeviceClass = 0,
.bDeviceSubClass = 0,
.bDeviceProtocol = 0,
.bMaxPacketSize0 = FIXED_CONTROL_ENDPOINT_SIZE,
.idVendor = CPU_TO_LE16(0xFFFF),
.idProduct = CPU_TO_LE16(0x0001),
.bcdDevice = VERSION_BCD(1.0),
.iManufacturer = kManufacturerDescriptorIndex,
.iProduct = kProductDescriptorIndex,
.iSerialNumber = 0,
.bNumConfigurations = 1
};
setOutputBit(&kRedLED, 1);
*outDescriptor = &kDeviceDescriptor;
return sizeof kDeviceDescriptor;
}
static uint16_t getLanguageDescriptor(void const **const outDescriptor) {
static USB_StdDescriptor_String_t const PROGMEM kDescriptor = {
.bLength = 4,
.bDescriptorType = DTYPE_String,
.bString = { LANGUAGE_ID_ENG }
};
*outDescriptor = &kDescriptor;
return pgm_read_byte(&kDescriptor.bLength);
}
static uint16_t getManufacturerDescriptor(void const **const outDescriptor) {
MakeStringDescriptor(kDescriptor, "Rob Mayoff");
*outDescriptor = &kDescriptor;
return pgm_read_byte(&kDescriptor.Header.Size);
}
static uint16_t getProductDescriptor(void const **const outDescriptor) {
MakeStringDescriptor(kDescriptor, "Mouse Imposter");
*outDescriptor = &kDescriptor;
return pgm_read_byte(&kDescriptor.Header.Size);
}
bool udi_cdc_data_enable(void)
{
// Initialize control signal management
udi_cdc_state = CPU_TO_LE16(0);
uid_cdc_state_msg.value = CPU_TO_LE16(0);
// Initialize TX management
udi_cdc_tx_buf_nb[0] = 0;
udi_cdc_tx_buf_nb[1] = 0;
udi_cdc_tx_buf_sel = 0;
udi_cdc_tx_trans_sel = UDI_CDC_TRANS_HALTED;
// Initialize RX management
udi_cdc_rx_buf_nb[0] = 0;
udi_cdc_rx_buf_nb[1] = 0;
udi_cdc_rx_pos = 0;
udi_cdc_rx_buf_sel = 0;
udi_cdc_rx_trans_sel = 0;
return udi_cdc_rx_start();
}
void AJ_WSL_HTC_ProcessInterruptCause(void)
{
uint16_t cause = 0;
AJ_Status status = AJ_ERR_SPI_READ;
status = AJ_WSL_SPI_RegisterRead(AJ_WSL_SPI_REG_INTR_CAUSE, (uint8_t*)&cause);
AJ_ASSERT(status == AJ_OK);
cause = LE16_TO_CPU(cause);
if (cause & AJ_WSL_SPI_REG_INTR_CAUSE_DATA_AVAILABLE) {
AJ_WSL_HTC_ProcessIncoming();
cause = cause ^ AJ_WSL_SPI_REG_INTR_CAUSE_DATA_AVAILABLE; //clear the bit
}
if (cause & AJ_WSL_SPI_REG_INTR_CAUSE_READ_DONE) {
uint16_t clearCause = CPU_TO_LE16(AJ_WSL_SPI_REG_INTR_CAUSE_READ_DONE);
status = AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_CAUSE, clearCause);
AJ_ASSERT(status == AJ_OK);
cause = cause ^ AJ_WSL_SPI_REG_INTR_CAUSE_READ_DONE;
}
if (cause & AJ_WSL_SPI_REG_INTR_CAUSE_WRITE_DONE) {
uint16_t clearCause = CPU_TO_LE16(AJ_WSL_SPI_REG_INTR_CAUSE_WRITE_DONE);
status = AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_CAUSE, clearCause);
AJ_ASSERT(status == AJ_OK);
cause = cause ^ AJ_WSL_SPI_REG_INTR_CAUSE_WRITE_DONE;
}
if (cause & AJ_WSL_SPI_REG_INTR_CAUSE_CPU_AWAKE) {
uint16_t clearCause = CPU_TO_LE16(AJ_WSL_SPI_REG_INTR_CAUSE_CPU_AWAKE);
status = AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_CAUSE, clearCause);
AJ_ASSERT(status == AJ_OK);
cause = cause ^ AJ_WSL_SPI_REG_INTR_CAUSE_CPU_AWAKE;
}
if (cause & AJ_WSL_SPI_REG_INTR_CAUSE_COUNTER) {
uint16_t clearCause = CPU_TO_LE16(AJ_WSL_SPI_REG_INTR_CAUSE_COUNTER);
status = AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_CAUSE, clearCause);
AJ_ASSERT(status == AJ_OK);
cause = cause ^ AJ_WSL_SPI_REG_INTR_CAUSE_COUNTER;
}
if (cause & ~AJ_WSL_SPI_REG_INTR_CAUSE_DATA_AVAILABLE) {
//AJ_InfoPrintf(("Some other interrupt cause as well %x\n", cause));
}
}
/**
* i40e_write_word - replace HMC context word
* @hmc_bits: pointer to the HMC memory
* @ce_info: a description of the struct to be read from
* @src: the struct to be read from
**/
static void i40e_write_word(u8 *hmc_bits,
struct i40e_context_ele *ce_info,
u8 *src)
{
u16 src_word, mask;
u8 *from, *dest;
u16 shift_width;
__le16 dest_word;
/* copy from the next struct field */
from = src + ce_info->offset;
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
mask = ((u16)1 << ce_info->width) - 1;
/* don't swizzle the bits until after the mask because the mask bits
* will be in a different bit position on big endian machines
*/
src_word = *(u16 *)from;
src_word &= mask;
/* shift to correct alignment */
mask <<= shift_width;
src_word <<= shift_width;
/* get the current bits from the target bit string */
dest = hmc_bits + (ce_info->lsb / 8);
i40e_memcpy(&dest_word, dest, sizeof(dest_word), I40E_DMA_TO_NONDMA);
dest_word &= ~(CPU_TO_LE16(mask)); /* get the bits not changing */
dest_word |= CPU_TO_LE16(src_word); /* add in the new bits */
/* put it all back */
i40e_memcpy(dest, &dest_word, sizeof(dest_word), I40E_NONDMA_TO_DMA);
}
uint8_t SI_Host_ReceiveResponse(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo)
{
uint8_t ErrorCode;
PIMA_Container_t PIMABlock;
uint8_t portnum = SIInterfaceInfo->Config.PortNumber;
if ((USB_HostState[portnum] != HOST_STATE_Configured) || !(SIInterfaceInfo->State.IsActive))
return PIPE_RWSTREAM_DeviceDisconnected;
if ((ErrorCode = SI_Host_ReceiveBlockHeader(SIInterfaceInfo, &PIMABlock)) != PIPE_RWSTREAM_NoError)
return ErrorCode;
if ((PIMABlock.Type != CPU_TO_LE16(PIMA_CONTAINER_ResponseBlock)) || (PIMABlock.Code != CPU_TO_LE16(0x2001)))
return SI_ERROR_LOGICAL_CMD_FAILED;
return PIPE_RWSTREAM_NoError;
}
/**
* i40e_read_word - read HMC context word into struct
* @hmc_bits: pointer to the HMC memory
* @ce_info: a description of the struct to be filled
* @dest: the struct to be filled
**/
static void i40e_read_word(u8 *hmc_bits,
struct i40e_context_ele *ce_info,
u8 *dest)
{
u16 dest_word, mask;
u8 *src, *target;
u16 shift_width;
__le16 src_word;
/* prepare the bits and mask */
shift_width = ce_info->lsb % 8;
mask = ((u16)1 << ce_info->width) - 1;
/* shift to correct alignment */
mask <<= shift_width;
/* get the current bits from the src bit string */
src = hmc_bits + (ce_info->lsb / 8);
i40e_memcpy(&src_word, src, sizeof(src_word), I40E_DMA_TO_NONDMA);
/* the data in the memory is stored as little endian so mask it
* correctly
*/
src_word &= ~(CPU_TO_LE16(mask));
/* get the data back into host order before shifting */
dest_word = LE16_TO_CPU(src_word);
dest_word >>= shift_width;
/* get the address from the struct field */
target = dest + ce_info->offset;
/* put it back in the struct */
i40e_memcpy(target, &dest_word, sizeof(dest_word), I40E_NONDMA_TO_DMA);
}
/**
* i40e_is_nvm_update_op - return true if this is an NVM update operation
* @desc: API request descriptor
**/
STATIC INLINE bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
{
return (desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_erase) ||
desc->opcode == CPU_TO_LE16(i40e_aqc_opc_nvm_update));
}
/**
* i40e_asq_send_command - send command to Admin Queue
* @hw: pointer to the hw struct
* @desc: prefilled descriptor describing the command (non DMA mem)
* @buff: buffer to use for indirect commands
* @buff_size: size of buffer for indirect commands
* @cmd_details: pointer to command details structure
*
* This is the main send command driver routine for the Admin Queue send
* queue. It runs the queue, cleans the queue, etc
**/
enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
struct i40e_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct i40e_asq_cmd_details *cmd_details)
{
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_dma_mem *dma_buff = NULL;
struct i40e_asq_cmd_details *details;
struct i40e_aq_desc *desc_on_ring;
bool cmd_completed = false;
u16 retval = 0;
u32 val = 0;
i40e_acquire_spinlock(&hw->aq.asq_spinlock);
hw->aq.asq_last_status = I40E_AQ_RC_OK;
if (hw->aq.asq.count == 0) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: Admin queue not initialized.\n");
status = I40E_ERR_QUEUE_EMPTY;
goto asq_send_command_error;
}
val = rd32(hw, hw->aq.asq.head);
if (val >= hw->aq.num_asq_entries) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: head overrun at %d\n", val);
status = I40E_ERR_QUEUE_EMPTY;
goto asq_send_command_error;
}
details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
if (cmd_details) {
i40e_memcpy(details,
cmd_details,
sizeof(struct i40e_asq_cmd_details),
I40E_NONDMA_TO_NONDMA);
/* If the cmd_details are defined copy the cookie. The
* CPU_TO_LE32 is not needed here because the data is ignored
* by the FW, only used by the driver
*/
if (details->cookie) {
desc->cookie_high =
CPU_TO_LE32(I40E_HI_DWORD(details->cookie));
desc->cookie_low =
CPU_TO_LE32(I40E_LO_DWORD(details->cookie));
}
} else {
i40e_memset(details, 0,
sizeof(struct i40e_asq_cmd_details),
I40E_NONDMA_MEM);
}
/* clear requested flags and then set additional flags if defined */
desc->flags &= ~CPU_TO_LE16(details->flags_dis);
desc->flags |= CPU_TO_LE16(details->flags_ena);
if (buff_size > hw->aq.asq_buf_size) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Invalid buffer size: %d.\n",
buff_size);
status = I40E_ERR_INVALID_SIZE;
goto asq_send_command_error;
}
if (details->postpone && !details->async) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Async flag not set along with postpone flag");
status = I40E_ERR_PARAM;
goto asq_send_command_error;
}
/* call clean and check queue available function to reclaim the
* descriptors that were processed by FW, the function returns the
* number of desc available
*/
/* the clean function called here could be called in a separate thread
* in case of asynchronous completions
*/
if (i40e_clean_asq(hw) == 0) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Error queue is full.\n");
status = I40E_ERR_ADMIN_QUEUE_FULL;
goto asq_send_command_error;
}
/* initialize the temp desc pointer with the right desc */
desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
/* if the desc is available copy the temp desc to the right place */
i40e_memcpy(desc_on_ring, desc, sizeof(struct i40e_aq_desc),
I40E_NONDMA_TO_DMA);
/* if buff is not NULL assume indirect command */
if (buff != NULL) {
dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
/* copy the user buff into the respective DMA buff */
i40e_memcpy(dma_buff->va, buff, buff_size,
I40E_NONDMA_TO_DMA);
desc_on_ring->datalen = CPU_TO_LE16(buff_size);
/* Update the address values in the desc with the pa value
* for respective buffer
*/
desc_on_ring->params.external.addr_high =
CPU_TO_LE32(I40E_HI_DWORD(dma_buff->pa));
desc_on_ring->params.external.addr_low =
CPU_TO_LE32(I40E_LO_DWORD(dma_buff->pa));
}
/* bump the tail */
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
buff, buff_size);
(hw->aq.asq.next_to_use)++;
if (hw->aq.asq.next_to_use == hw->aq.asq.count)
hw->aq.asq.next_to_use = 0;
if (!details->postpone)
wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
/* if cmd_details are not defined or async flag is not set,
* we need to wait for desc write back
*/
if (!details->async && !details->postpone) {
u32 total_delay = 0;
do {
/* AQ designers suggest use of head for better
* timing reliability than DD bit
*/
if (i40e_asq_done(hw))
break;
i40e_usec_delay(50);
total_delay += 50;
} while (total_delay < hw->aq.asq_cmd_timeout);
}
/* if ready, copy the desc back to temp */
if (i40e_asq_done(hw)) {
i40e_memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc),
I40E_DMA_TO_NONDMA);
if (buff != NULL)
i40e_memcpy(buff, dma_buff->va, buff_size,
I40E_DMA_TO_NONDMA);
retval = LE16_TO_CPU(desc->retval);
if (retval != 0) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Command completed with error 0x%X.\n",
retval);
/* strip off FW internal code */
retval &= 0xff;
}
cmd_completed = true;
if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
status = I40E_SUCCESS;
else if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_EBUSY)
status = I40E_ERR_NOT_READY;
else
status = I40E_ERR_ADMIN_QUEUE_ERROR;
hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
}
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: desc and buffer writeback:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
/* save writeback aq if requested */
if (details->wb_desc)
i40e_memcpy(details->wb_desc, desc_on_ring,
sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA);
/* update the error if time out occurred */
if ((!cmd_completed) &&
(!details->async && !details->postpone)) {
#ifdef PF_DRIVER
if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) {
#else
if (rd32(hw, hw->aq.asq.len) & I40E_VF_ATQLEN1_ATQCRIT_MASK) {
#endif
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: AQ Critical error.\n");
status = I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
} else {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: Writeback timeout.\n");
status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
}
}
asq_send_command_error:
i40e_release_spinlock(&hw->aq.asq_spinlock);
return status;
}
/**
* i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
* @desc: pointer to the temp descriptor (non DMA mem)
* @opcode: the opcode can be used to decide which flags to turn off or on
*
* Fill the desc with default values
**/
void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
u16 opcode)
{
/* zero out the desc */
i40e_memset((void *)desc, 0, sizeof(struct i40e_aq_desc),
I40E_NONDMA_MEM);
desc->opcode = CPU_TO_LE16(opcode);
desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_SI);
}
uint8_t SI_Host_OpenSession(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo)
{
if ((USB_HostState != HOST_STATE_Configured) || !(SIInterfaceInfo->State.IsActive))
return PIPE_RWSTREAM_DeviceDisconnected;
uint8_t ErrorCode;
SIInterfaceInfo->State.TransactionID = 0;
SIInterfaceInfo->State.IsSessionOpen = false;
PIMA_Container_t PIMABlock = (PIMA_Container_t)
{
.DataLength = CPU_TO_LE32(PIMA_COMMAND_SIZE(1)),
.Type = CPU_TO_LE16(PIMA_CONTAINER_CommandBlock),
.Code = CPU_TO_LE16(0x1002),
.Params = {CPU_TO_LE32(1)},
};
if ((ErrorCode = SI_Host_SendBlockHeader(SIInterfaceInfo, &PIMABlock)) != PIPE_RWSTREAM_NoError)
return ErrorCode;
if ((ErrorCode = SI_Host_ReceiveBlockHeader(SIInterfaceInfo, &PIMABlock)) != PIPE_RWSTREAM_NoError)
return ErrorCode;
if ((PIMABlock.Type != CPU_TO_LE16(PIMA_CONTAINER_ResponseBlock)) || (PIMABlock.Code != CPU_TO_LE16(0x2001)))
return SI_ERROR_LOGICAL_CMD_FAILED;
SIInterfaceInfo->State.IsSessionOpen = true;
return PIPE_RWSTREAM_NoError;
}
uint8_t SI_Host_CloseSession(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo)
{
if ((USB_HostState != HOST_STATE_Configured) || !(SIInterfaceInfo->State.IsActive))
return PIPE_RWSTREAM_DeviceDisconnected;
uint8_t ErrorCode;
PIMA_Container_t PIMABlock = (PIMA_Container_t)
{
.DataLength = CPU_TO_LE32(PIMA_COMMAND_SIZE(1)),
.Type = CPU_TO_LE16(PIMA_CONTAINER_CommandBlock),
.Code = CPU_TO_LE16(0x1003),
.Params = {CPU_TO_LE32(1)},
};
if ((ErrorCode = SI_Host_SendBlockHeader(SIInterfaceInfo, &PIMABlock)) != PIPE_RWSTREAM_NoError)
return ErrorCode;
if ((ErrorCode = SI_Host_ReceiveBlockHeader(SIInterfaceInfo, &PIMABlock)) != PIPE_RWSTREAM_NoError)
return ErrorCode;
SIInterfaceInfo->State.IsSessionOpen = false;
if ((PIMABlock.Type != CPU_TO_LE16(PIMA_CONTAINER_ResponseBlock)) || (PIMABlock.Code != CPU_TO_LE16(0x2001)))
return SI_ERROR_LOGICAL_CMD_FAILED;
return PIPE_RWSTREAM_NoError;
}
uint8_t SI_Host_SendCommand(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,
const uint16_t Operation,
const uint8_t TotalParams,
uint32_t* const Params)
{
if ((USB_HostState != HOST_STATE_Configured) || !(SIInterfaceInfo->State.IsActive))
return PIPE_RWSTREAM_DeviceDisconnected;
uint8_t ErrorCode;
PIMA_Container_t PIMABlock = (PIMA_Container_t)
{
.DataLength = cpu_to_le32(PIMA_COMMAND_SIZE(TotalParams)),
.Type = CPU_TO_LE16(PIMA_CONTAINER_CommandBlock),
.Code = cpu_to_le16(Operation),
};
memcpy(&PIMABlock.Params, Params, sizeof(uint32_t) * TotalParams);
if ((ErrorCode = SI_Host_SendBlockHeader(SIInterfaceInfo, &PIMABlock)) != PIPE_RWSTREAM_NoError)
return ErrorCode;
return PIPE_RWSTREAM_NoError;
}
uint8_t SI_Host_ReceiveResponse(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo)
{
uint8_t ErrorCode;
PIMA_Container_t PIMABlock;
if ((USB_HostState != HOST_STATE_Configured) || !(SIInterfaceInfo->State.IsActive))
return PIPE_RWSTREAM_DeviceDisconnected;
if ((ErrorCode = SI_Host_ReceiveBlockHeader(SIInterfaceInfo, &PIMABlock)) != PIPE_RWSTREAM_NoError)
return ErrorCode;
if ((PIMABlock.Type != CPU_TO_LE16(PIMA_CONTAINER_ResponseBlock)) || (PIMABlock.Code != CPU_TO_LE16(0x2001)))
return SI_ERROR_LOGICAL_CMD_FAILED;
return PIPE_RWSTREAM_NoError;
}
uint8_t SI_Host_ReceiveBlockHeader(USB_ClassInfo_SI_Host_t* const SIInterfaceInfo,
PIMA_Container_t* const PIMAHeader)
{
uint16_t TimeoutMSRem = SI_COMMAND_DATA_TIMEOUT_MS;
uint16_t PreviousFrameNumber = USB_Host_GetFrameNumber();
if ((USB_HostState != HOST_STATE_Configured) || !(SIInterfaceInfo->State.IsActive))
return PIPE_RWSTREAM_DeviceDisconnected;
Pipe_SelectPipe(SIInterfaceInfo->Config.DataINPipeNumber);
Pipe_Unfreeze();
while (!(Pipe_IsINReceived()))
{
uint16_t CurrentFrameNumber = USB_Host_GetFrameNumber();
if (CurrentFrameNumber != PreviousFrameNumber)
{
PreviousFrameNumber = CurrentFrameNumber;
if (!(TimeoutMSRem--))
return PIPE_RWSTREAM_Timeout;
}
Pipe_Freeze();
Pipe_SelectPipe(SIInterfaceInfo->Config.DataOUTPipeNumber);
Pipe_Unfreeze();
if (Pipe_IsStalled())
{
USB_Host_ClearPipeStall(SIInterfaceInfo->Config.DataOUTPipeNumber);
return PIPE_RWSTREAM_PipeStalled;
}
Pipe_Freeze();
Pipe_SelectPipe(SIInterfaceInfo->Config.DataINPipeNumber);
Pipe_Unfreeze();
if (Pipe_IsStalled())
{
USB_Host_ClearPipeStall(SIInterfaceInfo->Config.DataINPipeNumber);
return PIPE_RWSTREAM_PipeStalled;
}
if (USB_HostState == HOST_STATE_Unattached)
return PIPE_RWSTREAM_DeviceDisconnected;
}
Pipe_Read_Stream_LE(PIMAHeader, PIMA_COMMAND_SIZE(0), NULL);
if (PIMAHeader->Type == CPU_TO_LE16(PIMA_CONTAINER_ResponseBlock))
{
uint8_t ParamBytes = (PIMAHeader->DataLength - PIMA_COMMAND_SIZE(0));
if (ParamBytes)
Pipe_Read_Stream_LE(&PIMAHeader->Params, ParamBytes, NULL);
Pipe_ClearIN();
}
Pipe_Freeze();
return PIPE_RWSTREAM_NoError;
}
static void write_BOOT_PARAM(void)
{
uint32_t spi_API = 0;
uint16_t spi_API16 = 0;
AJ_AlwaysPrintf(("\n\n**************\nTEST: %s\n\n", __FUNCTION__));
// read the clock speed value
spi_API = 0x88888888;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 1, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x42424242;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 2, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x00000000;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 3, FALSE, 4, (uint8_t*)&spi_API);
spi_API = AJ_WSL_SPI_TARGET_CLOCK_SPEED_ADDR; //0x00428878;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ, TRUE, 4, (uint8_t*)&spi_API);
// now read back the value from the data port.
AJ_WSL_SPI_HostControlRegisterRead(AJ_WSL_SPI_TARGET_VALUE, TRUE, 4, (uint8_t*)&spi_API);
spi_API = LE32_TO_CPU(spi_API);
//AJ_InfoPrintf(("cycles read back was %ld \n", spi_API));
// read the flash is present value
{
// let's try this dance of writing multiple times...
spi_API = 0x88888888;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 1, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x42424242;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 2, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x00000000;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 3, FALSE, 4, (uint8_t*)&spi_API);
spi_API = AJ_WSL_SPI_TARGET_FLASH_PRESENT_ADDR; //0x0042880C;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ, TRUE, 4, (uint8_t*)&spi_API);
// now read back the value from the data port.
AJ_WSL_SPI_HostControlRegisterRead(AJ_WSL_SPI_TARGET_VALUE, TRUE, 4, (uint8_t*)&spi_API);
spi_API = LE32_TO_CPU(spi_API);
//AJ_InfoPrintf(("host if flash is present read back was %ld \n", spi_API));
}
// now write out the flash_is_present value
spi_API = 0x00000002;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_VALUE, TRUE, 4, (uint8_t*)&spi_API);
spi_API = 0x88888888;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_WRITE + 1, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x42424242;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_WRITE + 2, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x00000000;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_WRITE + 3, FALSE, 4, (uint8_t*)&spi_API);
spi_API = AJ_WSL_SPI_TARGET_FLASH_PRESENT_ADDR; //0x0042880C;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_WRITE, TRUE, 4, (uint8_t*)&spi_API);
// read the mbox block size
spi_API = 0x88888888;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 1, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x42424242;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 2, FALSE, 4, (uint8_t*)&spi_API);
spi_API = 0x00000000;
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ + 3, FALSE, 4, (uint8_t*)&spi_API);
spi_API = AJ_WSL_SPI_TARGET_MBOX_BLOCKSZ_ADDR; //0x0042886C;
spi_API = CPU_TO_LE32(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_TARGET_ADDR_READ, TRUE, 4, (uint8_t*)&spi_API);
// now read back the value from the data port.
AJ_WSL_SPI_HostControlRegisterRead(AJ_WSL_SPI_TARGET_VALUE, TRUE, 4, (uint8_t*)&spi_API);
spi_API = LE32_TO_CPU(spi_API);
AJ_WSL_MBOX_BLOCK_SIZE = spi_API;
//AJ_InfoPrintf(("block size was %ld \n", spi_API));
spi_API16 = 0x001f;
spi_API16 = CPU_TO_LE16(spi_API16);
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_ENABLE, spi_API16);
// wait until the write has been processed.
spi_API16 = 0;
while (!(spi_API16 & 1)) {
AJ_WSL_SPI_RegisterRead(AJ_WSL_SPI_REG_SPI_STATUS, (uint8_t*)&spi_API16);
spi_API16 = LE16_TO_CPU(spi_API16);
uint16_t space = 0;
AJ_WSL_SPI_RegisterRead(AJ_WSL_SPI_REG_WRBUF_SPC_AVA, (uint8_t*)&space);
}
// clear the read and write interrupt cause register
spi_API = (1 << 9) | (1 << 8);
spi_API = CPU_TO_LE16(spi_API);
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_CAUSE, spi_API);
{
spi_API16 = 0x1;
spi_API16 = CPU_TO_LE16(spi_API16);
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_HOST_CTRL_BYTE_SIZE, spi_API16);
// waiting seems to allow the following write to succeed and thus enable interrupts.
// we need something more deterministic.
AJ_Sleep(1000);
spi_API16 = 0x00FF;
spi_API = CPU_TO_LE16(spi_API);
AJ_WSL_SPI_HostControlRegisterWrite(AJ_WSL_SPI_CPU_INT_STATUS, FALSE, 1, (uint8_t*)&spi_API16);
}
}
/**
* i40e_asq_send_command - send command to Admin Queue
* @hw: pointer to the hw struct
* @desc: prefilled descriptor describing the command (non DMA mem)
* @buff: buffer to use for indirect commands
* @buff_size: size of buffer for indirect commands
* @cmd_details: pointer to command details structure
*
* This is the main send command driver routine for the Admin Queue send
* queue. It runs the queue, cleans the queue, etc
**/
enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
struct i40e_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct i40e_asq_cmd_details *cmd_details)
{
#ifdef I40E_QV
struct i40e_aq_desc qv_desc = {0};
struct i40e_aq_desc *qv_desc_on_ring;
#endif /* I40E_QV */
enum i40e_status_code status = I40E_SUCCESS;
struct i40e_dma_mem *dma_buff = NULL;
struct i40e_asq_cmd_details *details;
struct i40e_aq_desc *desc_on_ring;
bool cmd_completed = FALSE;
u16 retval = 0;
u32 val = 0;
val = rd32(hw, hw->aq.asq.head);
if (val >= hw->aq.num_asq_entries) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: head overrun at %d\n", val);
status = I40E_ERR_QUEUE_EMPTY;
goto asq_send_command_exit;
}
if (hw->aq.asq.count == 0) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: Admin queue not initialized.\n");
status = I40E_ERR_QUEUE_EMPTY;
goto asq_send_command_exit;
}
if (i40e_is_nvm_update_op(desc) && hw->aq.nvm_busy) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: NVM busy.\n");
status = I40E_ERR_NVM;
goto asq_send_command_exit;
}
details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
if (cmd_details) {
i40e_memcpy(details,
cmd_details,
sizeof(struct i40e_asq_cmd_details),
I40E_NONDMA_TO_NONDMA);
/* If the cmd_details are defined copy the cookie. The
* CPU_TO_LE32 is not needed here because the data is ignored
* by the FW, only used by the driver
*/
if (details->cookie) {
desc->cookie_high =
CPU_TO_LE32(I40E_HI_DWORD(details->cookie));
desc->cookie_low =
CPU_TO_LE32(I40E_LO_DWORD(details->cookie));
}
} else {
i40e_memset(details, 0,
sizeof(struct i40e_asq_cmd_details),
I40E_NONDMA_MEM);
}
/* clear requested flags and then set additional flags if defined */
desc->flags &= ~CPU_TO_LE16(details->flags_dis);
desc->flags |= CPU_TO_LE16(details->flags_ena);
i40e_acquire_spinlock(&hw->aq.asq_spinlock);
if (buff_size > hw->aq.asq_buf_size) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Invalid buffer size: %d.\n",
buff_size);
status = I40E_ERR_INVALID_SIZE;
goto asq_send_command_error;
}
if (details->postpone && !details->async) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Async flag not set along with postpone flag");
status = I40E_ERR_PARAM;
goto asq_send_command_error;
}
/* call clean and check queue available function to reclaim the
* descriptors that were processed by FW, the function returns the
* number of desc available
*/
/* the clean function called here could be called in a separate thread
* in case of asynchronous completions
*/
if (i40e_clean_asq(hw) == 0) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Error queue is full.\n");
status = I40E_ERR_ADMIN_QUEUE_FULL;
goto asq_send_command_error;
}
/* initialize the temp desc pointer with the right desc */
desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
/* if the desc is available copy the temp desc to the right place */
i40e_memcpy(desc_on_ring, desc, sizeof(struct i40e_aq_desc),
I40E_NONDMA_TO_DMA);
#ifdef I40E_QV
/* copy the descriptor from ring to userspace buffer */
i40e_memcpy(&qv_desc, desc_on_ring, sizeof(struct i40e_aq_desc),
I40E_DMA_TO_NONDMA);
qv_desc_on_ring = desc_on_ring;
desc_on_ring = &qv_desc;
#endif /* I40E_QV */
/* if buff is not NULL assume indirect command */
if (buff != NULL) {
dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
/* copy the user buff into the respective DMA buff */
i40e_memcpy(dma_buff->va, buff, buff_size,
I40E_NONDMA_TO_DMA);
desc_on_ring->datalen = CPU_TO_LE16(buff_size);
/* Update the address values in the desc with the pa value
* for respective buffer
*/
desc_on_ring->params.external.addr_high =
CPU_TO_LE32(I40E_HI_DWORD(dma_buff->pa));
desc_on_ring->params.external.addr_low =
CPU_TO_LE32(I40E_LO_DWORD(dma_buff->pa));
#ifdef I40E_QV
/* copy the descriptor from userspace buffer to ring */
i40e_memcpy(qv_desc_on_ring, desc_on_ring,
sizeof(struct i40e_aq_desc), I40E_NONDMA_TO_DMA);
#endif /* I40E_QV */
}
/* bump the tail */
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
buff, buff_size);
(hw->aq.asq.next_to_use)++;
if (hw->aq.asq.next_to_use == hw->aq.asq.count)
hw->aq.asq.next_to_use = 0;
if (!details->postpone)
wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
/* if cmd_details are not defined or async flag is not set,
* we need to wait for desc write back
*/
if (!details->async && !details->postpone) {
u32 total_delay = 0;
u32 delay_len = 10;
do {
#ifdef I40E_QV
/* copy the descriptor from ring to user buffer */
i40e_memcpy(desc_on_ring, qv_desc_on_ring,
sizeof(struct i40e_aq_desc), I40E_DMA_TO_NONDMA);
#endif /* I40E_QV */
/* AQ designers suggest use of head for better
* timing reliability than DD bit
*/
if (i40e_asq_done(hw))
break;
/* ugh! delay while spin_lock */
i40e_usec_delay(delay_len);
total_delay += delay_len;
} while (total_delay < hw->aq.asq_cmd_timeout);
}
/* if ready, copy the desc back to temp */
if (i40e_asq_done(hw)) {
#ifdef I40E_QV
/* Swap pointer back */
desc_on_ring = qv_desc_on_ring;
#endif /* I40E_QV */
i40e_memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc),
I40E_DMA_TO_NONDMA);
if (buff != NULL)
i40e_memcpy(buff, dma_buff->va, buff_size,
I40E_DMA_TO_NONDMA);
retval = LE16_TO_CPU(desc->retval);
if (retval != 0) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Command completed with error 0x%X.\n",
retval);
/* strip off FW internal code */
retval &= 0xff;
}
cmd_completed = TRUE;
if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
status = I40E_SUCCESS;
else
status = I40E_ERR_ADMIN_QUEUE_ERROR;
hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
}
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQTX: desc and buffer writeback:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
/* update the error if time out occurred */
if ((!cmd_completed) &&
(!details->async && !details->postpone)) {
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQTX: Writeback timeout.\n");
status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
}
if (!status && i40e_is_nvm_update_op(desc))
hw->aq.nvm_busy = TRUE;
asq_send_command_error:
i40e_release_spinlock(&hw->aq.asq_spinlock);
asq_send_command_exit:
return status;
}
uint8_t AOA_Host_StartAccessoryMode(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo)
{
uint8_t ErrorCode;
uint16_t AccessoryProtocol;
if ((ErrorCode = AOA_Host_GetAccessoryProtocol(&AccessoryProtocol)) != HOST_WAITERROR_Successful)
return ErrorCode;
if (AccessoryProtocol != CPU_TO_LE16(AOA_PROTOCOL_AccessoryV1))
return AOA_ERROR_LOGICAL_CMD_FAILED;
for (uint8_t PropertyIndex = 0; PropertyIndex < AOA_STRING_TOTAL_STRINGS; PropertyIndex++)
{
if ((ErrorCode = AOA_Host_SendPropertyString(AOAInterfaceInfo, PropertyIndex)) != HOST_WAITERROR_Successful)
return ErrorCode;
}
USB_ControlRequest = (USB_Request_Header_t)
{
.bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR | REQREC_DEVICE),
.bRequest = AOA_REQ_StartAccessoryMode,
.wValue = 0,
.wIndex = 0,
.wLength = 0,
};
Pipe_SelectPipe(PIPE_CONTROLPIPE);
return USB_Host_SendControlRequest(NULL);
}
static uint8_t AOA_Host_GetAccessoryProtocol(uint16_t* const Protocol)
{
USB_ControlRequest = (USB_Request_Header_t)
{
.bmRequestType = (REQDIR_DEVICETOHOST | REQTYPE_VENDOR | REQREC_DEVICE),
.bRequest = AOA_REQ_GetAccessoryProtocol,
.wValue = 0,
.wIndex = 0,
.wLength = sizeof(uint16_t),
};
Pipe_SelectPipe(PIPE_CONTROLPIPE);
return USB_Host_SendControlRequest(Protocol);
}
static uint8_t AOA_Host_SendPropertyString(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo,
const uint8_t StringIndex)
{
const char* String = ((char**)&AOAInterfaceInfo->Config.PropertyStrings)[StringIndex];
if (String == NULL)
String = "";
USB_ControlRequest = (USB_Request_Header_t)
{
.bmRequestType = (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR | REQREC_DEVICE),
.bRequest = AOA_REQ_SendString,
.wValue = 0,
.wIndex = StringIndex,
.wLength = (strlen(String) + 1),
};
Pipe_SelectPipe(PIPE_CONTROLPIPE);
return USB_Host_SendControlRequest((char*)String);
}
uint8_t AOA_Host_SendData(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo,
const uint8_t* const Buffer,
const uint16_t Length)
{
if ((USB_HostState != HOST_STATE_Configured) || !(AOAInterfaceInfo->State.IsActive))
return PIPE_READYWAIT_DeviceDisconnected;
uint8_t ErrorCode;
Pipe_SelectPipe(AOAInterfaceInfo->Config.DataOUTPipeNumber);
Pipe_Unfreeze();
ErrorCode = Pipe_Write_Stream_LE(Buffer, Length, NULL);
Pipe_Freeze();
return ErrorCode;
}
uint8_t AOA_Host_SendString(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo,
const char* const String)
{
if ((USB_HostState != HOST_STATE_Configured) || !(AOAInterfaceInfo->State.IsActive))
return PIPE_READYWAIT_DeviceDisconnected;
uint8_t ErrorCode;
Pipe_SelectPipe(AOAInterfaceInfo->Config.DataOUTPipeNumber);
Pipe_Unfreeze();
ErrorCode = Pipe_Write_Stream_LE(String, strlen(String), NULL);
Pipe_Freeze();
return ErrorCode;
}
uint8_t AOA_Host_SendByte(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo,
const uint8_t Data)
{
if ((USB_HostState != HOST_STATE_Configured) || !(AOAInterfaceInfo->State.IsActive))
return PIPE_READYWAIT_DeviceDisconnected;
uint8_t ErrorCode;
Pipe_SelectPipe(AOAInterfaceInfo->Config.DataOUTPipeNumber);
Pipe_Unfreeze();
if (!(Pipe_IsReadWriteAllowed()))
{
Pipe_ClearOUT();
if ((ErrorCode = Pipe_WaitUntilReady()) != PIPE_READYWAIT_NoError)
return ErrorCode;
}
Pipe_Write_8(Data);
Pipe_Freeze();
return PIPE_READYWAIT_NoError;
}
uint16_t AOA_Host_BytesReceived(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo)
{
if ((USB_HostState != HOST_STATE_Configured) || !(AOAInterfaceInfo->State.IsActive))
return 0;
Pipe_SelectPipe(AOAInterfaceInfo->Config.DataINPipeNumber);
Pipe_Unfreeze();
if (Pipe_IsINReceived())
{
if (!(Pipe_BytesInPipe()))
{
Pipe_ClearIN();
Pipe_Freeze();
return 0;
}
else
{
Pipe_Freeze();
return Pipe_BytesInPipe();
}
}
else
{
Pipe_Freeze();
return 0;
}
}
int16_t AOA_Host_ReceiveByte(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo)
{
if ((USB_HostState != HOST_STATE_Configured) || !(AOAInterfaceInfo->State.IsActive))
return -1;
int16_t ReceivedByte = -1;
Pipe_SelectPipe(AOAInterfaceInfo->Config.DataINPipeNumber);
Pipe_Unfreeze();
if (Pipe_IsINReceived())
{
if (Pipe_BytesInPipe())
ReceivedByte = Pipe_Read_8();
if (!(Pipe_BytesInPipe()))
Pipe_ClearIN();
}
Pipe_Freeze();
return ReceivedByte;
}
uint8_t AOA_Host_Flush(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo)
{
if ((USB_HostState != HOST_STATE_Configured) || !(AOAInterfaceInfo->State.IsActive))
return PIPE_READYWAIT_DeviceDisconnected;
uint8_t ErrorCode;
Pipe_SelectPipe(AOAInterfaceInfo->Config.DataOUTPipeNumber);
Pipe_Unfreeze();
if (!(Pipe_BytesInPipe()))
return PIPE_READYWAIT_NoError;
bool BankFull = !(Pipe_IsReadWriteAllowed());
Pipe_ClearOUT();
if (BankFull)
{
if ((ErrorCode = Pipe_WaitUntilReady()) != PIPE_READYWAIT_NoError)
return ErrorCode;
Pipe_ClearOUT();
}
Pipe_Freeze();
return PIPE_READYWAIT_NoError;
}
#if defined(FDEV_SETUP_STREAM)
void AOA_Host_CreateStream(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo,
FILE* const Stream)
{
*Stream = (FILE)FDEV_SETUP_STREAM(AOA_Host_putchar, AOA_Host_getchar, _FDEV_SETUP_RW);
fdev_set_udata(Stream, AOAInterfaceInfo);
}
void AOA_Host_CreateBlockingStream(USB_ClassInfo_AOA_Host_t* const AOAInterfaceInfo,
FILE* const Stream)
{
*Stream = (FILE)FDEV_SETUP_STREAM(AOA_Host_putchar, AOA_Host_getchar_Blocking, _FDEV_SETUP_RW);
fdev_set_udata(Stream, AOAInterfaceInfo);
}
/*------------------------------------------------------------------------------
* CameraControl_DeviceOperation_Capture
*/
uint16_t CameraControl_DeviceOperation_Capture ( USB_ClassInfo_SI_Host_t* SIInterfaceInfo,
PTP_STORETYPE_EN enStorageType,
PTP_FMT_EN enFileFormat )
{
uint8_t iError = 0;
uint32_t iStorageID = 0;
CHECK_CAMERA_CONNECTION;
// Open a new session
iError = CameraControl_OpenSession(SIInterfaceInfo);
if ( iError != PIPE_RWSTREAM_NoError )
{
iError = -1;
goto ExitFunction;
}
// Search for the appropriate storage ID given the type
if ( CameraControl_GetStorageID ( enStorageType, &iStorageID )!=0 )
{
printf_P(PSTR("\r\nStorage not found. Run get_storage_info..."));
iError = -2;
goto ExitFunction;
}
// Initiate capture operation
// OpCode 0x100E (PTP_OC_InitiateCapture)
// Param1 Storage ID
// Param2 Object Format
PIMA_Container_t PIMABlock = (PIMA_Container_t)
{
.DataLength = CPU_TO_LE32(PIMA_COMMAND_SIZE(2)),
.Type = CPU_TO_LE16(PIMA_CONTAINER_CommandBlock),
.Code = CPU_TO_LE16(PTP_OC_InitiateCapture),
.Params = {iStorageID, enFileFormat},
};
iError = CameraControl_InitiateTransaction ( SIInterfaceInfo, &PIMABlock );
if ( iError != PIPE_RWSTREAM_NoError ) goto ExitFunction;
ExitFunction:
// Close the session
iError = CameraControl_CloseSession(SIInterfaceInfo);
if ( iError != PIPE_RWSTREAM_NoError )
{
}
return 0;
}
/*------------------------------------------------------------------------------
* CameraControl_DeviceOperation_GetPropertyDesc
*/
uint16_t CameraControl_DeviceOperation_GetPropertyDesc ( USB_ClassInfo_SI_Host_t* SIInterfaceInfo,
PTP_DEVPROPERTY_EN enPropertyType )
{
/* uint8_t iError = 0;
uint8_t iTemp1 = 0;
uint8_t iTemp2 = 0;
CHECK_CAMERA_CONNECTION;
// Open a new session
iError = CameraControl_OpenSession(SIInterfaceInfo);
if ( iError != PIPE_RWSTREAM_NoError )
{
iError = -1;
return iError;
}
// Initiate capture operation
// OpCode 0x1014 (PTP_OC_GetDevicePropDesc)
PIMA_Container_t PIMABlock = (PIMA_Container_t)
{
.DataLength = CPU_TO_LE32(PIMA_COMMAND_SIZE(1)),
.Type = CPU_TO_LE16(PIMA_CONTAINER_CommandBlock),
.Code = CPU_TO_LE16(PTP_OC_GetDevicePropDesc),
.Params = {enPropertyType},
};
iError = CameraControl_InitiateTransaction ( SIInterfaceInfo, &PIMABlock );
if ( iError != PIPE_RWSTREAM_NoError ) return -1;
// Get the size (in bytes) of the dataset
uint16_t DatasetSize = (PIMABlock.DataLength - PIMA_COMMAND_SIZE(0));
if (DatasetSize==0) return -1;
printf_P(PSTR(ESC_FG_CYAN " Got property info of %d bytes.\r\n" ESC_FG_WHITE), DatasetSize);
// Create a buffer large enough to hold the entire device info
uint8_t Dataset[DatasetSize];
// Read in the data block data
SI_Host_ReadData(SIInterfaceInfo, Dataset, DatasetSize);
// Once all the data has been read, the pipe must be cleared before the response can be sent
Pipe_ClearIN();
// Create a pointer for walking through the info dataset
uint8_t* DatasetPos = Dataset;
iTemp1 = DatasetSize;
// Read out the description
while (iTemp1--)
{
if ( !(iTemp2 % 16) )
{
putchar('\r'); putchar('\n');
}
printf_P ( PSTR("%02x "), *DatasetPos );
DatasetPos++;
iTemp2++;
}
putchar('\r'); putchar('\n');
// Receive the final response block from the device
iError = CameraControl_GetResponseAndCheck (SIInterfaceInfo, &PIMABlock);
// Close the session
iError = CameraControl_CloseSession(SIInterfaceInfo);
if ( iError != PIPE_RWSTREAM_NoError )
{
}
return 0;*/
return 0;
}
/*------------------------------------------------------------------------------
* CameraControl_DeviceOperation_GetPropertyDesc
*/
uint16_t CameraControl_DeviceOperation_GetPropertyDescBin ( USB_ClassInfo_SI_Host_t* SIInterfaceInfo,
PTP_DEVPROPERTY_EN enPropertyType, uint16_t transID )
{
return CameraControl_GeneralStream_Bin (SIInterfaceInfo,
PTP_OC_GetDevicePropDesc,
enPropertyType,
0,
0,
1,
TP_DATA_PROP_DESC,
transID );
}
/*------------------------------------------------------------------------------
* CameraControl_DeviceOperation_GetPropertyValBin
*/
uint16_t CameraControl_DeviceOperation_GetPropertyValBin ( USB_ClassInfo_SI_Host_t* SIInterfaceInfo,
PTP_DEVPROPERTY_EN enPropertyType, uint16_t transID )
{
return CameraControl_GeneralStream_Bin (SIInterfaceInfo,
PTP_OC_GetDevicePropValue,
enPropertyType,
0,
0,
1,
TP_DATA_PROP_VAL,
transID );
}
/*------------------------------------------------------------------------------
* CameraControl_GetPropertyVal32Bit
*/
uint16_t CameraControl_GetPropertyVal32Bit ( USB_ClassInfo_SI_Host_t* SIInterfaceInfo, PTP_DEVPROPERTY_EN enPropertyType, uint32_t *iVal )
{
uint16_t ReturnedDataSize;
uint8_t ErrorCode = 0;
uint8_t RecData[16] = {0};
CHECK_CAMERA_CONNECTION;
SIInterfaceInfo->State.TransactionID = 0;
// Create PIMA message block
PIMA_Container_t PIMABlock = (PIMA_Container_t)
{
.DataLength = CPU_TO_LE32(PIMA_COMMAND_SIZE(1)),
.Type = CPU_TO_LE16(PIMA_CONTAINER_CommandBlock),
.Code = CPU_TO_LE16(PTP_OC_GetDevicePropValue),
.TransactionID = CPU_TO_LE32(0x00000000),
.Params = {enPropertyType},
};
ErrorCode = CameraControl_InitiateTransaction ( SIInterfaceInfo, &PIMABlock );
// Get the size (in bytes) of the device info structure
ReturnedDataSize = (PIMABlock.DataLength - PIMA_COMMAND_SIZE(0));
ReturnedDataSize = (ReturnedDataSize>16)?16:ReturnedDataSize;
SI_Host_ReadData(SIInterfaceInfo, RecData, ReturnedDataSize);
// Once all the data has been read, the pipe must be cleared before the response can be sent
Pipe_ClearIN();
uint8_t * temp = (uint8_t*)((void*)(iVal));
temp[0] = RecData[0];
temp[1] = RecData[1];
temp[2] = RecData[2];
temp[3] = RecData[3];
// Receive the final response block from the device
CameraControl_GetResponseAndCheck (SIInterfaceInfo, &PIMABlock);
return 0;
}
/*------------------------------------------------------------------------------
* CameraControl_DeviceOperation_SetPropertyValBin
*/
uint16_t CameraControl_DeviceOperation_SetPropertyValBin ( USB_ClassInfo_SI_Host_t* SIInterfaceInfo,
PTP_DEVPROPERTY_EN enPropertyType, uint32_t val )
{
uint16_t SentDataSize;
uint8_t ErrorCode = 0;
uint8_t *SentData = ((uint8_t*)((void*)(&val)));
CHECK_CAMERA_CONNECTION;
SIInterfaceInfo->State.TransactionID = 0;
// Set the size (in bytes) of the device property val
if (enPropertyType==TP_PROPERTY_EVENT_ExposureTime||enPropertyType==TP_PROPERTY_EVENT_FocalLength) // 32 bits
SentDataSize = 4;
else SentDataSize = 2; // 16 bits
// Create PIMA message block
PIMA_Container_t PIMABlock = (PIMA_Container_t)
{
.DataLength = CPU_TO_LE32(PIMA_COMMAND_SIZE(1)+SentDataSize),
.Type = CPU_TO_LE16(PIMA_CONTAINER_CommandBlock),
.Code = CPU_TO_LE16(PTP_OC_SetDevicePropValue),
.TransactionID = CPU_TO_LE32(0x00000000),
.Params = {enPropertyType},
};
ErrorCode = CameraControl_InitiateTransaction ( SIInterfaceInfo, &PIMABlock );
SI_Host_ReadData(SIInterfaceInfo, SentData, SentDataSize);
// Receive the final response block from the device
CameraControl_GetResponseAndCheck (SIInterfaceInfo, &PIMABlock);
return 0;
}
/**
* i40e_clean_arq_element
* @hw: pointer to the hw struct
* @e: event info from the receive descriptor, includes any buffers
* @pending: number of events that could be left to process
*
* This function cleans one Admin Receive Queue element and returns
* the contents through e. It can also return how many events are
* left to process through 'pending'
**/
enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
struct i40e_arq_event_info *e,
u16 *pending)
{
enum i40e_status_code ret_code = I40E_SUCCESS;
u16 ntc = hw->aq.arq.next_to_clean;
struct i40e_aq_desc *desc;
struct i40e_dma_mem *bi;
u16 desc_idx;
u16 datalen;
u16 flags;
u16 ntu;
/* pre-clean the event info */
i40e_memset(&e->desc, 0, sizeof(e->desc), I40E_NONDMA_MEM);
/* take the lock before we start messing with the ring */
i40e_acquire_spinlock(&hw->aq.arq_spinlock);
if (hw->aq.arq.count == 0) {
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
"AQRX: Admin queue not initialized.\n");
ret_code = I40E_ERR_QUEUE_EMPTY;
goto clean_arq_element_err;
}
/* set next_to_use to head */
#ifdef INTEGRATED_VF
if (!i40e_is_vf(hw))
ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
else
ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
#else
#ifdef PF_DRIVER
ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK;
#endif /* PF_DRIVER */
#ifdef VF_DRIVER
ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK;
#endif /* VF_DRIVER */
#endif /* INTEGRATED_VF */
if (ntu == ntc) {
/* nothing to do - shouldn't need to update ring's values */
ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
goto clean_arq_element_out;
}
/* now clean the next descriptor */
desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
desc_idx = ntc;
hw->aq.arq_last_status =
(enum i40e_admin_queue_err)LE16_TO_CPU(desc->retval);
flags = LE16_TO_CPU(desc->flags);
if (flags & I40E_AQ_FLAG_ERR) {
ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
i40e_debug(hw,
I40E_DEBUG_AQ_MESSAGE,
"AQRX: Event received with error 0x%X.\n",
hw->aq.arq_last_status);
}
i40e_memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc),
I40E_DMA_TO_NONDMA);
datalen = LE16_TO_CPU(desc->datalen);
e->msg_len = min(datalen, e->buf_len);
if (e->msg_buf != NULL && (e->msg_len != 0))
i40e_memcpy(e->msg_buf,
hw->aq.arq.r.arq_bi[desc_idx].va,
e->msg_len, I40E_DMA_TO_NONDMA);
i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
hw->aq.arq_buf_size);
/* Restore the original datalen and buffer address in the desc,
* FW updates datalen to indicate the event message
* size
*/
bi = &hw->aq.arq.r.arq_bi[ntc];
i40e_memset((void *)desc, 0, sizeof(struct i40e_aq_desc), I40E_DMA_MEM);
desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_BUF);
if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
desc->flags |= CPU_TO_LE16(I40E_AQ_FLAG_LB);
desc->datalen = CPU_TO_LE16((u16)bi->size);
desc->params.external.addr_high = CPU_TO_LE32(I40E_HI_DWORD(bi->pa));
desc->params.external.addr_low = CPU_TO_LE32(I40E_LO_DWORD(bi->pa));
/* set tail = the last cleaned desc index. */
wr32(hw, hw->aq.arq.tail, ntc);
/* ntc is updated to tail + 1 */
ntc++;
if (ntc == hw->aq.num_arq_entries)
ntc = 0;
hw->aq.arq.next_to_clean = ntc;
hw->aq.arq.next_to_use = ntu;
#ifdef PF_DRIVER
i40e_nvmupd_check_wait_event(hw, LE16_TO_CPU(e->desc.opcode), &e->desc);
#endif /* PF_DRIVER */
clean_arq_element_out:
/* Set pending if needed, unlock and return */
if (pending != NULL)
*pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
clean_arq_element_err:
i40e_release_spinlock(&hw->aq.arq_spinlock);
return ret_code;
}
AJ_Status AJ_WSL_SPI_HostControlRegisterRead(uint32_t targetRegister, uint8_t increment, uint16_t cbLen, uint8_t* spi_data)
{
aj_spi_status rc;
wsl_spi_command send;
AJ_Status status = AJ_ERR_SPI_WRITE;
uint8_t pcs = AJ_WSL_SPI_PCS;
// write the size
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_HOST_CTRL_BYTE_SIZE, cbLen | (increment ? 0 : 0x40));
// now send the host_control_config register update
{
uint16_t externalRegister = 0;
externalRegister = (1 << 15) | (0 << 14) | (targetRegister); // external access, write, counter dec
externalRegister = CPU_TO_LE16(externalRegister);
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_HOST_CTRL_CONFIG, externalRegister);
}
// get the spi status
{
uint16_t spi_16 = 0;
AJ_WSL_SPI_RegisterRead(AJ_WSL_SPI_REG_SPI_STATUS, (uint8_t*)&spi_16);
spi_16 = LE16_TO_CPU(spi_16);
}
// initialize an SPI CMD structure with the register of interest
send.cmd_rx = AJ_WSL_SPI_READ;
send.cmd_reg = AJ_WSL_SPI_INTERNAL;
send.cmd_addr = AJ_WSL_SPI_REG_HOST_CTRL_RD_PORT;
// write the register, one byte at a time, in the right order
rc = AJ_SPI_WRITE(AJ_WSL_SPI_DEVICE, *((uint8_t*)&send + 1), AJ_WSL_SPI_PCS, AJ_WSL_SPI_CONTINUE);
AJ_ASSERT(rc == SPI_OK);
rc = AJ_SPI_READ(AJ_WSL_SPI_DEVICE, spi_data, &pcs); // toss.
AJ_ASSERT(rc == SPI_OK);
rc = AJ_SPI_WRITE(AJ_WSL_SPI_DEVICE, *(uint8_t*)&send, AJ_WSL_SPI_PCS, AJ_WSL_SPI_END);
AJ_ASSERT(rc == SPI_OK);
rc = AJ_SPI_READ(AJ_WSL_SPI_DEVICE, spi_data, &pcs); // toss.
AJ_ASSERT(rc == SPI_OK);
// now, read the data back
if (rc == SPI_OK) {
while ((rc == SPI_OK) && (cbLen > 1)) {
/* Test read: should return OK with what is sent. */
rc = AJ_SPI_WRITE(AJ_WSL_SPI_DEVICE, 0, AJ_WSL_SPI_PCS, AJ_WSL_SPI_CONTINUE);
AJ_ASSERT(rc == SPI_OK);
rc = AJ_SPI_READ(AJ_WSL_SPI_DEVICE, spi_data, &pcs);
AJ_ASSERT(rc == SPI_OK);
spi_data++;
cbLen = cbLen - 1;
}
if (rc == SPI_OK) {
rc = AJ_SPI_WRITE(AJ_WSL_SPI_DEVICE, 0, AJ_WSL_SPI_PCS, AJ_WSL_SPI_END);
AJ_ASSERT(rc == SPI_OK);
rc = AJ_SPI_READ(AJ_WSL_SPI_DEVICE, spi_data, &pcs);
AJ_ASSERT(rc == SPI_OK);
}
if (rc == SPI_OK) {
status = AJ_OK;
}
}
// clear the rd/wr buffer interrupt
{
uint16_t spi_16 = 0x300;
spi_16 = CPU_TO_LE16(spi_16);
AJ_WSL_SPI_RegisterWrite(AJ_WSL_SPI_REG_INTR_CAUSE, spi_16);
}
return status;
}
/**
* i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
* @hw: pointer to the hardware structure
**/
STATIC enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw)
{
enum i40e_status_code ret_code;
struct i40e_aq_desc *desc;
struct i40e_dma_mem *bi;
int i;
/* We'll be allocating the buffer info memory first, then we can
* allocate the mapped buffers for the event processing
*/
/* buffer_info structures do not need alignment */
ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head,
(hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem)));
if (ret_code)
goto alloc_arq_bufs;
hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va;
/* allocate the mapped buffers */
for (i = 0; i < hw->aq.num_arq_entries; i++) {
bi = &hw->aq.arq.r.arq_bi[i];
ret_code = i40e_allocate_dma_mem(hw, bi,
i40e_mem_arq_buf,
hw->aq.arq_buf_size,
I40E_ADMINQ_DESC_ALIGNMENT);
if (ret_code)
goto unwind_alloc_arq_bufs;
/* now configure the descriptors for use */
desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
desc->flags = CPU_TO_LE16(I40E_AQ_FLAG_BUF);
if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
desc->flags |= CPU_TO_LE16(I40E_AQ_FLAG_LB);
desc->opcode = 0;
/* This is in accordance with Admin queue design, there is no
* register for buffer size configuration
*/
desc->datalen = CPU_TO_LE16((u16)bi->size);
desc->retval = 0;
desc->cookie_high = 0;
desc->cookie_low = 0;
desc->params.external.addr_high =
CPU_TO_LE32(I40E_HI_DWORD(bi->pa));
desc->params.external.addr_low =
CPU_TO_LE32(I40E_LO_DWORD(bi->pa));
desc->params.external.param0 = 0;
desc->params.external.param1 = 0;
}
alloc_arq_bufs:
return ret_code;
unwind_alloc_arq_bufs:
/* don't try to free the one that failed... */
i--;
for (; i >= 0; i--)
i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
i40e_free_virt_mem(hw, &hw->aq.arq.dma_head);
return ret_code;
}
* device characteristics, including the supported USB version, control endpoint size and the
* number of device configurations. The descriptor is read out by the USB host when the enumeration
* process begins.
*/
const USB_Descriptor_Device_t PROGMEM DeviceDescriptor =
{
.Header = {.Size = sizeof(USB_Descriptor_Device_t), .Type = DTYPE_Device},
.USBSpecification = VERSION_BCD(01.10),
.Class = USB_CSCP_NoDeviceClass,
.SubClass = USB_CSCP_NoDeviceSubclass,
.Protocol = USB_CSCP_NoDeviceProtocol,
.Endpoint0Size = FIXED_CONTROL_ENDPOINT_SIZE,
.VendorID = CPU_TO_LE16(0x03EB),
.ProductID = CPU_TO_LE16(0x2041),
.ReleaseNumber = VERSION_BCD(00.02),
.ManufacturerStrIndex = 0x01,
.ProductStrIndex = 0x02,
.SerialNumStrIndex = NO_DESCRIPTOR,
.NumberOfConfigurations = FIXED_NUM_CONFIGURATIONS
};
/** Configuration descriptor structure. This descriptor, located in FLASH memory, describes the usage
* of the device in one of its supported configurations, including information about any device interfaces
* and endpoints. The descriptor is read out by the USB host during the enumeration process when selecting
* a configuration so that the host may correctly communicate with the USB device.
*/
bstreamhandle
open_wav_read_stream(char *fname)
{
bstreamhandle h;
int fd, sav;
Wave_filehdr *wav;
struct stat st;
uint32_t data_size;
wav = NULL;
str_errno = 0;
fd = open(fname, O_RDONLY);
if (fd < 0)
return (NULL);
if (fstat(fd, &st) < 0) {
goto wav_open_failed;
}
if ((st.st_mode & S_IFMT) != S_IFREG) {
str_errno = STR_ERR_NO_REG_FILE;
goto wav_open_failed;
}
wav = (Wave_filehdr *)my_zalloc(sizeof (*wav));
if (read(fd, wav, sizeof (*wav)) != sizeof (*wav)) {
str_errno = STR_ERR_WAV_READ_ERR;
goto wav_open_failed;
}
if ((strncmp(wav->riff, "RIFF", 4) != 0) ||
(strncmp(wav->wave, "WAVE", 4) != 0)) {
str_errno = STR_ERR_WAV_BAD_HEADER;
goto wav_open_failed;
}
if (((CPU_TO_LE32(wav->total_chunk_size) + 8) != st.st_size) ||
(strncmp(wav->fmt, "fmt ", 4) != 0) ||
(CPU_TO_LE16(wav->fmt_tag) != 1) ||
(CPU_TO_LE16(wav->n_channels) != 2) ||
(CPU_TO_LE32(wav->sample_rate) != 44100) ||
(CPU_TO_LE16(wav->bits_per_sample) != 16) ||
(strncmp(wav->data, "data", 4) != 0) ||
((CPU_TO_LE32(wav->data_size) + 44) != st.st_size)) {
str_errno = STR_ERR_WAV_UNSUPPORTED_FORMAT;
goto wav_open_failed;
}
data_size = CPU_TO_LE32(wav->data_size);
if (lseek(fd, sizeof (*wav), SEEK_SET) < 0) {
goto wav_open_failed;
}
free(wav);
h = (bstreamhandle)my_zalloc(sizeof (*h));
h->bstr_fd = fd;
h->bstr_read = file_stream_read;
h->bstr_close = file_stream_close;
h->bstr_size = audio_stream_size;
h->bstr_rewind = wav_stream_rewind;
h->bstr_private = (void *)data_size;
return (h);
wav_open_failed:
sav = errno;
(void) close(fd);
if (wav != NULL)
free(wav);
errno = sav;
return (NULL);
}
* device characteristics, including the supported USB version, control endpoint size and the
* number of device configurations. The descriptor is read out by the USB host when the enumeration
* process begins.
*/
const USB_Descriptor_Device_t PROGMEM DeviceDescriptor =
{
.Header = {.Size = sizeof(USB_Descriptor_Device_t), .Type = DTYPE_Device},
.USBSpecification = VERSION_BCD(02.00),
.Class = USB_CSCP_NoDeviceClass,
.SubClass = USB_CSCP_NoDeviceSubclass,
.Protocol = USB_CSCP_NoDeviceProtocol,
.Endpoint0Size = FIXED_CONTROL_ENDPOINT_SIZE,
.VendorID = CPU_TO_LE16(0x03EB),
.ProductID = CPU_TO_LE16(0x2046),
.ReleaseNumber = VERSION_BCD(00.02),
.ManufacturerStrIndex = 0x01,
.ProductStrIndex = 0x02,
.SerialNumStrIndex = NO_DESCRIPTOR,
.NumberOfConfigurations = FIXED_NUM_CONFIGURATIONS
};
/** Configuration descriptor structure. This descriptor, located in FLASH memory, describes the usage
* of the device in one of its supported configurations, including information about any device interfaces
* and endpoints. The descriptor is read out by the USB host during the enumeration process when selecting
* a configuration so that the host may correctly communicate with the USB device.
*/
