/*************************************************************************
* @b EVM_init()
*
* @n
*
* Initializes the platform hardware. This routine is configured to start in
* the evm.cfg configuration file. It is the first routine that BIOS
* calls and is executed before Main is called. If you are debugging within
* CCS the default option in your target configuration file may be to execute
* all code up until Main as the image loads. To debug this you should disable
* that option.
*
* @param[in] None
*
* @retval
* None
************************************************************************/
void EVM_init()
{
platform_init_flags sFlags;
platform_init_config sConfig;
/* Status of the call to initialize the platform */
int32_t pform_status;
/* Platform Information - we will read it form the Platform Library */
platform_info sPlatformInfo;
int core;
/*
* You can choose what to initialize on the platform by setting the following
* flags. Things like the DDR, PLL, etc should have been set by the boot loader.
*/
memset( (void *) &sFlags, 0, sizeof(platform_init_flags));
memset( (void *) &sConfig, 0, sizeof(platform_init_config));
sFlags.pll = 0; /* PLLs for clocking */
sFlags.ddr = 0; /* External memory */
sFlags.tcsl = 1; /* Time stamp counter */
sFlags.phy = 1; /* Ethernet */ //ToDo: Shouldn't this better be 0 ?
sFlags.ecc = 0; /* Memory ECC */
sConfig.pllm = 0; /* Use libraries default clock divisor */
pform_status = platform_init(&sFlags, &sConfig);
/* If we initialized the platform okay */
if (pform_status == Platform_EOK) {
/* Get information about the platform so we can use it in various places */
memset( (void *) &sPlatformInfo, 0, sizeof(platform_info));
platform_get_info(&sPlatformInfo);
number_of_cores = sPlatformInfo.cpu.core_count;
MultiProc_setLocalId((Uint16) platform_get_coreid());
} else {
/* Initialization of the platform failed... die */
logout("Platform failed to initialize. Error code %d \n", pform_status);
while (1) {
(void) platform_led(1, PLATFORM_LED_ON, PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
(void) platform_led(1, PLATFORM_LED_OFF, PLATFORM_USER_LED_CLASS);
(void) platform_delay(50000);
}
}
/* Unlock the chip registers */
CSL_BootCfgUnlockKicker();
/* wake up the other core to run slave part */
for (core = 1; core < CORE_AMOUNT; core++)
{
/* IPC interrupt other cores */
DEVICE_REG32_W(IPCGR(core), 1);
platform_delay(1000);
}
}
/**
* @brief
* Configure the sgmii Serdes on devices using the initialization sequence
*/
void configSerdes()
{
/* Unlock the chip configuration registers to allow SGMII SERDES registers to
* be written */
CSL_BootCfgUnlockKicker();
/* Configure the SERDES */
/* Multiply to be 8 with Quarter Rate in the Rx registers */
CSL_BootCfgSetSGMIIConfigPLL (0x00000041);
platform_delaycycles(100);
//31:25 Reserved 0000000
//23:24 LOOPBACK 00
// 22 ENOC 1
//21:18 EQ 0001
//17:15 CDR 001 -- first order threshold of 17
//14:12 LOS 000 -- tie off
//11:10 ALIGN 01 -- Comma Aligned
//09:07 TERM 100 -- tie off (100)
// 06 INVPAIR 0
//05:04 RATE 01 -- tie off (10) //00 = Full Rate, 01 = Half Rate (*0.5), 10 = Quarter Rate (*0.25)
//03:01 BUSWIDTH 000 -- tie off
// 00 ENRX 1
// 0000 0000 0100 0100 0000 0010 0001 0001 = 0x0044_0211 -- My estimated value
// 0000 0000 0100 0100 0000 0100 0001 0001 = 0x0044_0411 -- New DV value
// 0000 0000 0000 1000 0000 1000 0100 0001 = 0x0008_0841 -- Original DV value
CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621);
CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621);
//31:22 Reserved 0
//21:20 LOOPBACK 00
//19:18 RDTCT 00 -- tie off
// 17 ENIDL 0 -- tie off
// 16 MYSNC 1 -- tie off
//15:12 DEMPHASIS ???? - 0001 Lets give some de-emphasis
//11:08 SWING ????
// 07 CM 1 -- tie off
// 06 INVPAIR 0
//05:04 RATE 01 -- tie off
//03:01 BUSWIDTH 000 -- tie off
// 00 ENTX 1
// 0000 0000 0011 0001 ???? ???? 1001 0001 = 0x0031_1E91 -- My estimated value
// 0000 0000 0000 0001 0000 1111 0001 0001 = 0x0001_0F11 -- New DV value
// 0000 0000 0100 0000 0001 1110 0100 0001 = 0x0040_1e41 -- Original DV value
CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1);
CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1);
/* All done with configuration. Return Now. */
return;
}
/** ============================================================================
* @n@b Init_SGMII_SERDES
*
* @b Description
* @n This API sets up the configuration for the SGMII SERDES. Assumes a 125 MHz
* reference clock.
*
* @param[in]
* @n None
*
* @return
* @n None
* =============================================================================
*/
Int32 Init_SGMII_SERDES(Void)
{
CSL_SGMII_STATUS sgmii_status;
/*
* The following SERDES configuration is required for chip simulator only.
* The platform-dependent SERDES configuration should be done by the corresponding
* CCS GEL scripts or platformLib
*/
//if (cpswSimTest)
//{
/* Unlock the chip configuration registers to allow SGMII SERDES registers to
* be written */
CSL_BootCfgUnlockKicker();
CSL_BootCfgSetSGMIIConfigPLL (0x00000041);
CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621);
CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1);
CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621);
CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1);
/* Re-lock the chip configuration registers to prevent unintentional writes */
CSL_BootCfgLockKicker();
// }
/* Poll the SGMII0 lock bit to confirm that the sgmii module has recognized
that the SERDES PLL has locked */
do
{
CSL_SGMII_getStatus(0, &sgmii_status);
} while (sgmii_status.bIsLocked != 1);
/* Poll the SGMII1 lock bit to confirm that the sgmii module has recognized
that the SERDES PLL has locked */
do
{
CSL_SGMII_getStatus(1, &sgmii_status);
} while (sgmii_status.bIsLocked != 1);
//platform_write("serdes PLL locked for both PHY \n");
/* SGMII SERDES Configuration complete. Return. */
return 0;
}
/**
* @brief
* Configure the sgmii Serdes on devices using the initialization sequence
*/
void configSerdes()
{
CSL_SGMII_STATUS sgmii_status;
uint32_t loopCount;
/* Unlock the chip configuration registers to allow SGMII SERDES registers to
* be written */
CSL_BootCfgUnlockKicker();
/* Configure the SERDES */
/* Multiply to be 8 with Quarter Rate in the Rx registers */
CSL_BootCfgSetSGMIIConfigPLL (0x00000051);
loopCount = 100;
while (loopCount--) {
asm(" NOP");
}
//31:25 Reserved 0000000
//23:24 LOOPBACK 00
// 22 ENOC 1
//21:18 EQ 0001
//17:15 CDR 001 -- first order threshold of 17
//14:12 LOS 000 -- tie off
//11:10 ALIGN 01 -- Comma Aligned
//09:07 TERM 100 -- tie off (100)
// 06 INVPAIR 0
//05:04 RATE 01 -- tie off (10) //00 = Full Rate, 01 = Half Rate (*0.5), 10 = Quarter Rate (*0.25)
//03:01 BUSWIDTH 000 -- tie off
// 00 ENRX 1
// 0000 0000 0100 0100 0000 0010 0001 0001 = 0x0044_0211 -- My estimated value
// 0000 0000 0100 0100 0000 0100 0001 0001 = 0x0044_0411 -- New DV value
// 0000 0000 0000 1000 0000 1000 0100 0001 = 0x0008_0841 -- Original DV value
CSL_BootCfgSetSGMIIRxConfig (0, 0x00700621);
CSL_BootCfgSetSGMIIRxConfig (1, 0x00700621);
//31:22 Reserved 0
//21:20 LOOPBACK 00
//19:18 RDTCT 00 -- tie off
// 17 ENIDL 0 -- tie off
// 16 MYSNC 1 -- tie off
//15:12 DEMPHASIS ???? - 0001 Lets give some de-emphasis
//11:08 SWING ????
// 07 CM 1 -- tie off
// 06 INVPAIR 0
//05:04 RATE 01 -- tie off
//03:01 BUSWIDTH 000 -- tie off
// 00 ENTX 1
// 0000 0000 0011 0001 ???? ???? 1001 0001 = 0x0031_1E91 -- My estimated value
// 0000 0000 0000 0001 0000 1111 0001 0001 = 0x0001_0F11 -- New DV value
// 0000 0000 0100 0000 0001 1110 0100 0001 = 0x0040_1e41 -- Original DV value
CSL_BootCfgSetSGMIITxConfig (0, 0x000108A1);
CSL_BootCfgSetSGMIITxConfig (1, 0x000108A1);
/* Poll the SGMII0 lock bit to confirm that the sgmii module has recognized
that the SERDES PLL has locked */
do
{
CSL_SGMII_getStatus(0, &sgmii_status);
} while (sgmii_status.bIsLocked != 1);
/* Poll the SGMII1 lock bit to confirm that the sgmii module has recognized
that the SERDES PLL has locked */
do
{
CSL_SGMII_getStatus(1, &sgmii_status);
} while (sgmii_status.bIsLocked != 1);
/* All done with configuration. Return Now. */
return;
}
void KeyStone_main_PLL_init ( unsigned int main_PLLM, unsigned int main_PLLD)
{
unsigned int i;
if(0<main_PLLM&&main_PLLM<=4096&&0<main_PLLD&&main_PLLD<=64)
{
CSL_BootCfgUnlockKicker();
boot_cfg_regs->CORE_PLL_CTL1 |= 0x00000040; //Set ENSAT = 1
printf("Initialize main PLL = x%d/%d\n", main_PLLM, main_PLLD);
//Bypass the PLL, PLL OUTPUT_DIVIDER = 2
pllc_regs->SECCTL |= 0x00880000;
/*Clear the PLLENSRC bit in PLLCTL to 0 to allow PLLCTL.PLLEN to take effect*/
pllc_regs->PLLCTL= pllc_regs->PLLCTL&(~(1<<5));
/*Clear the PLLEN bit in PLLCTL to 0 (select PLL bypass mode)*/
pllc_regs->PLLCTL= pllc_regs->PLLCTL&(~(1<<0));
/*Wait for 4 input clock cycles to ensure PLLC switches to bypass mode properly*/
for(i=0; i< 4*8192/5+1; i++)
asm(" nop 5");
/*The PLL has a bandgap generator circuit driving the PLL voltage regulator. In order
to ensure proper PLL startup, the PLL power_down pin needs to be toggled. This is
accomplished by toggling the ¡°PLLPWRDN¡± bit in the PLLCTL register. This needs to
be done before the main PLL initialization sequence. */
pllc_regs->PLLCTL |= (1<<1); //Power down the PLL
// wait for 5 us (min)
for(i=0; i< 1000; i++)
asm(" nop 5");
// Verify if pll is in power down
if ((pllc_regs->PLLCTL & (1<<1)) !=0 )
{
pllc_regs->PLLCTL &= ~(1<<1); // Power up PLL
// Wait PLL Stabilization time that is 150 usec
for(i=0; i< 30000; i++)
asm(" nop 5");
}
/*In PLLCTL, write PLLRST = 1 (PLL is reset)*/
pllc_regs->PLLCTL= pllc_regs->PLLCTL|(1<<3);
/*Program the required multiplier and divider values*/
//pllc_regs->PREDIV= 0x8000;
/*PLLM[5:0] bits of the multiplier is controlled by the PLLM
register inside the PLL controller and PLLM[12:6] bits are
controlled by the chip level register. MAINPLLCTL0 register
PLLM[12:6] bits should be written just before writing to PLLM
register PLLM[5:0] bits in the controller to have the complete
13 bit value latched when the GO operation is initiated in the
PLL controller.*/
boot_cfg_regs->CORE_PLL_CTL0 = ((main_PLLM-1)<<24)| /*BWADJ[7:0]*/
(((main_PLLM*2-1)&0x1FC0)<<6)|(main_PLLD-1);
pllc_regs->PLLM= (main_PLLM*2-1)&0x3F;
boot_cfg_regs->CORE_PLL_CTL1 = 0x00000040 /*Set ENSAT bit = 1*/
|(main_PLLM-1)>>8; /*BWADJ[11:8]*/
//pllc_regs->POSTDIV= 0x8000;
/*Wait 1000 ns for PLL reset*/
for(i=0; i< 1500/5+1; i++)
asm(" nop 5");
/*In PLLCTL, write PLLRST = 0 to bring PLL out of reset*/
pllc_regs->PLLCTL= pllc_regs->PLLCTL&(~(1<<3));
/*Wait 2000 input clock cycles for PLL to lock*/
for(i=0; i< 2000*8192/5+1; i++)
asm(" nop 5");
//clear the bypass bit, enable PLL
pllc_regs->SECCTL &= ~(0x00800000);
/*Set the PLLEN bit in PLLCTL to 1 to enable PLL mode*/
pllc_regs->PLLCTL= pllc_regs->PLLCTL|(1<<0);
}
