// Clock gating for unused peripherals
void ClockGating(void)
{
Uint16 pcgcr_value, clkstop_value;
// set PCGCR1
pcgcr_value = 0;
// clock gating SPI
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_SPICG, DISABLED);
// clock gating SD/MMC
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_MMCSD0CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_MMCSD0CG, DISABLED);
// clock stop request for UART
clkstop_value = CSL_FMKT(SYS_CLKSTOP_URTCLKSTPREQ, REQ);
// write to CLKSTOP
CSL_FSET(CSL_SYSCTRL_REGS->CLKSTOP, 15, 0, clkstop_value);
// wait for acknowledge
while (CSL_FEXT(CSL_SYSCTRL_REGS->CLKSTOP, SYS_CLKSTOP_URTCLKSTPACK)==0);
// clock gating UART
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_UARTCG, DISABLED);
// clock stop request for EMIF
//clkstop_value = CSL_FMKT(SYS_CLKSTOP_EMFCLKSTPREQ, REQ);
// write to CLKSTOP
//CSL_FSET(CSL_SYSCTRL_REGS->CLKSTOP, 15, 0, clkstop_value);
// wait for acknowledge
//while (CSL_FEXT(CSL_SYSCTRL_REGS->CLKSTOP, SYS_CLKSTOP_EMFCLKSTPACK)==0);
// clock gating EMIF
//pcgcr_value |= CSL_FMKT(SYS_PCGCR1_EMIFCG, DISABLED);
// clock gating unused I2S (I2S 0, 1, 3)
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S0CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S1CG, DISABLED);
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_I2S3CG, DISABLED);
// clcok gating DMA0
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_DMA0CG, DISABLED);
// clcok gating Timer 1
//pcgcr_value |= CSL_FMKT(SYS_PCGCR1_TMR1CG, DISABLED);
// clcok gating Timer 2
pcgcr_value |= CSL_FMKT(SYS_PCGCR1_TMR2CG, DISABLED);
// write to PCGCR1
CSL_FSET(CSL_SYSCTRL_REGS->PCGCR1, 15, 0, pcgcr_value);
// set PCGCR2
pcgcr_value = 0;
// clock gating LCD
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_LCDCG, DISABLED);
// clcok gating DMA2
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_DMA2CG, DISABLED);
// clcok gating DMA3
pcgcr_value |= CSL_FMKT(SYS_PCGCR2_DMA3CG, DISABLED);
// write to PCGCR2
CSL_FSET(CSL_SYSCTRL_REGS->PCGCR2, 15, 0, pcgcr_value);
return;
}
/*..........................................................................*/
void QK_onIdle(void) {
QF_INT_DISABLE();
SLED_ON(); /* switch the System LED on and off */
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
SLED_OFF();
QF_INT_ENABLE();
#ifdef Q_SPY
if (CSL_FEXT(l_uartObj.uartRegs->LSR, UART_LSR_THRE)) {
uint16_t b;
QF_INT_DISABLE();
b = QS_getByte();
QF_INT_ENABLE();
if (b != QS_EOD) { /* not End-Of-Data? */
CSL_FSET(l_uartObj.uartRegs->THR, 7U, 0U, b);
}
}
#elif defined NDEBUG
/* Put the CPU and peripherals to the low-power mode.
* you might need to customize the clock management for your application,
* see the datasheet for your particular TMS320C5500 device.
*/
asm(" IDLE");
#endif
}
/** ===========================================================================
* @n@b SPI_config
*
* @b Description
* @n It configures the SPI Controller registers of particular handle as per
* the values passed in the SPI config structure.
*
* @b Arguments
* @verbatim
spiHandle Handle to the spi.
spiHwConfig Pointer to spi Config structure.
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Hardware setup successful
* @li CSL_ESYS_BADHANDLE - Invalid handle
* @li CSL_ESYS_INVPARAMS - Congig Parameter is invalid.
*
* <b> Pre Condition </b>
* @n SPI_open function should call before call this function.
*
* <b> Post Condition </b>
* @n SPI_close function can call after this function call.
*
* @b Modifies
* @n 1. SPI registers will be updated as per config parameter
* @n 2. CSL_SpiObj Object will be updated to store some info
* as passed config parameter.
*
* @b Example
* @verbatim
CSL_SpiHandle hSpi;
SPI_Config spiHwConfig;
Int16 status;
status = SPI_config(hSpi, &spiHwConfig);
...
@endverbatim
* ===========================================================================
*/
CSL_Status SPI_config (CSL_SpiHandle hSpi,
SPI_Config *spiHwConfig)
{
Int16 status;
Uint16 sysClkDiv, spicmd2;
volatile Uint16 delay;
status = CSL_SOK;
if(NULL == hSpi)
{
return (CSL_ESYS_BADHANDLE);
}
if(NULL == spiHwConfig)
{
return (CSL_ESYS_INVPARAMS);
}
/* Disable the serial Data clock */
CSL_FSET(CSL_SPI_REGS->SPICCR, CSL_SPI_SPICCR_CLKEN_SHIFT,
CSL_SPI_SPICCR_CLKEN_SHIFT, CSL_SPI_SPICCR_CLKEN_DISABLED);
//CSL_FINST(CSL_SPI_REGS->SPICCR, SPI_SPICCR_CLKEN, DISABLED);
CSL_FINST(CSL_SPI_REGS->SPICCR, SPI_SPICCR_RST, RELEASE);
/* Clock division must be gater or equal to 2 */
if(spiHwConfig->spiClkDiv > 2)
{
sysClkDiv = spiHwConfig->spiClkDiv - 1;
}
else
{
sysClkDiv = 2; /* Default clock division is 2 */
}
/* Set Clock division */
CSL_FINS(CSL_SPI_REGS->SPICDR, SPI_SPICDR_CLKDV, sysClkDiv);
/* Set Wordlength bit 0,1,2......31 */
spicmd2 = spiHwConfig->wLen << CSL_SPI_SPICMD2_CLEN_SHIFT;
//CSL_FINS(CSL_SPI_REGS->SPICMD2, SPI_SPICMD2_CLEN, spiHwConfig->wLen);
/* Set the frame length bits 0,1,2 ......4095 */
CSL_FINS(CSL_SPI_REGS->SPICMD1, SPI_SPICMD1_FLEN, spiHwConfig->frLen-1);
/* Enable or Disable word count IRQ */
CSL_FINS(CSL_SPI_REGS->SPICMD1, SPI_SPICMD1_CIRQ, spiHwConfig->wcEnable);
for(delay = 0; delay < 16; delay++);
/* Enable the serial Data clock */
CSL_SPI_REGS->SPICCR =
(Uint16)(CSL_SPI_SPICCR_CLKEN_ENABLED << CSL_SPI_SPICCR_CLKEN_SHIFT);
/* Enable or Disable frame count IRQ */
CSL_FINS(CSL_SPI_REGS->SPICMD1, SPI_SPICMD1_FIRQ, spiHwConfig->fcEnable);
/* Select active CS for transfer */
spicmd2 |= spiHwConfig->csNum << CSL_SPI_SPICMD2_CSNUM_SHIFT;
CSL_FSET(CSL_SPI_REGS->SPICMD2, 15, 0, spicmd2);
//CSL_FINS(CSL_SPI_REGS->SPICMD2, SPI_SPICMD2_CSNUM, spiHwConfig->csNum);
/* Set Data delay, cs pol, clk pol and clpck pkase bit as per chip select */
switch(spiHwConfig->csNum)
{
case CSL_SPI_SPICMD2_CSNUM_CS0:
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_DD0,
spiHwConfig->dataDelay);
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_CSP0,
spiHwConfig->csPol);
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_CKP0,
spiHwConfig->clkPol);
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_CKPH0,
spiHwConfig->clkPh);
break;
case CSL_SPI_SPICMD2_CSNUM_CS1:
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_DD1,
spiHwConfig->dataDelay);
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_CSP1,
spiHwConfig->csPol);
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_CKP1,
spiHwConfig->clkPol);
CSL_FINS(CSL_SPI_REGS->SPIDCR1, SPI_SPIDCR1_CKPH1,
spiHwConfig->clkPh);
break;
case CSL_SPI_SPICMD2_CSNUM_CS2:
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_DD2,
spiHwConfig->dataDelay);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CSP2,
spiHwConfig->csPol);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CKP2,
spiHwConfig->clkPol);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CKPH2,
spiHwConfig->clkPh);
break;
case CSL_SPI_SPICMD2_CSNUM_CS3:
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_DD3,
spiHwConfig->dataDelay);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CSP3,
spiHwConfig->csPol);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CKP3,
spiHwConfig->clkPol);
CSL_FINS(CSL_SPI_REGS->SPIDCR2, SPI_SPIDCR2_CKPH3,
spiHwConfig->clkPh);
break;
default:
status = CSL_ESYS_INVPARAMS;
}
if(CSL_ESYS_INVPARAMS != status)
{
hSpi->configured = TRUE;
}
else
{
hSpi->configured = FALSE;
}
return (status);
}
