void
ste_txeoc(struct ste_softc *sc)
{
u_int8_t txstat;
struct ifnet *ifp;
ifp = &sc->arpcom.ac_if;
while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
STE_TXSTATUS_TXDONE) {
if (txstat & STE_TXSTATUS_UNDERRUN ||
txstat & STE_TXSTATUS_EXCESSCOLLS ||
txstat & STE_TXSTATUS_RECLAIMERR) {
ifp->if_oerrors++;
printf("%s: transmission error: %x\n",
sc->sc_dev.dv_xname, txstat);
ste_reset(sc);
ste_init(sc);
if (txstat & STE_TXSTATUS_UNDERRUN &&
sc->ste_tx_thresh < ETHER_MAX_DIX_LEN) {
sc->ste_tx_thresh += STE_MIN_FRAMELEN;
printf("%s: tx underrun, increasing tx"
" start threshold to %d bytes\n",
sc->sc_dev.dv_xname, sc->ste_tx_thresh);
}
CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
(ETHER_MAX_DIX_LEN >> 4));
}
ste_init(sc);
CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
}
int
an_seek_bap(struct an_softc *sc, int id, int off)
{
int i, status;
CSR_WRITE_2(sc, AN_SEL0, id);
CSR_WRITE_2(sc, AN_OFF0, off);
for (i = 0; ; i++) {
status = CSR_READ_2(sc, AN_OFF0);
if ((status & AN_OFF_BUSY) == 0)
break;
if (i == AN_TIMEOUT) {
printf("%s: timeout in an_seek_bap to 0x%x/0x%x\n",
sc->sc_dev.dv_xname, id, off);
sc->sc_bap_off = AN_OFF_ERR; /* invalidate */
return ETIMEDOUT;
}
DELAY(10);
}
if (status & AN_OFF_ERR) {
printf("%s: failed in an_seek_bap to 0x%x/0x%x\n",
sc->sc_dev.dv_xname, id, off);
sc->sc_bap_off = AN_OFF_ERR; /* invalidate */
return EIO;
}
sc->sc_bap_id = id;
sc->sc_bap_off = off;
return 0;
}
void
bwi_phy_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
{
struct bwi_softc *sc = mac->mac_sc;
CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
CSR_WRITE_2(sc, BWI_PHY_DATA, data);
}
int
rtk_intr(void *arg)
{
struct rtk_softc *sc;
struct ifnet *ifp;
uint16_t status;
int handled;
sc = arg;
ifp = &sc->ethercom.ec_if;
if (!device_has_power(sc->sc_dev))
return 0;
/* Disable interrupts. */
CSR_WRITE_2(sc, RTK_IMR, 0x0000);
handled = 0;
for (;;) {
status = CSR_READ_2(sc, RTK_ISR);
if (status == 0xffff)
break; /* Card is gone... */
if (status)
CSR_WRITE_2(sc, RTK_ISR, status);
if ((status & RTK_INTRS) == 0)
break;
handled = 1;
if (status & RTK_ISR_RX_OK)
rtk_rxeof(sc);
if (status & RTK_ISR_RX_ERR)
rtk_rxeof(sc);
if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR))
rtk_txeof(sc);
if (status & RTK_ISR_SYSTEM_ERR) {
rtk_reset(sc);
rtk_init(ifp);
}
}
/* Re-enable interrupts. */
CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
rtk_start(ifp);
rnd_add_uint32(&sc->rnd_source, status);
return handled;
}
void
vte_miibus_statchg(struct device *dev)
{
struct vte_softc *sc = (struct vte_softc *)dev;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
struct mii_data *mii;
uint16_t val;
if ((ifp->if_flags & IFF_RUNNING) == 0)
return;
mii = &sc->sc_miibus;
sc->vte_flags &= ~VTE_FLAG_LINK;
if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
(IFM_ACTIVE | IFM_AVALID)) {
switch (IFM_SUBTYPE(mii->mii_media_active)) {
case IFM_10_T:
case IFM_100_TX:
sc->vte_flags |= VTE_FLAG_LINK;
break;
default:
break;
}
}
/* Stop RX/TX MACs. */
vte_stop_mac(sc);
/* Program MACs with resolved duplex and flow control. */
if ((sc->vte_flags & VTE_FLAG_LINK) != 0) {
/*
* Timer waiting time : (63 + TIMER * 64) MII clock.
* MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps).
*/
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
val = 18 << VTE_IM_TIMER_SHIFT;
else
val = 1 << VTE_IM_TIMER_SHIFT;
sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT;
val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT;
/* 48.6us for 100Mbps, 50.8us for 10Mbps */
CSR_WRITE_2(sc, VTE_MRICR, val);
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX)
val = 18 << VTE_IM_TIMER_SHIFT;
else
val = 1 << VTE_IM_TIMER_SHIFT;
sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT;
val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT;
/* 48.6us for 100Mbps, 50.8us for 10Mbps */
CSR_WRITE_2(sc, VTE_MTICR, val);
vte_mac_config(sc);
vte_start_mac(sc);
}
}
void
EtherStop(void)
{
/*
* Issue software reset
*/
CSR_WRITE_2(ELINK_COMMAND, RX_DISABLE);
CSR_WRITE_2(ELINK_COMMAND, TX_DISABLE);
CSR_WRITE_2(ELINK_COMMAND, STOP_TRANSCEIVER);
CSR_WRITE_2(ELINK_COMMAND, INTR_LATCH);
}
void
ste_iff(struct ste_softc *sc)
{
struct ifnet *ifp = &sc->arpcom.ac_if;
struct arpcom *ac = &sc->arpcom;
struct ether_multi *enm;
struct ether_multistep step;
u_int32_t rxmode, hashes[2];
int h = 0;
rxmode = CSR_READ_1(sc, STE_RX_MODE);
rxmode &= ~(STE_RXMODE_ALLMULTI | STE_RXMODE_BROADCAST |
STE_RXMODE_MULTIHASH | STE_RXMODE_PROMISC |
STE_RXMODE_UNICAST);
bzero(hashes, sizeof(hashes));
ifp->if_flags &= ~IFF_ALLMULTI;
/*
* Always accept broadcast frames.
* Always accept frames destined to our station address.
*/
rxmode |= STE_RXMODE_BROADCAST | STE_RXMODE_UNICAST;
if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI;
rxmode |= STE_RXMODE_ALLMULTI;
if (ifp->if_flags & IFF_PROMISC)
rxmode |= STE_RXMODE_PROMISC;
} else {
rxmode |= STE_RXMODE_MULTIHASH;
/* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm);
while (enm != NULL) {
h = ether_crc32_be(enm->enm_addrlo,
ETHER_ADDR_LEN) & 0x3F;
if (h < 32)
hashes[0] |= (1 << h);
else
hashes[1] |= (1 << (h - 32));
ETHER_NEXT_MULTI(step, enm);
}
}
CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
CSR_WRITE_1(sc, STE_RX_MODE, rxmode);
}
/*
* Wait for firmware come up after power enabled.
*/
void
an_wait(struct an_softc *sc)
{
int i;
CSR_WRITE_2(sc, AN_COMMAND, AN_CMD_NOOP2);
for (i = 0; i < 3*hz; i++) {
if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD)
break;
(void)tsleep(sc, PWAIT, "anatch", 1);
}
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD);
}
int
an_intr(void *arg)
{
struct an_softc *sc = arg;
struct ifnet *ifp = &sc->sc_ic.ic_if;
int i;
u_int16_t status;
if (!sc->sc_enabled || sc->sc_invalid ||
(sc->sc_dev.dv_flags & DVF_ACTIVE) == 0 ||
(ifp->if_flags & IFF_RUNNING) == 0)
return 0;
if ((ifp->if_flags & IFF_UP) == 0) {
CSR_WRITE_2(sc, AN_INT_EN, 0);
CSR_WRITE_2(sc, AN_EVENT_ACK, ~0);
return 1;
}
/* maximum 10 loops per interrupt */
for (i = 0; i < 10; i++) {
if (!sc->sc_enabled || sc->sc_invalid)
return 1;
if (CSR_READ_2(sc, AN_SW0) != AN_MAGIC) {
DPRINTF(("an_intr: magic number changed: %x\n",
CSR_READ_2(sc, AN_SW0)));
sc->sc_invalid = 1;
return 1;
}
status = CSR_READ_2(sc, AN_EVENT_STAT);
CSR_WRITE_2(sc, AN_EVENT_ACK, status & ~(AN_INTRS));
if ((status & AN_INTRS) == 0)
break;
if (status & AN_EV_RX)
an_rxeof(sc);
if (status & (AN_EV_TX | AN_EV_TX_EXC))
an_txeof(sc, status);
if (status & AN_EV_LINKSTAT)
an_linkstat_intr(sc);
if (ifq_is_oactive(&ifp->if_snd) == 0 &&
sc->sc_ic.ic_state == IEEE80211_S_RUN &&
!IFQ_IS_EMPTY(&ifp->if_snd))
an_start(ifp);
}
return 1;
}
int
__haiku_disable_interrupts(device_t dev)
{
struct xl_softc *sc = device_get_softc(dev);
u_int16_t status = CSR_READ_2(sc, XL_STATUS);
if (status == 0xffff || (status & XL_INTRS) == 0)
return 0;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK | (status & XL_INTRS));
atomic_set((int32 *)&sc->xl_intr_status, status);
return 1;
}
static int
wi_pcmcia_set_hcr(struct wi_softc *sc, int mode)
{
u_int16_t hcr;
CSR_WRITE_2(sc, WI_COR, WI_COR_RESET);
tsleep(sc, PWAIT, "wiinit", 1);
hcr = CSR_READ_2(sc, WI_HCR);
hcr = (hcr & WI_HCR_4WIRE) | (mode & ~WI_HCR_4WIRE);
CSR_WRITE_2(sc, WI_HCR, hcr);
tsleep(sc, PWAIT, "wiinit", 1);
CSR_WRITE_2(sc, WI_COR, WI_COR_IOMODE);
tsleep(sc, PWAIT, "wiinit", 1);
return 0;
}
void
an_stop(struct ifnet *ifp, int disable)
{
struct an_softc *sc = ifp->if_softc;
int i, s;
if (!sc->sc_enabled)
return;
DPRINTF(("an_stop: disable %d\n", disable));
s = splnet();
ieee80211_new_state(&sc->sc_ic, IEEE80211_S_INIT, -1);
if (!sc->sc_invalid) {
an_cmd(sc, AN_CMD_FORCE_SYNCLOSS, 0);
CSR_WRITE_2(sc, AN_INT_EN, 0);
an_cmd(sc, AN_CMD_DISABLE, 0);
for (i = 0; i < AN_TX_RING_CNT; i++)
an_cmd(sc, AN_CMD_DEALLOC_MEM, sc->sc_txd[i].d_fid);
}
sc->sc_tx_timer = 0;
ifp->if_timer = 0;
ifp->if_flags &= ~IFF_RUNNING;
ifq_clr_oactive(&ifp->if_snd);
if (disable) {
if (sc->sc_disable)
(*sc->sc_disable)(sc);
sc->sc_enabled = 0;
}
splx(s);
}
void *
kse_init(unsigned tag, void *data)
{
struct local *l;
struct desc *txd, *rxd;
unsigned i, val, fdx;
uint8_t *en;
l = ALLOC(struct local, sizeof(struct desc)); /* desc alignment */
memset(l, 0, sizeof(struct local));
l->csr = DEVTOV(pcicfgread(tag, 0x10));
en = data;
i = CSR_READ_2(l, MARL);
en[0] = i;
en[1] = i >> 8;
i = CSR_READ_2(l, MARM);
en[2] = i;
en[3] = i >> 8;
i = CSR_READ_2(l, MARH);
en[4] = i;
en[5] = i >> 8;
printf("MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
en[0], en[1], en[2], en[3], en[4], en[5]);
CSR_WRITE_2(l, CIDR, 1);
mii_dealan(l, 5);
val = pcicfgread(tag, PCI_ID_REG);
if (PCI_PRODUCT(val) == 0x8841) {
val = CSR_READ_4(l, P1SR);
fdx = !!(val & (1U << 9));
printf("%s", (val & (1U << 8)) ? "100Mbps" : "10Mbps");
if (fdx)
printf("-FDX");
printf("\n");
}
txd = &l->txd;
rxd = &l->rxd[0];
rxd[0].xd0 = htole32(R0_OWN);
rxd[0].xd1 = htole32(FRAMESIZE);
rxd[0].xd2 = htole32(VTOPHYS(l->rxstore[0]));
rxd[0].xd3 = htole32(VTOPHYS(&rxd[1]));
rxd[1].xd0 = htole32(R0_OWN);
rxd[1].xd1 = htole32(R1_RER | FRAMESIZE);
rxd[1].xd2 = htole32(VTOPHYS(l->rxstore[1]));
rxd[1].xd3 = htole32(VTOPHYS(&rxd[0]));
l->rx = 0;
CSR_WRITE_4(l, TDLB, VTOPHYS(txd));
CSR_WRITE_4(l, RDLB, VTOPHYS(rxd));
CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */
CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */
CSR_WRITE_4(l, MDRSC, 01); /* start receiving */
return l;
}
int
EtherSend(char *pkt, int len)
{
volatile struct ex_dpd *dpd;
int i;
dpd = SNDBUF_VIRT;
dpd->dpd_nextptr = 0;
dpd->dpd_fsh = len;
#ifdef _STANDALONE
dpd->dpd_frags[0].fr_addr = vtophys(pkt);
#else
memcpy(SNDBUF_VIRT + 100, pkt, len);
dpd->dpd_frags[0].fr_addr = SNDBUF_PHYS + 100;
#endif
dpd->dpd_frags[0].fr_len = len | EX_FR_LAST;
CSR_WRITE_4(ELINK_DNLISTPTR, SNDBUF_PHYS);
CSR_WRITE_2(ELINK_COMMAND, ELINK_DNUNSTALL);
i = 10000;
while (!(dpd->dpd_fsh & 0x00010000)) {
if (--i < 0) {
printf("3c90xb: send timeout\n");
return -1;
}
delay(1);
}
return len;
}
int
an_alloc_nicmem(struct an_softc *sc, int len, int *idp)
{
int i;
if (an_cmd(sc, AN_CMD_ALLOC_MEM, len)) {
printf("%s: failed to allocate %d bytes on NIC\n",
sc->sc_dev.dv_xname, len);
return(ENOMEM);
}
for (i = 0; i < AN_TIMEOUT; i++) {
if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_ALLOC)
break;
if (i == AN_TIMEOUT) {
printf("%s: timeout in alloc\n", sc->sc_dev.dv_xname);
return ETIMEDOUT;
}
DELAY(10);
}
*idp = CSR_READ_2(sc, AN_ALLOC_FID);
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_ALLOC);
return 0;
}
void
ex_reset(void)
{
CSR_WRITE_2(ELINK_COMMAND, GLOBAL_RESET);
delay(100000);
ex_waitcmd();
}
void
ANTARES_REENABLE_INTERRUPTS(device_t dev)
{
struct rl_softc *sc = device_get_softc(dev);
RL_LOCK(sc);
CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
RL_UNLOCK(sc);
}
int
ANTARES_CHECK_DISABLE_INTERRUPTS(device_t dev)
{
struct wi_softc* sc = (struct wi_softc*)device_get_softc(dev);
struct ifnet* ifp = sc->sc_ifp;
if (sc->wi_gone || !sc->sc_enabled || (ifp->if_flags & IFF_UP) == 0) {
CSR_WRITE_2(sc, WI_INT_EN, 0);
CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
return 0;
}
CSR_WRITE_2(sc, WI_INT_EN, 0);
// Disable interrupts.
return 1;
}
uint16_t
bwi_phy_read(struct bwi_mac *mac, uint16_t ctrl)
{
struct bwi_softc *sc = mac->mac_sc;
CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
return CSR_READ_2(sc, BWI_PHY_DATA);
}
int
ste_intr(void *xsc)
{
struct ste_softc *sc;
struct ifnet *ifp;
u_int16_t status;
int claimed = 0;
sc = xsc;
ifp = &sc->arpcom.ac_if;
/* See if this is really our interrupt. */
if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
return claimed;
for (;;) {
status = CSR_READ_2(sc, STE_ISR_ACK);
if (!(status & STE_INTRS))
break;
claimed = 1;
if (status & STE_ISR_RX_DMADONE) {
ste_rxeoc(sc);
ste_rxeof(sc);
}
if (status & STE_ISR_TX_DMADONE)
ste_txeof(sc);
if (status & STE_ISR_TX_DONE)
ste_txeoc(sc);
if (status & STE_ISR_STATS_OFLOW) {
timeout_del(&sc->sc_stats_tmo);
ste_stats_update(sc);
}
if (status & STE_ISR_LINKEVENT)
mii_pollstat(&sc->sc_mii);
if (status & STE_ISR_HOSTERR) {
ste_reset(sc);
ste_init(sc);
}
}
/* Re-enable interrupts */
CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
ste_start(ifp);
return claimed;
}
int
ANTARES_CHECK_DISABLE_INTERRUPTS(device_t dev)
{
struct rl_softc *sc = device_get_softc(dev);
uint16_t status;
status = CSR_READ_2(sc, RL_ISR);
if (status == 0xffff)
return 0;
if (status != 0 && (status & RL_INTRS) == 0) {
CSR_WRITE_2(sc, RL_ISR, status);
return 0;
}
if ((status & RL_INTRS) == 0)
return 0;
CSR_WRITE_2(sc, RL_IMR, 0);
return 1;
}
void
vte_miibus_writereg(struct device *dev, int phy, int reg, int val)
{
struct vte_softc *sc = (struct vte_softc *)dev;
int i;
CSR_WRITE_2(sc, VTE_MMWD, val);
CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
(phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT));
for (i = VTE_PHY_TIMEOUT; i > 0; i--) {
DELAY(5);
if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0)
break;
}
if (i == 0)
printf("%s: phy write timeout: phy %d, reg %d\n",
sc->sc_dev.dv_xname, phy, reg);
}
static uint16_t
pcn_bcr_read16(pcn_t *pcnp, uint32_t reg)
{
uint16_t val;
mutex_enter(&pcnp->pcn_reglock);
CSR_WRITE_2(pcnp, PCN_IO16_RAP, reg);
val = CSR_READ_2(pcnp, PCN_IO16_BDP);
mutex_exit(&pcnp->pcn_reglock);
return (val);
}
void
ex_set_media(void)
{
int config0, config1;
CSR_WRITE_2(ELINK_W3_MAC_CONTROL, 0);
if (ether_medium == ETHERMEDIUM_MII)
goto setcfg;
GO_WINDOW(4);
CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, 0);
CSR_WRITE_2(ELINK_COMMAND, STOP_TRANSCEIVER);
delay(800);
switch (ether_medium) {
case ETHERMEDIUM_UTP:
CSR_WRITE_2(ELINK_W4_MEDIA_TYPE,
JABBER_GUARD_ENABLE | LINKBEAT_ENABLE);
break;
case ETHERMEDIUM_BNC:
CSR_WRITE_2(ELINK_COMMAND, START_TRANSCEIVER);
delay(800);
break;
case ETHERMEDIUM_AUI:
CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, SQE_ENABLE);
delay(800);
break;
case ETHERMEDIUM_100TX:
CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, LINKBEAT_ENABLE);
break;
}
setcfg:
GO_WINDOW(3);
config0 = CSR_READ_2(ELINK_W3_INTERNAL_CONFIG);
config1 = CSR_READ_2(ELINK_W3_INTERNAL_CONFIG + 2);
config1 = config1 & ~CONFIG_MEDIAMASK;
config1 |= (mediatab[ether_medium].address_cfg
<< CONFIG_MEDIAMASK_SHIFT);
CSR_WRITE_2(ELINK_W3_INTERNAL_CONFIG, config0);
CSR_WRITE_2(ELINK_W3_INTERNAL_CONFIG + 2, config1);
}
/* Must be called at proper protection level! */
int
an_cmd(struct an_softc *sc, int cmd, int val)
{
int i, stat;
/* make sure previous command completed */
if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY) {
if (sc->sc_ic.ic_if.if_flags & IFF_DEBUG)
printf("%s: command 0x%x busy\n", sc->sc_dev.dv_xname,
CSR_READ_2(sc, AN_COMMAND));
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY);
}
CSR_WRITE_2(sc, AN_PARAM0, val);
CSR_WRITE_2(sc, AN_PARAM1, 0);
CSR_WRITE_2(sc, AN_PARAM2, 0);
CSR_WRITE_2(sc, AN_COMMAND, cmd);
if (cmd == AN_CMD_FW_RESTART) {
/* XXX: should sleep here */
DELAY(100*1000);
}
for (i = 0; i < AN_TIMEOUT; i++) {
if (CSR_READ_2(sc, AN_EVENT_STAT) & AN_EV_CMD)
break;
DELAY(10);
}
stat = CSR_READ_2(sc, AN_STATUS);
/* clear stuck command busy if necessary */
if (CSR_READ_2(sc, AN_COMMAND) & AN_CMD_BUSY)
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY);
/* Ack the command */
CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD);
if (i == AN_TIMEOUT) {
if (sc->sc_ic.ic_if.if_flags & IFF_DEBUG)
printf("%s: command 0x%x param 0x%x timeout\n",
sc->sc_dev.dv_xname, cmd, val);
return ETIMEDOUT;
}
if (stat & AN_STAT_CMD_RESULT) {
if (sc->sc_ic.ic_if.if_flags & IFF_DEBUG)
printf("%s: command 0x%x param 0x%x status 0x%x "
"resp 0x%x 0x%x 0x%x\n",
sc->sc_dev.dv_xname, cmd, val, stat,
CSR_READ_2(sc, AN_RESP0), CSR_READ_2(sc, AN_RESP1),
CSR_READ_2(sc, AN_RESP2));
return EIO;
}
return 0;
}
int
HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev)
{
struct an_softc* sc = (struct an_softc*)device_get_softc(dev);
if (sc->an_gone)
return 0;
CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
// Disable interrupts.
return 1;
}
static int
wi_pccard_attach(device_t dev)
{
struct wi_softc *sc;
int error;
sc = device_get_softc(dev);
sc->wi_gone = 0;
sc->wi_bus_type = WI_BUS_PCCARD;
error = wi_alloc(dev, 0);
if (error == 0) {
/* Make sure interrupts are disabled. */
CSR_WRITE_2(sc, WI_INT_EN, 0);
CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
error = wi_attach(dev);
if (error != 0)
wi_free(dev);
}
return error;
}
static void
rtk_phy_writereg(device_t self, int phy, int reg, int data)
{
struct rtk_softc *sc = device_private(self);
struct rtk_mii_frame frame;
int rtk8139_reg;
if ((sc->sc_quirk & RTKQ_8129) == 0) {
if (phy != 7)
return;
switch (reg) {
case MII_BMCR:
rtk8139_reg = RTK_BMCR;
break;
case MII_BMSR:
rtk8139_reg = RTK_BMSR;
break;
case MII_ANAR:
rtk8139_reg = RTK_ANAR;
break;
case MII_ANER:
rtk8139_reg = RTK_ANER;
break;
case MII_ANLPAR:
rtk8139_reg = RTK_LPAR;
break;
default:
#if 0
printf("%s: bad phy register\n", device_xname(self));
#endif
return;
}
CSR_WRITE_2(sc, rtk8139_reg, data);
return;
}
memset(&frame, 0, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
frame.mii_data = data;
rtk_mii_writereg(sc, &frame);
}
/*
* Bring device up.
*/
void
ex_init(void)
{
int i;
ex_waitcmd();
EtherStop();
/*
* Set the station address and clear the station mask. The latter
* is needed for 90x cards, 0 is the default for 90xB cards.
*/
GO_WINDOW(2);
for (i = 0; i < 6; i++) {
CSR_WRITE_1(ELINK_W2_ADDR_0 + i,
myethaddr[i]);
CSR_WRITE_1(ELINK_W2_RECVMASK_0 + i, 0);
}
GO_WINDOW(3);
CSR_WRITE_2(ELINK_COMMAND, RX_RESET);
ex_waitcmd();
CSR_WRITE_2(ELINK_COMMAND, TX_RESET);
ex_waitcmd();
CSR_WRITE_2(ELINK_COMMAND, SET_INTR_MASK | 0); /* disable */
CSR_WRITE_2(ELINK_COMMAND, ACK_INTR | 0xff);
ex_set_media();
CSR_WRITE_2(ELINK_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST);
CSR_WRITE_4(ELINK_DNLISTPTR, 0);
CSR_WRITE_2(ELINK_COMMAND, TX_ENABLE);
CSR_WRITE_4(ELINK_UPLISTPTR, RECVBUF_PHYS);
CSR_WRITE_2(ELINK_COMMAND, RX_ENABLE);
CSR_WRITE_2(ELINK_COMMAND, ELINK_UPUNSTALL);
GO_WINDOW(1);
}
void
ste_setmulti(struct ste_softc *sc)
{
struct ifnet *ifp;
struct arpcom *ac = &sc->arpcom;
struct ether_multi *enm;
struct ether_multistep step;
int h = 0;
u_int32_t hashes[2] = { 0, 0 };
ifp = &sc->arpcom.ac_if;
allmulti:
if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
return;
}
/* first, zot all the existing hash bits */
CSR_WRITE_2(sc, STE_MAR0, 0);
CSR_WRITE_2(sc, STE_MAR1, 0);
CSR_WRITE_2(sc, STE_MAR2, 0);
CSR_WRITE_2(sc, STE_MAR3, 0);
/* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm);
while (enm != NULL) {
if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
goto allmulti;
}
h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) & 0x3F;
if (h < 32)
hashes[0] |= (1 << h);
else
hashes[1] |= (1 << (h - 32));
ETHER_NEXT_MULTI(step, enm);
}
CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
return;
}
