/**
* @INTERNAL
* Bringup and enable SRIO interface. After this call packet
* I/O should be fully functional. This is called with IPD
* enabled but PKO disabled.
*
* @param interface Interface to bring up
*
* @return Zero on success, negative on failure
*/
int __cvmx_helper_srio_enable(int interface)
{
int num_ports = cvmx_helper_ports_on_interface(interface);
int index;
cvmx_sriomaintx_core_enables_t sriomaintx_core_enables;
cvmx_sriox_imsg_ctrl_t sriox_imsg_ctrl;
cvmx_sriox_status_reg_t srio_status_reg;
cvmx_dpi_ctl_t dpi_ctl;
int srio_port = interface - 4;
/* All SRIO ports have a cvmx_srio_rx_message_header_t header
on them that must be skipped by IPD */
for (index=0; index<num_ports; index++)
{
cvmx_pip_prt_cfgx_t port_config;
cvmx_sriox_omsg_portx_t sriox_omsg_portx;
cvmx_sriox_omsg_sp_mrx_t sriox_omsg_sp_mrx;
cvmx_sriox_omsg_fmp_mrx_t sriox_omsg_fmp_mrx;
cvmx_sriox_omsg_nmp_mrx_t sriox_omsg_nmp_mrx;
int ipd_port = cvmx_helper_get_ipd_port(interface, index);
port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port));
/* Only change the skip if the user hasn't already set it */
if (!port_config.s.skip)
{
port_config.s.skip = sizeof(cvmx_srio_rx_message_header_t);
cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64);
}
/* Enable TX with PKO */
sriox_omsg_portx.u64 = cvmx_read_csr(CVMX_SRIOX_OMSG_PORTX(index, srio_port));
sriox_omsg_portx.s.port = (srio_port) * 2 + index;
sriox_omsg_portx.s.enable = 1;
cvmx_write_csr(CVMX_SRIOX_OMSG_PORTX(index, srio_port), sriox_omsg_portx.u64);
/* Allow OMSG controller to send regardless of the state of any other
controller. Allow messages to different IDs and MBOXes to go in
parallel */
sriox_omsg_sp_mrx.u64 = 0;
sriox_omsg_sp_mrx.s.xmbox_sp = 1;
sriox_omsg_sp_mrx.s.ctlr_sp = 1;
sriox_omsg_sp_mrx.s.ctlr_fmp = 1;
sriox_omsg_sp_mrx.s.ctlr_nmp = 1;
sriox_omsg_sp_mrx.s.id_sp = 1;
sriox_omsg_sp_mrx.s.id_fmp = 1;
sriox_omsg_sp_mrx.s.id_nmp = 1;
sriox_omsg_sp_mrx.s.mbox_sp = 1;
sriox_omsg_sp_mrx.s.mbox_fmp = 1;
sriox_omsg_sp_mrx.s.mbox_nmp = 1;
sriox_omsg_sp_mrx.s.all_psd = 1;
cvmx_write_csr(CVMX_SRIOX_OMSG_SP_MRX(index, srio_port), sriox_omsg_sp_mrx.u64);
/* Allow OMSG controller to send regardless of the state of any other
controller. Allow messages to different IDs and MBOXes to go in
parallel */
sriox_omsg_fmp_mrx.u64 = 0;
sriox_omsg_fmp_mrx.s.ctlr_sp = 1;
sriox_omsg_fmp_mrx.s.ctlr_fmp = 1;
sriox_omsg_fmp_mrx.s.ctlr_nmp = 1;
sriox_omsg_fmp_mrx.s.id_sp = 1;
sriox_omsg_fmp_mrx.s.id_fmp = 1;
sriox_omsg_fmp_mrx.s.id_nmp = 1;
sriox_omsg_fmp_mrx.s.mbox_sp = 1;
sriox_omsg_fmp_mrx.s.mbox_fmp = 1;
sriox_omsg_fmp_mrx.s.mbox_nmp = 1;
sriox_omsg_fmp_mrx.s.all_psd = 1;
cvmx_write_csr(CVMX_SRIOX_OMSG_FMP_MRX(index, srio_port), sriox_omsg_fmp_mrx.u64);
/* Once the first part of a message is accepted, always acept the rest
of the message */
sriox_omsg_nmp_mrx.u64 = 0;
sriox_omsg_nmp_mrx.s.all_sp = 1;
sriox_omsg_nmp_mrx.s.all_fmp = 1;
sriox_omsg_nmp_mrx.s.all_nmp = 1;
cvmx_write_csr(CVMX_SRIOX_OMSG_NMP_MRX(index, srio_port), sriox_omsg_nmp_mrx.u64);
}
/* Choose the receive controller based on the mailbox */
sriox_imsg_ctrl.u64 = cvmx_read_csr(CVMX_SRIOX_IMSG_CTRL(srio_port));
sriox_imsg_ctrl.s.prt_sel = 0;
sriox_imsg_ctrl.s.mbox = 0xa;
cvmx_write_csr(CVMX_SRIOX_IMSG_CTRL(srio_port), sriox_imsg_ctrl.u64);
/* DPI must be enabled for us to RX messages */
dpi_ctl.u64 = cvmx_read_csr(CVMX_DPI_CTL);
dpi_ctl.s.clk = 1;
dpi_ctl.s.en = 1;
cvmx_write_csr(CVMX_DPI_CTL, dpi_ctl.u64);
/* Make sure register access is allowed */
srio_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(srio_port));
if (!srio_status_reg.s.access)
return 0;
/* Enable RX */
if (!cvmx_srio_config_read32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_CORE_ENABLES(srio_port), &sriomaintx_core_enables.u32))
{
sriomaintx_core_enables.s.imsg0 = 1;
sriomaintx_core_enables.s.imsg1 = 1;
cvmx_srio_config_write32(srio_port, 0, -1, 0, 0,
CVMX_SRIOMAINTX_CORE_ENABLES(srio_port), sriomaintx_core_enables.u32);
}
return 0;
}
static int cn6xxx_probe(struct rio_dev *dev, const struct rio_device_id *id)
{
u32 data;
cvmx_sriomaintx_m2s_bar2_start_t sriomaintx_m2s_bar2_start;
cvmx_sriomaintx_lcs_ba0_t sriomaintx_lcs_ba0;
cvmx_sriomaintx_lcs_ba1_t sriomaintx_lcs_ba1;
cvmx_sriomaintx_m2s_bar1_start0_t sriomaintx_m2s_bar1_start0;
cvmx_sriomaintx_m2s_bar1_start1_t sriomaintx_m2s_bar1_start1;
cvmx_sriomaintx_m2s_bar0_start0_t sriomaintx_m2s_bar0_start0;
cvmx_sriomaintx_m2s_bar0_start1_t sriomaintx_m2s_bar0_start1;
cvmx_sriomaintx_core_enables_t sriomaintx_core_enables;
cvmx_sriomaintx_port_gen_ctl_t sriomaintx_port_gen_ctl;
cvmx_sriomaintx_port_0_ctl_t sriomaintx_port_0_ctl;
const char *state;
int index;
if (rio_read_config_32(dev, CVMX_SRIOMAINTX_IR_PI_PHY_STAT(0), &data))
return -1;
switch (data & 0x3ff) {
case 0x0:
state = "Silent";
break;
case 0x2:
state = "Seek";
break;
case 0x4:
state = "Discovery";
break;
case 0x8:
state = "1x Mode Lane 0";
break;
case 0x10:
state = "1x Mode Lane 1";
break;
case 0x20:
state = "1x Mode Lane 2";
break;
case 0x40:
state = "1x Recovery";
break;
case 0x80:
state = "2x Mode";
break;
case 0x100:
state = "2x Recovery";
break;
case 0x200:
state = "4x Mode";
break;
default:
state = "Reserved";
break;
}
dev_info(&dev->dev, "Link state: %s\n", state);
/* Setup BAR2 */
sriomaintx_m2s_bar2_start.u32 = 0;
sriomaintx_m2s_bar2_start.s.addr64 = BAR2_ADDRESS >> 48;
sriomaintx_m2s_bar2_start.s.addr48 = BAR2_ADDRESS >> 41;
sriomaintx_m2s_bar2_start.s.esx = 0;
sriomaintx_m2s_bar2_start.s.cax = 0;
sriomaintx_m2s_bar2_start.s.addr66 = 0; // BAR2_ADDRESS >> 64;
sriomaintx_m2s_bar2_start.s.enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR2_START(0),
sriomaintx_m2s_bar2_start.u32))
return -1;
dev_info(&dev->dev, "BAR2 0x%016llx - 0x%016llx\n", BAR2_ADDRESS,
BAR2_ADDRESS + BAR2_SIZE - 1);
/* Setup Maintinance */
sriomaintx_lcs_ba0.u32 = 0;
sriomaintx_lcs_ba0.s.lcsba = MAINT_ADDRESS >> 35;
sriomaintx_lcs_ba1.u32 = 0;
sriomaintx_lcs_ba1.s.lcsba = (MAINT_ADDRESS >> 24) & 0x7ff;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_LCS_BA0(0),
sriomaintx_lcs_ba0.u32))
return -1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_LCS_BA1(0),
sriomaintx_lcs_ba1.u32))
return -1;
dev_info(&dev->dev, "Maintenance 0x%016llx - 0x%016llx\n",
MAINT_ADDRESS, MAINT_ADDRESS + MAINT_SIZE - 1);
/* Setup BAR1 */
sriomaintx_m2s_bar1_start0.u32 = 0;
sriomaintx_m2s_bar1_start0.s.addr64 = BAR1_ADDRESS >> 48;
sriomaintx_m2s_bar1_start0.s.addr48 = BAR1_ADDRESS >> 32;
sriomaintx_m2s_bar1_start1.u32 = 0;
sriomaintx_m2s_bar1_start1.s.addr32 = (BAR1_ADDRESS >> 20) & 0xfff;
sriomaintx_m2s_bar1_start1.s.barsize = BAR1_SHIFT;
sriomaintx_m2s_bar1_start1.s.addr66 = 0; // BAR1_ADDRESS >> 64;
sriomaintx_m2s_bar1_start1.s.enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR1_START0(0),
sriomaintx_m2s_bar1_start0.u32))
return -1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR1_START1(0),
sriomaintx_m2s_bar1_start1.u32))
return -1;
dev_info(&dev->dev, "BAR1 0x%016llx - 0x%016llx\n", BAR1_ADDRESS,
BAR1_ADDRESS + BAR1_SIZE - 1);
/* Setup BAR0 */
sriomaintx_m2s_bar0_start0.u32 = 0;
sriomaintx_m2s_bar0_start0.s.addr64 = BAR0_ADDRESS >> 48;
sriomaintx_m2s_bar0_start0.s.addr48 = BAR0_ADDRESS >> 32;
sriomaintx_m2s_bar0_start1.u32 = 0;
sriomaintx_m2s_bar0_start1.s.addr32 = (BAR0_ADDRESS >> 14) & 0x3ffff;
sriomaintx_m2s_bar0_start1.s.addr66 = 0; // BAR0_ADDRESS >> 64;
sriomaintx_m2s_bar0_start1.s.enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR0_START0(0),
sriomaintx_m2s_bar0_start0.u32))
return -1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_M2S_BAR0_START1(0),
sriomaintx_m2s_bar0_start1.u32))
return -1;
dev_info(&dev->dev, "BAR0 0x%016llx - 0x%016llx\n", BAR0_ADDRESS,
BAR0_ADDRESS + BAR0_SIZE - 1);
/* Set enables */
sriomaintx_core_enables.u32 = 0;
sriomaintx_core_enables.s.imsg1 = 1;
sriomaintx_core_enables.s.imsg0 = 1;
sriomaintx_core_enables.s.doorbell = 1;
sriomaintx_core_enables.s.memory = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_CORE_ENABLES(0),
sriomaintx_core_enables.u32))
return -1;
/* Enable transaction mastering */
if (rio_read_config_32(dev, CVMX_SRIOMAINTX_PORT_GEN_CTL(0),
&sriomaintx_port_gen_ctl.u32))
return -1;
sriomaintx_port_gen_ctl.s.menable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_PORT_GEN_CTL(0),
sriomaintx_port_gen_ctl.u32))
return -1;
/* Set link I/O enabled */
if (rio_read_config_32(dev, CVMX_SRIOMAINTX_PORT_0_CTL(0),
&sriomaintx_port_0_ctl.u32))
return -1;
sriomaintx_port_0_ctl.s.o_enable = 1;
sriomaintx_port_0_ctl.s.i_enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_PORT_0_CTL(0),
sriomaintx_port_0_ctl.u32))
return -1;
if (rio_request_inb_dbell(dev->net->hport, dev, 0, 1,
cn6xxx_doorbell)) {
dev_err(&dev->dev, "Register for incomming doorbells failed\n");
return -1;
}
for (index=0; index<16; index++) {
cvmx_sriomaintx_bar1_idxx_t sriomaintx_bar1_idxx;
sriomaintx_bar1_idxx.u32 = 0;
sriomaintx_bar1_idxx.s.la = index;
sriomaintx_bar1_idxx.s.enable = 1;
if (rio_write_config_32(dev, CVMX_SRIOMAINTX_BAR1_IDXX(index, 0),
sriomaintx_bar1_idxx.u32))
return -1;
}
dev_info(&dev->dev, "SLI_MAC_CREDIT_CNT = 0x%llx\n", c6xxx_read_bar0(dev, CVMX_SLI_MAC_CREDIT_CNT));
if (rio_send_doorbell(dev, 0))
dev_err(&dev->dev, "Sending doorbell failed\n");
if (rio_send_doorbell(dev, 1))
dev_err(&dev->dev, "Sending doorbell failed\n");
return 0;
}
