// There has been a change in state. Update the end point.
static void
usbs_state_notify (usbs_control_endpoint * pcep)
{
static int old_state = USBS_STATE_CHANGE_POWERED;
int state = pcep->state & USBS_STATE_MASK;
if (pcep->state != old_state) {
usbs_end_all_transfers (-EPIPE);
switch (state) {
case USBS_STATE_DETACHED:
case USBS_STATE_ATTACHED:
case USBS_STATE_POWERED:
// Nothing to do
break;
case USBS_STATE_DEFAULT:
HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, 0);
break;
case USBS_STATE_ADDRESSED:
HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, AT91_UDP_GLB_FADDEN);
break;
case USBS_STATE_CONFIGURED:
HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_GLB_STATE, AT91_UDP_GLB_CONFG);
break;
default:
CYG_FAIL("Unknown endpoint state");
}
if (pcep->state_change_fn) {
(*pcep->state_change_fn) (pcep, 0, pcep->state, old_state);
}
old_state = pcep->state;
}
}
void
exception_handler(HAL_SavedRegisters *regs)
{
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
// diag_printf("Exception! Frame: %x\n", regs);
// show_regs(regs);
static int gdb_active;
if (gdb_active == 0) {
gdb_active = 1;
_hal_registers = regs;
__handle_exception();
gdb_active = 0;
}
#elif defined(CYGPKG_KERNEL_EXCEPTIONS)
// We should decode the vector and pass a more appropriate
// value as the second argument. For now we simply pass a
// pointer to the saved registers. We should also divert
// breakpoint and other debug vectors into the debug stubs.
cyg_hal_deliver_exception( regs->vector, (CYG_ADDRWORD)regs );
#else
CYG_FAIL("Exception!!!");
#endif
return;
}
externC void cyg_drv_dsr_unlock()
{
CYG_REPORT_FUNCTION();
do
{
if( dsr_disable_counter == 1 )
{
call_dsrs();
}
HAL_REORDER_BARRIER();
dsr_disable_counter = 0;
HAL_REORDER_BARRIER();
// Check that no DSRs have been posted between calling
// call_dsrs() and zeroing dsr_disable_counter. If so,
// loop back and call them.
if( dsr_list != NULL )
{
dsr_disable_counter = 1;
continue;
}
CYG_REPORT_RETURN();
return;
} while(1);
CYG_FAIL( "Should not be executed" );
}
void
cyg_hal_exception_handler(HAL_SavedRegisters *regs)
{
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
// If we caught an exception inside the stubs, see if we were expecting it
// and if so jump to the saved address
if (__mem_fault_handler) {
regs->pc = (CYG_ADDRWORD)__mem_fault_handler;
return; // Caught an exception inside stubs
}
_hal_registers = regs;
__handle_exception();
#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && defined(CYGPKG_HAL_EXCEPTIONS)
// We should decode the vector and pass a more appropriate
// value as the second argument. For now we simply pass a
// pointer to the saved registers. We should also divert
// breakpoint and other debug vectors into the debug stubs.
cyg_hal_deliver_exception( regs->vector>>8, (CYG_ADDRWORD)regs );
#else
CYG_FAIL("Exception!!!");
#endif
return;
}
void cyg_hal_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data,
CYG_ADDRWORD stackpointer )
{
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
// Set the pointer to the registers of the current exception
// context. At entry the GDB stub will expand the
// HAL_SavedRegisters structure into a (bigger) register array.
_hal_registers = (HAL_SavedRegisters *)stackpointer;
__handle_exception();
#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
defined(CYGPKG_HAL_EXCEPTIONS)
// We should decode the vector and pass a more appropriate
// value as the second argument. For now we simply pass a
// pointer to the saved registers. We should also divert
// breakpoint and other debug vectors into the debug stubs.
cyg_hal_deliver_exception( vector, stackpointer );
#else
CYG_FAIL("Exception!!!");
#endif
return;
}
void hal_deliver_exception( HAL_SavedRegisters *regs )
{
// Special case handler for code which has chosen to take care
// of data exceptions (i.e. code which expects them to happen)
// This is common in discovery code, e.g. checking for a particular
// device which may generate an exception when probing if the
// device is not present
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
if (__mem_fault_handler )
{
regs->u.exception.pc = (unsigned long)__mem_fault_handler;
return; // Caught an exception inside stubs
}
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
_hal_registers = regs;
__handle_exception();
#elif defined(CYGPKG_KERNEL_EXCEPTIONS)
cyg_hal_deliver_exception( regs->u.exception.vector, (CYG_ADDRWORD)regs );
#else
CYG_FAIL("Exception!!!");
#endif
}
void hal_diag_write_char(char c)
{
static int diag_index = 0;
static unsigned char diag_buffer[128];
CYG_ASSERT(diag_index < 128, "Diagnostic buffer overflow");
diag_buffer[diag_index++] = (unsigned char) c;
if (('\n' == c) || (128 == diag_index)) {
if ((-1 != auxiliary_console_id) && synth_auxiliary_running) {
synth_auxiliary_xchgmsg(auxiliary_console_id, 0, 0, 0, diag_buffer, diag_index, (int *) 0, (unsigned char*) 0, (int *)0, 0);
diag_index = 0;
} else {
int written;
unsigned char* next = diag_buffer;
while (diag_index > 0) {
written = cyg_hal_sys_write(1, next, diag_index);
if (written > 0) {
diag_index -= written;
next += written;
} else if ((-CYG_HAL_SYS_EINTR != written) && (-CYG_HAL_SYS_EAGAIN != written)) {
CYG_FAIL("Unexpected error writing to stdout.");
diag_index = 0;
break;
}
}
CYG_ASSERT(0 == diag_index, "All data should have been written out");
diag_index = 0;
cyg_hal_sys_fdatasync(1);
}
}
}
externC cyg_uint32
hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
CYG_TRACE1(true, "Interrupt: %d", vector);
CYG_FAIL("Spurious Interrupt!!!");
return 0;
}
void
hal_spurious_IRQ(HAL_SavedRegisters *regs)
{
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
exception_handler(regs);
#else
CYG_FAIL("Spurious interrupt!!");
#endif
}
// Note: The PINTs can be masked and configured individually, even
// though there are only two vectors. Maybe add some fake vectors just
// for masking/configuring?
void
hal_interrupt_configure(int vector, int level, int up)
{
#if (CYGARC_SH_MOD_INTC >= 2)
if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
&& (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
cyg_uint16 icr1, ss, mask;
ss = 0;
mask = CYGARC_REG_ICR1_SENSE_UP|CYGARC_REG_ICR1_SENSE_LEVEL;
if (up) ss |= CYGARC_REG_ICR1_SENSE_UP;
if (level) ss |= CYGARC_REG_ICR1_SENSE_LEVEL;
CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
switch( (vector) ) {
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ5_shift;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ4_shift;
break;
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ3_shift;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ2_shift;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ1_shift;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
ss <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
mask <<= CYGARC_REG_ICR1_SENSE_IRQ0_shift;
break;
#endif
default:
CYG_FAIL("Unhandled interrupt vector");
}
HAL_READ_UINT16(CYGARC_REG_ICR1, icr1);
icr1 &= ~mask;
icr1 |= ss;
HAL_WRITE_UINT16(CYGARC_REG_ICR1, icr1);
}
#endif
CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vector, level, up);
}
/* Put a register into the GDB register structure */
void
put_register (regnames_t reg, target_register_t value)
{
GDB_Registers* gdb_regs;
gdb_regs = (GDB_Registers*)_registers;
if (reg >= R0 && reg <= MDL) {
gdb_regs->r[reg] = value;
} else {
CYG_FAIL("Attempt to write to non-existent register ");
}
}
externC void
hal_set_gdb_registers(HAL_SavedRegisters* ecos_regs, CYG_ADDRWORD* gdb_regs)
{
int i;
for (i = 0; i < 15; i++) {
ecos_regs->da[i] = gdb_regs[i];
}
if (gdb_regs[15] != (CYG_ADDRWORD) &(ecos_regs[1])) {
CYG_FAIL("gdb has requested a thread context switch - not supported,");
}
HAL_CONTEXT_PCSR_SET_SR(ecos_regs, gdb_regs[16]);
HAL_CONTEXT_PCSR_SET_PC(ecos_regs, gdb_regs[17]);
}
///
/// Initialize the ICAP
///
void icap_init(void){
CYG_REPORT_FUNCTION();
XStatus Status;
icap_config = XHwIcap_LookupConfig(HWICAP_DEVICEID);
Status = XHwIcap_CfgInitialize(&HwIcap, &icap_config, icap_config->BaseAddress);
if (Status != XST_SUCCESS)
{
switch (Status) {
case XST_INVALID_PARAM:
diag_printf("HWICAP: invalid parameter\n");
break;
case XST_FAILURE:
diag_printf("HWICAP: failure\n");
break;
case XST_DEVICE_IS_STARTED:
diag_printf("HWICAP: device already started\n");
break;
case XST_DEVICE_NOT_FOUND:
diag_printf("HWICAP: device not found\n");
break;
default:
diag_printf("HWICAP: failed with return value %d\n", Status);
}
CYG_FAIL("failed to initialize icap\naborting\n");
}
// Run self test
Status = XHwIcap_SelfTest(&HwIcap);
if (Status != XST_SUCCESS) {
CYG_FAIL("HWICAP: self-test failed\n");
}
cyg_mutex_init(&icap_mutex);
CYG_REPORT_RETURN();
}
///
/// Load a bitstream via ICAP
///
/// @param bitstream pointer to the bitstream array
/// @param length length of bitstream in bytes
///
void icap_load(unsigned char * bitstream, size_t length){
XStatus status;
if (!cyg_mutex_lock(&icap_mutex)) {
CYG_FAIL("mutex lock failed, aborting thread\n");
} else {
// wait until ICAP is ready
while (HwIcap.IsTransferInProgress) {
diag_printf("icap_load(): transfer in progress, waiting...\n");
cyg_thread_delay(1);
}
while (! (XHwIcap_GetStatusReg(&HwIcap) & XHI_SR_DONE_MASK)) {
diag_printf("icap_load(): device busy, waiting...\n");
cyg_thread_delay(1);
}
status = XHwIcap_DeviceWrite(&HwIcap, (Xuint32*)bitstream, length/4);
if (status != XST_SUCCESS)
{
if(status == XST_DEVICE_BUSY) diag_printf("HWICAP: device busy\n");
if(status == XST_INVALID_PARAM) diag_printf("HWICAP: invalid parameter\n");
CYG_FAIL("failed to load bitstream\naborting\n");
}
// wait until ICAP is ready
while (HwIcap.IsTransferInProgress) {
diag_printf("icap_load(): transfer in progress, waiting...\n");
cyg_thread_delay(1);
}
while (! (XHwIcap_GetStatusReg(&HwIcap) & XHI_SR_DONE_MASK)) {
diag_printf("icap_load(): device busy, waiting...\n");
cyg_thread_delay(1);
}
cyg_mutex_unlock(&icap_mutex);
}
}
///
/// Initialize the external "ICAP"
///
void ecap_init(void){
char *address;
unsigned int port;
address = string(UPBFUN_RECONOS_ECAP_HOST);
port = UPBFUN_RECONOS_ECAP_PORT;
if ((conn_s = socket(AF_INET, SOCK_STREAM, 0)) < 0) {
CYG_FAIL("unable to create socket");
}
memset(&servaddr, 0, sizeof(servaddr));
servaddr.sin_family = AF_INET;
servaddr.sin_port = htons(port);
if (inet_aton(address, &servaddr.sin_addr) <= 0) {
CYG_FAIL("invalid remote IP address");
}
if (connect(conn_s, (struct sockaddr *) &servaddr, sizeof(servaddr)) < 0) {
CYG_FAIL("can't connect()");
}
}
///
/// Load a bitstream via the external "ICAP"
///
/// @param bitstream pointer to the bitstream struct
///
void ecap_load(reconos_bitstream_t *bitstream) {
char recv_buf[80];
ssize_t send_len, recv_len;
send_len = Writeline(conn_s, bitstream->filename, strlen(bitstream->filename));
CYG_ASSERT(send_len = strlen(bitstream->filename), "Error while writing to ECAP");
recv_len = Readline(conn_s, recv_buf, 80);
#ifdef UPBDBG_RECONOS_DEBUG
diag_printf("\t\tECAP says: %s", recv_buf);
#endif
if ( recv_buf[0] != 'O' || recv_buf[1] != 'K' ) {
CYG_FAIL("ecap reconfiguration failed");
}
}
externC cyg_uint32 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
// For some reason I seem to be geting spurious interrupts on
// interrupt 0x27(39). This is the parallel port. This is masked
// in the PIC so the exact reason for these is a mystery. They do
// appear to be real interrupts since they always appear just
// after a clear of the interrupt flag, and the stack shows a
// proper interrupt context being pushed by the hardware. This may
// be some feature of the Celeron CPU I am using.
if( vector == 0x27 )
return 2;
diag_printf("hal_arch_default_isr: %d (data: %d)\n", vector,data);
CYG_FAIL("Spurious Interrupt!!!");
return 0;
}
// Return the size of the block which is at the given address
static size_t
flash_block_size(struct cyg_flash_dev *dev, const cyg_flashaddr_t addr)
{
int i;
size_t offset;
CYG_ASSERT((addr >= dev->start) && (addr <= dev->end), "Not inside device");
offset = addr - dev->start;
for (i=0; i < dev->num_block_infos; i++) {
if (offset < (dev->block_info[i].blocks * dev->block_info[i].block_size))
return dev->block_info[i].block_size;
offset = offset -
(dev->block_info[i].blocks * dev->block_info[i].block_size);
}
CYG_FAIL("Programming error");
return 0;
}
cyg_uint32
hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
cyg_uint32 result;
#if (defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) \
|| defined(CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT)) && \
(defined(CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT) || \
defined(CYGHWR_HAL_GDB_PORT_VECTOR) && \
defined(HAL_CTRLC_ISR))
#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
#if CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
int gdb_vector = -1;
// This check only to avoid crash on older stubs in case of unhandled
// interrupts. It is a bit messy, but required in a transition period.
#ifndef CYGSEM_HAL_ROM_MONITOR
if (CYGNUM_CALL_IF_TABLE_VERSION_CALL_HACK ==
(CYGACC_CALL_IF_VERSION() & CYGNUM_CALL_IF_TABLE_VERSION_CALL_MASK))
#endif
{
hal_virtual_comm_table_t* __chan = CYGACC_CALL_IF_DEBUG_PROCS();
if (__chan)
gdb_vector = CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_DBG_ISR_VECTOR);
}
if( CYGHWR_HAL_GDB_PORT_VECTORS_MATCH(vector, gdb_vector) )
#else
// Old code using hardwired channels. This should go away eventually.
if( vector == CYGHWR_HAL_GDB_PORT_VECTOR )
#endif
#endif
{
result = HAL_CTRLC_ISR( vector, data );
if( 0 != result ) return result;
}
#endif
result = hal_arch_default_isr (vector, data);
if( 0 != result) return result;
CYG_TRACE2(true, "Interrupt: %d, Data: 0x%08x", vector, data);
CYG_FAIL("Spurious Interrupt!!!");
return 0;
}
__externC void
__eprintf (const char *string, const char *expression,
unsigned int line, const char *filename)
{
#ifdef CYGINT_ISO_STDIO_FORMATTED_IO
fprintf(stderr, string, expression, line, filename);
#else
diag_printf(string, expression, line, filename);
#endif
#ifdef CYGINT_ISO_STDIO_FILEACCESS
fflush (stderr);
#endif
#if CYGINT_ISO_EXIT
abort();
#else
CYG_FAIL( "Aborting" );
for (;;);
#endif
} // __eprintf()
void
hal_interrupt_unmask(int vector)
{
CYG_BYTE ier;
const struct int_regs *regs=&interrupt_registers[vector-CYGNUM_HAL_INTERRUPT_EXTERNAL_0];
if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
HAL_READ_UINT8(CYGARC_TCSR,ier);
ier |= 0x20;
HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | ier);
} else {
if ((vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0) && regs->ier) {
HAL_READ_UINT8(regs->ier,ier);
ier |= regs->mask;
HAL_WRITE_UINT8(regs->ier,ier);
} else {
CYG_FAIL("Unknown interrupt vector");
}
}
}
void
exception_handler(HAL_SavedRegisters *regs)
{
// Special case handler for code which has chosen to take care
// of data exceptions (i.e. code which expects them to happen)
// This is common in discovery code, e.g. checking for a particular
// device which may generate an exception when probing if the
// device is not present
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
if (__mem_fault_handler &&
regs->vector == CYGNUM_HAL_EXCEPTION_DATA_ACCESS) {
regs->pc = (unsigned long)__mem_fault_handler;
return; // Caught an exception inside stubs
}
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) && !defined(CYGPKG_CYGMON)
if (++exception_level == 1) __take_over_debug_traps();
_hal_registers = regs;
__handle_exception();
if (--exception_level == 0) __restore_debug_traps();
#elif defined(CYGPKG_KERNEL_EXCEPTIONS)
// We should decode the vector and pass a more appropriate
// value as the second argument. For now we simply pass a
// pointer to the saved registers. We should also divert
// breakpoint and other debug vectors into the debug stubs.
cyg_hal_deliver_exception( regs->vector, (CYG_ADDRWORD)regs );
#else
CYG_FAIL("Exception!!!");
#endif
return;
}
int main(int argc, char** argv)
{
CYG_ASSERT( true, message);
CYG_ASSERT( false, message);
CYG_ASSERTC(true);
CYG_ASSERTC(false);
CYG_FAIL(message);
CYG_CHECK_DATA_PTR( &argc, message);
CYG_CHECK_DATA_PTR( 0, message);
CYG_CHECK_FUNC_PTR( &main, message);
CYG_CHECK_FUNC_PTR( 0, message);
CYG_CHECK_DATA_PTRC(&argc);
CYG_CHECK_DATA_PTRC(0);
CYG_CHECK_FUNC_PTRC(&main);
CYG_CHECK_FUNC_PTRC(0);
CYG_PRECONDITION(true, message);
CYG_PRECONDITION(false, message);
CYG_PRECONDITIONC(true);
CYG_PRECONDITIONC(false);
CYG_POSTCONDITION(true, message);
CYG_POSTCONDITION(false, message);
CYG_POSTCONDITIONC(true);
CYG_POSTCONDITIONC(false);
CYG_LOOP_INVARIANT(true, message);
CYG_LOOP_INVARIANT(false, message);
CYG_LOOP_INVARIANTC(true);
CYG_LOOP_INVARIANTC(false);
CYG_INVARIANT(true, message);
CYG_INVARIANT(false, message);
CYG_INVARIANTC(true);
CYG_INVARIANTC(false);
CYG_TEST_PASS_FINISH("disabled assertions in C code do nothing");
return 0;
}
void
hal_interrupt_configure(int vector,int level,int up)
{
CYG_WORD iscr,mask;
CYG_WORD *iscr_ptr;
int conf=1;
if (level) conf = 0;
if (up) conf = 2;
CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
if (vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 &&
vector <= CYGNUM_HAL_INTERRUPT_EXTERNAL_15) {
iscr_ptr = (vector <= CYGNUM_HAL_INTERRUPT_EXTERNAL_7)?CYGARC_ISCRL:CYGARC_ISCRH;
mask = 3 << ((vector - CYGNUM_HAL_INTERRUPT_EXTERNAL_0) & 7) * 2;
HAL_READ_UINT16(iscr_ptr,iscr);
iscr &= ~mask;
iscr |= conf << ((vector - CYGNUM_HAL_INTERRUPT_EXTERNAL_0) & 7) * 2;
HAL_WRITE_UINT16(iscr_ptr,iscr);
} else {
CYG_FAIL("Unhandled interrupt vector");
}
}
// Get info about the current block, i.e. base and size.
static void
strata_get_block_info(struct cyg_flash_dev* dev, const cyg_flashaddr_t addr, cyg_flashaddr_t* block_start, size_t* block_size)
{
cyg_uint32 i;
size_t offset = addr - dev->start;
cyg_flashaddr_t result;
result = dev->start;
for (i = 0; i < dev->num_block_infos; i++) {
if (offset < (dev->block_info[i].blocks * dev->block_info[i].block_size)) {
offset -= (offset % dev->block_info[i].block_size);
*block_start = result + offset;
*block_size = dev->block_info[i].block_size;
return;
}
result += (dev->block_info[i].blocks * dev->block_info[i].block_size);
offset -= (dev->block_info[i].blocks * dev->block_info[i].block_size);
}
CYG_FAIL("Address out of range of selected flash device");
}
externC cyg_uint32
hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
CYG_TRACE1(true, "Interrupt: %d", vector);
#ifndef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
#ifdef CYGDBG_HAL_CTRLC_ISR
// then see if it is an incoming character interrupt and break
// into the stub ROM if the char is a ^C.
if ( CYGDBG_HAL_CTRLC_ISR( vector, data ) )
return 1; // interrupt handled
#endif
#endif
#endif
diag_printf("Spurious Interrupt!!! - vector: %d, data: %x\n", vector,
data);
CYG_FAIL("Spurious Interrupt!!!");
return 0;
}
void
hal_interrupt_acknowledge(int vector)
{
#if (CYGARC_SH_MOD_INTC >= 2)
if ( (vector) >= CYGNUM_HAL_INTERRUPT_IRQ_IRQ0
&& (vector) <= CYGNUM_HAL_INTERRUPT_IRQ_IRQ5) {
cyg_uint8 irr0;
HAL_READ_UINT8(CYGARC_REG_IRR0, irr0);
switch ( vector ) {
#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
irr0 &= ~CYGARC_REG_IRR0_IRQ0;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
irr0 &= ~CYGARC_REG_IRR0_IRQ1;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
irr0 &= ~CYGARC_REG_IRR0_IRQ2;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
irr0 &= ~CYGARC_REG_IRR0_IRQ3;
break;
#endif
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
irr0 &= ~CYGARC_REG_IRR0_IRQ4;
break;
case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
irr0 &= ~CYGARC_REG_IRR0_IRQ5;
break;
default:
CYG_FAIL("Unhandled interrupt vector");
}
HAL_WRITE_UINT8(CYGARC_REG_IRR0, irr0);
}
#endif
CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vector);
}
void
hal_interrupt_acknowledge(int vector)
{
CYG_BYTE isr;
const struct int_regs *regs=&interrupt_registers[vector-CYGNUM_HAL_INTERRUPT_EXTERNAL_0];
if (vector >= CYGNUM_HAL_INTERRUPT_DEND0A &&
vector <= CYGNUM_HAL_INTERRUPT_DEND1B)
return;
if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
HAL_READ_UINT8(CYGARC_TCSR,isr);
isr &= ~0x80;
HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | isr);
} else {
if ((vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0) && regs->isr) {
HAL_READ_UINT8(regs->isr,isr);
isr &= ~(regs->status);
HAL_WRITE_UINT8(regs->isr,isr);
} else {
CYG_FAIL("Unknown interrupt vector");
}
}
}
static void
reset(void)
{
CYGARC_HAL_SAVE_GP();
// With luck, the platform defines some magic that will cause a hardware
// reset.
#ifdef HAL_PLATFORM_RESET
HAL_PLATFORM_RESET();
#endif
#ifdef HAL_PLATFORM_RESET_ENTRY
// If that's not the case (above is an empty statement) there may
// be defined an address we can jump to - and effectively
// reinitialize the system. Not quite as good as a reset, but it
// is often enough.
goto *HAL_PLATFORM_RESET_ENTRY;
#else
#error " no RESET_ENTRY"
#endif
CYG_FAIL("Reset failed");
CYGARC_HAL_RESTORE_GP();
}
void
hal_interrupt_unmask(int vector)
{
switch( (vector) ) {
case CYGNUM_HAL_INTERRUPT_NMI:
/* fall through */
case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:
/* Normally can only be masked by fiddling Imask in SR,
but some platforms use external interrupt controller,
so allow regular handling. */
// fall through
case CYGNUM_HAL_INTERRUPT_TMU0_TUNI0 ... CYGNUM_HAL_ISR_MAX:
cyg_hal_IMASK_table[vector] = 1;
hal_interrupt_update_level(vector);
break;
case CYGNUM_HAL_INTERRUPT_RESERVED_1E0:
case CYGNUM_HAL_INTERRUPT_RESERVED_3E0:
/* Do nothing for these reserved vectors. */
break;
default:
CYG_FAIL("Unknown interrupt vector");
break;
}
}
