CY_CFG_SECTION
static void ClockSetup(void)
{
/* Enable HALF_EN before trimming for the flash accelerator. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));
/* Trim IMO BG based on desired frequency. */
SetIMOBGTrims(24u);
/* Going less than or equal to 24MHz, so update the clock speed then adjust trim value. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM2), (25u));
CyDelayCycles(5u);
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_IMO_TRIM1), (CY_GET_REG8((void *)CYREG_SFLASH_IMO_TRIM21)));
CyDelayUs(5u);
/* Disable HALF_EN since it is not required at this IMO frequency. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT02), 0x00000013u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT07), 0x00000010u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT13), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT15), 0x00000021u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x82000000u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000000u);
/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x8000000Du);
/* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B00), 0x80000017u);
/* CYDEV_CLK_DIVIDER_A01 Starting address: CYDEV_CLK_DIVIDER_A01 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A01), 0x800001F3u);
/* CYDEV_CLK_DIVIDER_B01 Starting address: CYDEV_CLK_DIVIDER_B01 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B01), 0xC00001DFu);
/* CYDEV_CLK_DIVIDER_FRAC_A00 Starting address: CYDEV_CLK_DIVIDER_FRAC_A00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_FRAC_A00), 0x800C0010u);
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0002u, /* Base address: 0x400F0000 Count: 2 */
0x400F3004u, /* Base address: 0x400F3000 Count: 4 */
0x400F3129u, /* Base address: 0x400F3100 Count: 41 */
0x400F3241u, /* Base address: 0x400F3200 Count: 65 */
0x400F333Du, /* Base address: 0x400F3300 Count: 61 */
0x400F4005u, /* Base address: 0x400F4000 Count: 5 */
0x400F4105u, /* Base address: 0x400F4100 Count: 5 */
0x400F4203u, /* Base address: 0x400F4200 Count: 3 */
0x400F4305u, /* Base address: 0x400F4300 Count: 5 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x72u, 0x01u},
{0x81u, 0x0Fu},
{0x38u, 0xA0u},
{0x3Eu, 0x50u},
{0x58u, 0x04u},
{0x5Fu, 0x01u},
{0x05u, 0x14u},
{0x06u, 0x02u},
{0x07u, 0x40u},
{0x0Cu, 0x80u},
{0x0Du, 0x02u},
{0x0Eu, 0x28u},
{0x15u, 0x10u},
{0x17u, 0x15u},
{0x18u, 0x05u},
{0x1Du, 0x84u},
{0x1Eu, 0x86u},
{0x24u, 0x28u},
{0x25u, 0x07u},
{0x26u, 0x14u},
{0x27u, 0x28u},
{0x2Du, 0x90u},
{0x2Eu, 0x01u},
{0x2Fu, 0x20u},
{0x37u, 0x29u},
{0x3Du, 0x02u},
{0x3Eu, 0x10u},
{0x3Fu, 0x80u},
{0x45u, 0x82u},
{0x47u, 0x28u},
{0x4Du, 0x08u},
{0x56u, 0x42u},
{0x57u, 0x54u},
{0x67u, 0x01u},
{0x6Eu, 0x11u},
{0x6Fu, 0x55u},
{0x74u, 0x80u},
{0x75u, 0x80u},
{0x77u, 0x02u},
{0xC0u, 0xF0u},
{0xC2u, 0xF0u},
{0xC4u, 0x70u},
{0xCAu, 0xF0u},
{0xCCu, 0xE0u},
{0xCEu, 0xB0u},
{0xD0u, 0xF0u},
{0xD8u, 0x10u},
{0x00u, 0xCDu},
{0x04u, 0x10u},
{0x05u, 0x02u},
{0x06u, 0x60u},
{0x08u, 0x72u},
{0x0Au, 0x08u},
{0x0Cu, 0x4Du},
{0x0Eu, 0x80u},
{0x0Fu, 0x04u},
{0x10u, 0x12u},
{0x12u, 0x64u},
{0x16u, 0x80u},
{0x17u, 0x03u},
{0x18u, 0x01u},
{0x1Au, 0x32u},
{0x1Cu, 0x02u},
{0x1Eu, 0x0Du},
{0x1Fu, 0x01u},
{0x20u, 0xCDu},
{0x23u, 0x04u},
{0x24u, 0x8Du},
{0x26u, 0x40u},
{0x28u, 0xCDu},
{0x2Fu, 0x03u},
{0x32u, 0x80u},
{0x34u, 0x70u},
{0x35u, 0x04u},
{0x36u, 0x0Fu},
{0x37u, 0x03u},
{0x3Au, 0xA0u},
{0x3Eu, 0x04u},
{0x3Fu, 0x10u},
{0x54u, 0x09u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Cu, 0x11u},
{0x5Du, 0x10u},
{0x5Fu, 0x01u},
{0x80u, 0x0Eu},
{0x81u, 0x02u},
{0x83u, 0x0Du},
{0x85u, 0x09u},
{0x87u, 0x06u},
{0x89u, 0x03u},
{0x8Bu, 0x0Cu},
{0x90u, 0x05u},
{0x92u, 0x0Au},
{0x94u, 0x03u},
{0x96u, 0x04u},
{0xA4u, 0x04u},
{0xA6u, 0x09u},
{0xADu, 0x05u},
{0xAFu, 0x0Au},
{0xB0u, 0x0Fu},
{0xB7u, 0x0Fu},
{0xB8u, 0x02u},
{0xBBu, 0x80u},
{0xD4u, 0x40u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDCu, 0x11u},
{0xDDu, 0x10u},
{0xDFu, 0x01u},
{0x01u, 0x02u},
{0x04u, 0x04u},
{0x07u, 0x49u},
{0x09u, 0x06u},
{0x0Cu, 0x01u},
{0x0Du, 0x0Au},
{0x0Eu, 0x09u},
{0x0Fu, 0x20u},
{0x13u, 0x08u},
{0x17u, 0x16u},
{0x19u, 0x02u},
{0x1Cu, 0x14u},
{0x1Du, 0x10u},
{0x1Eu, 0x01u},
{0x1Fu, 0x20u},
{0x23u, 0x01u},
{0x26u, 0xA0u},
{0x28u, 0x01u},
{0x2Cu, 0x01u},
{0x2Du, 0x02u},
{0x36u, 0x80u},
{0x37u, 0x08u},
{0x38u, 0x28u},
{0x3Bu, 0x01u},
{0x3Du, 0x48u},
{0x5Du, 0x08u},
{0x5Eu, 0x82u},
{0x5Fu, 0x10u},
{0x60u, 0x11u},
{0x63u, 0x08u},
{0x66u, 0x80u},
{0x6Du, 0x40u},
{0x86u, 0x84u},
{0x8Au, 0x60u},
{0x8Bu, 0x10u},
{0x8Cu, 0x01u},
{0x8Du, 0x08u},
{0x8Eu, 0x80u},
{0x90u, 0x28u},
{0x92u, 0x04u},
{0x97u, 0x01u},
{0x99u, 0x08u},
{0x9Au, 0x40u},
{0x9Bu, 0x5Fu},
{0x9Du, 0x10u},
{0xA1u, 0x06u},
{0xA2u, 0x45u},
{0xA3u, 0x14u},
{0xA7u, 0x20u},
{0xB4u, 0x05u},
{0xB5u, 0x04u},
{0xC0u, 0xF8u},
{0xC2u, 0xFCu},
{0xC4u, 0x74u},
{0xCAu, 0x98u},
{0xCCu, 0x50u},
{0xCEu, 0x57u},
{0xD6u, 0xF0u},
{0xD8u, 0x1Eu},
{0xE2u, 0x60u},
{0xEAu, 0x10u},
{0x57u, 0x80u},
{0x5Eu, 0x80u},
{0x5Fu, 0x02u},
{0xD4u, 0x40u},
{0xD6u, 0xA0u},
{0x8Au, 0x40u},
{0x8Fu, 0x80u},
{0xA6u, 0x40u},
{0xA7u, 0x80u},
{0xB7u, 0x02u},
{0x6Cu, 0x40u},
{0x70u, 0x08u},
{0xDCu, 0x03u},
{0x54u, 0x02u},
{0xA0u, 0x02u},
{0xB4u, 0x4Au},
{0xD6u, 0x04u},
{0xECu, 0x0Au},
{0x01u, 0x0Au},
{0x10u, 0x0Au},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
CYPACKED typedef struct {
void CYFAR *dest;
const void CYCODE *src;
uint16 size;
} CYPACKED_ATTR cfg_memcpy_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 128u},
{(void CYFAR *)(CYDEV_UDB_P0_ROUTE_BASE), 768u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
/* UDB_0_1_1_CONFIG Address: CYDEV_UDB_P0_U1_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_1_1_CONFIG_VAL[] = {
0x84u, 0xC1u, 0x00u, 0x32u, 0x01u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x00u, 0x12u, 0x60u, 0x84u, 0x00u, 0x00u,
0x0Au, 0x12u, 0x10u, 0x04u, 0x56u, 0x9Au, 0x09u, 0x05u, 0x07u, 0x27u, 0x38u, 0x48u, 0x84u, 0x00u, 0x00u, 0x00u,
0x04u, 0x16u, 0x80u, 0x00u, 0x80u, 0x12u, 0x04u, 0x00u, 0x84u, 0x12u, 0x00u, 0x04u, 0x00u, 0x16u, 0x00u, 0x00u,
0x08u, 0x1Du, 0x7Fu, 0x07u, 0x02u, 0xE0u, 0x80u, 0x00u, 0x08u, 0x00u, 0x00u, 0x22u, 0x00u, 0x00u, 0x51u, 0x00u,
0x43u, 0x02u, 0x10u, 0x00u, 0x00u, 0x0Eu, 0xDCu, 0xBFu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x11u, 0x11u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UDB_P0_U1_BASE), BS_UDB_0_1_1_CONFIG_VAL, 128u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
/* Copy device configuration data into registers */
for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
{
const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
void * CYDATA destPtr = mc->dest;
const void CYCODE * CYDATA srcPtr = mc->src;
uint16 CYDATA numBytes = mc->size;
CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x03003300u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE76u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x0000004Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00D80D92u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_INTCFG), 0x0000000Fu);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC2), 0x00000087u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x0000003Cu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC2), 0x0000003Cu);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC2), 0x00000003u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x0000000Eu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x000005B1u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_INTCFG), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x00000002u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00930000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x000A0000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x10700000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x000F0000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3301u, /* Base address: 0x400F3300 Count: 1 */
0x400F4002u, /* Base address: 0x400F4000 Count: 2 */
0x400F4102u, /* Base address: 0x400F4100 Count: 2 */
0x400F4304u, /* Base address: 0x400F4300 Count: 4 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0xE2u, 0x80u},
{0x53u, 0x04u},
{0xD4u, 0x20u},
{0x8Bu, 0x04u},
{0x97u, 0x08u},
{0x19u, 0x08u},
{0x89u, 0x08u},
{0xC6u, 0x08u},
{0xE2u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00000300u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x00450000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x00000004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000180u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3101u, /* Base address: 0x400F3100 Count: 1 */
0x400F322Fu, /* Base address: 0x400F3200 Count: 47 */
0x400F3326u, /* Base address: 0x400F3300 Count: 38 */
0x400F4009u, /* Base address: 0x400F4000 Count: 9 */
0x400F410Eu, /* Base address: 0x400F4100 Count: 14 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4310u, /* Base address: 0x400F4300 Count: 16 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0xE6u, 0x09u},
{0x11u, 0x09u},
{0x13u, 0x16u},
{0x14u, 0x01u},
{0x15u, 0x03u},
{0x16u, 0x06u},
{0x17u, 0x1Cu},
{0x19u, 0x05u},
{0x1Bu, 0x1Au},
{0x1Cu, 0x04u},
{0x1Eu, 0x03u},
{0x20u, 0x02u},
{0x21u, 0x11u},
{0x22u, 0x05u},
{0x23u, 0x0Eu},
{0x2Au, 0x07u},
{0x30u, 0x05u},
{0x32u, 0x03u},
{0x33u, 0x1Bu},
{0x35u, 0x17u},
{0x36u, 0x07u},
{0x37u, 0x0Fu},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Fu, 0x01u},
{0x80u, 0x04u},
{0x82u, 0x0Bu},
{0x85u, 0x02u},
{0x87u, 0x01u},
{0x8Fu, 0x03u},
{0x90u, 0x02u},
{0x91u, 0x01u},
{0x92u, 0x0Du},
{0x93u, 0x02u},
{0x98u, 0x01u},
{0x9Au, 0x0Eu},
{0x9Bu, 0x03u},
{0x9Cu, 0x08u},
{0x9Eu, 0x07u},
{0xB1u, 0x03u},
{0xB2u, 0x03u},
{0xB6u, 0x0Fu},
{0xBEu, 0x44u},
{0xBFu, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0x00u, 0x02u},
{0x0Au, 0x04u},
{0x0Bu, 0x82u},
{0x0Eu, 0x22u},
{0x17u, 0x12u},
{0x19u, 0x44u},
{0x1Eu, 0x52u},
{0x1Fu, 0x80u},
{0x22u, 0x01u},
{0x26u, 0x38u},
{0x27u, 0x12u},
{0x2Fu, 0x80u},
{0x31u, 0x02u},
{0x33u, 0x20u},
{0x36u, 0x28u},
{0x37u, 0x02u},
{0x3Bu, 0x88u},
{0x59u, 0x04u},
{0x5Au, 0x52u},
{0x61u, 0x40u},
{0x83u, 0x02u},
{0x84u, 0x01u},
{0x85u, 0x02u},
{0x86u, 0x04u},
{0x87u, 0x44u},
{0x8Au, 0x28u},
{0x8Eu, 0x01u},
{0x8Fu, 0x21u},
{0xC0u, 0x08u},
{0xC2u, 0xABu},
{0xC4u, 0x50u},
{0xCAu, 0x80u},
{0xCCu, 0xE5u},
{0xCEu, 0x0Au},
{0xD6u, 0x0Fu},
{0xD8u, 0x08u},
{0xE2u, 0x3Au},
{0xE6u, 0x8Eu},
{0x50u, 0x04u},
{0x53u, 0x01u},
{0x57u, 0x80u},
{0x5Fu, 0x40u},
{0x80u, 0x04u},
{0x87u, 0x80u},
{0xD4u, 0xE0u},
{0xD6u, 0x20u},
{0xE6u, 0x90u},
{0x52u, 0x20u},
{0x54u, 0x02u},
{0x56u, 0x08u},
{0x58u, 0x80u},
{0x82u, 0x20u},
{0x83u, 0x01u},
{0x87u, 0x40u},
{0x88u, 0x02u},
{0x8Au, 0x08u},
{0x8Cu, 0x80u},
{0x97u, 0x42u},
{0xD4u, 0xE0u},
{0xD6u, 0x20u},
{0xE6u, 0xE0u},
{0x82u, 0x40u},
{0x84u, 0x01u},
{0x08u, 0x40u},
{0x0Au, 0x20u},
{0x0Fu, 0x14u},
{0x1Au, 0x80u},
{0x1Bu, 0x20u},
{0x1Cu, 0x02u},
{0x1Fu, 0x08u},
{0x83u, 0x20u},
{0x84u, 0x40u},
{0x87u, 0x1Cu},
{0x8Eu, 0x10u},
{0x96u, 0x80u},
{0xA4u, 0x01u},
{0xC2u, 0x0Fu},
{0xC6u, 0x0Fu},
{0xE2u, 0x02u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00003333u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00003333u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x001B0000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x80000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00D20000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0xAA000000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT0_BASE), 0x0000000Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00000DB6u);
/* IOPINS0_1 Starting address: CYDEV_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT1_BASE), 0x0000008Fu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00400492u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_INTCFG), 0x00008000u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00DB6DB6u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT3_BASE), 0x000000F0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00492D80u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
static void AnalogSetDefault(void)
{
CY_SET_XTND_REG32((void CYFAR *)CYREG_CTBM0_DFT_CTRL, 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)CYREG_CTBM1_DFT_CTRL, 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)CYREG_PASS_DSAB_DSAB_CTRL, 0x00000000u);
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
{
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00990000u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00D80000u);
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00031000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC2), 0x00000020u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0003u, /* Base address: 0x400F0000 Count: 3 */
0x400F3069u, /* Base address: 0x400F3000 Count: 105 */
0x400F313Bu, /* Base address: 0x400F3100 Count: 59 */
0x400F3214u, /* Base address: 0x400F3200 Count: 20 */
0x400F3350u, /* Base address: 0x400F3300 Count: 80 */
0x400F4111u, /* Base address: 0x400F4100 Count: 17 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4301u, /* Base address: 0x400F4300 Count: 1 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x80u, 0x0Fu},
{0x82u, 0x38u},
{0x83u, 0x72u},
{0x00u, 0x80u},
{0x01u, 0x02u},
{0x02u, 0x20u},
{0x03u, 0x09u},
{0x04u, 0x20u},
{0x06u, 0xC0u},
{0x09u, 0x13u},
{0x0Au, 0x15u},
{0x0Cu, 0x40u},
{0x0Du, 0x10u},
{0x0Eu, 0x20u},
{0x10u, 0x13u},
{0x12u, 0x0Cu},
{0x14u, 0x13u},
{0x16u, 0x04u},
{0x18u, 0x03u},
{0x19u, 0x13u},
{0x1Au, 0x14u},
{0x20u, 0xE0u},
{0x24u, 0x0Au},
{0x26u, 0x14u},
{0x27u, 0x04u},
{0x28u, 0xE0u},
{0x2Du, 0x01u},
{0x2Eu, 0x08u},
{0x2Fu, 0x0Au},
{0x30u, 0x10u},
{0x31u, 0x03u},
{0x32u, 0xE0u},
{0x33u, 0x10u},
{0x34u, 0x0Fu},
{0x37u, 0x0Cu},
{0x3Au, 0x20u},
{0x3Eu, 0x01u},
{0x3Fu, 0x40u},
{0x40u, 0x23u},
{0x41u, 0x06u},
{0x45u, 0xECu},
{0x47u, 0x0Bu},
{0x48u, 0x13u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Eu, 0xF0u},
{0x4Fu, 0x44u},
{0x50u, 0x0Cu},
{0x54u, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x66u, 0xC0u},
{0x6Au, 0x40u},
{0x6Bu, 0x02u},
{0x80u, 0x10u},
{0x82u, 0x40u},
{0x84u, 0x0Cu},
{0x85u, 0x2Cu},
{0x86u, 0x71u},
{0x87u, 0x43u},
{0x88u, 0x10u},
{0x8Au, 0xACu},
{0x8Cu, 0x09u},
{0x8Eu, 0xD0u},
{0x93u, 0x0Cu},
{0x96u, 0x20u},
{0x99u, 0x71u},
{0x9Bu, 0x06u},
{0x9Eu, 0x03u},
{0xA3u, 0x08u},
{0xA4u, 0x14u},
{0xA5u, 0x71u},
{0xA7u, 0x0Eu},
{0xA8u, 0xDCu},
{0xA9u, 0x80u},
{0xAAu, 0x22u},
{0xABu, 0x13u},
{0xB3u, 0x0Fu},
{0xB4u, 0xE0u},
{0xB5u, 0x30u},
{0xB6u, 0x1Fu},
{0xB7u, 0xC0u},
{0xB9u, 0xA0u},
{0xBAu, 0x20u},
{0xBBu, 0x08u},
{0xBFu, 0x10u},
{0xC0u, 0x03u},
{0xC5u, 0x40u},
{0xC9u, 0xFFu},
{0xCAu, 0x07u},
{0xCBu, 0xFFu},
{0xCCu, 0x40u},
{0xCDu, 0x20u},
{0xCEu, 0xF0u},
{0xCFu, 0x05u},
{0xD0u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE1u, 0xA8u},
{0xE2u, 0x40u},
{0xE3u, 0x20u},
{0x00u, 0xA0u},
{0x01u, 0x09u},
{0x04u, 0x04u},
{0x05u, 0x22u},
{0x07u, 0x01u},
{0x08u, 0x10u},
{0x0Au, 0x80u},
{0x0Bu, 0x28u},
{0x0Du, 0xC0u},
{0x0Fu, 0x20u},
{0x10u, 0x81u},
{0x11u, 0x18u},
{0x15u, 0x08u},
{0x17u, 0x20u},
{0x19u, 0x28u},
{0x1Au, 0x44u},
{0x1Cu, 0x04u},
{0x1Du, 0x80u},
{0x1Fu, 0x30u},
{0x20u, 0x12u},
{0x21u, 0x01u},
{0x22u, 0x02u},
{0x25u, 0x04u},
{0x27u, 0x29u},
{0x29u, 0x08u},
{0x2Au, 0x80u},
{0x2Du, 0x02u},
{0x2Eu, 0x20u},
{0x2Fu, 0x20u},
{0x33u, 0x10u},
{0x34u, 0x01u},
{0x35u, 0x20u},
{0x37u, 0x01u},
{0x39u, 0x53u},
{0x3Du, 0x08u},
{0x42u, 0x24u},
{0x47u, 0x08u},
{0x49u, 0x01u},
{0x4Bu, 0x29u},
{0x4Du, 0x02u},
{0x51u, 0x04u},
{0x54u, 0x10u},
{0x56u, 0x20u},
{0x57u, 0x10u},
{0x58u, 0x10u},
{0x59u, 0x01u},
{0x5Au, 0x40u},
{0x5Bu, 0x04u},
{0x89u, 0x08u},
{0x8Au, 0x02u},
{0xC0u, 0xFFu},
{0xC2u, 0xAEu},
{0xC4u, 0x6Fu},
{0xCAu, 0xEAu},
{0xCCu, 0xA4u},
{0xCEu, 0x4Du},
{0xD0u, 0x46u},
{0xD2u, 0x04u},
{0xD6u, 0x0Fu},
{0x01u, 0x01u},
{0x02u, 0x04u},
{0x0Eu, 0x02u},
{0x12u, 0x02u},
{0x1Au, 0x01u},
{0x1Eu, 0x01u},
{0x2Cu, 0x08u},
{0x30u, 0x01u},
{0x32u, 0x02u},
{0x34u, 0x04u},
{0x35u, 0x01u},
{0x36u, 0x08u},
{0x3Eu, 0x45u},
{0x3Fu, 0x10u},
{0x54u, 0x18u},
{0x56u, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x00u, 0x80u},
{0x01u, 0x08u},
{0x03u, 0x48u},
{0x06u, 0x80u},
{0x07u, 0x02u},
{0x09u, 0x80u},
{0x0Au, 0x26u},
{0x0Bu, 0x40u},
{0x0Du, 0x11u},
{0x0Eu, 0x01u},
{0x12u, 0x03u},
{0x13u, 0x28u},
{0x15u, 0x80u},
{0x19u, 0x01u},
{0x1Au, 0x0Du},
{0x1Bu, 0x08u},
{0x1Cu, 0x04u},
{0x1Fu, 0x85u},
{0x20u, 0x08u},
{0x22u, 0x18u},
{0x23u, 0x42u},
{0x27u, 0x04u},
{0x2Au, 0x89u},
{0x2Bu, 0x08u},
{0x31u, 0x10u},
{0x32u, 0x05u},
{0x33u, 0x40u},
{0x38u, 0x04u},
{0x3Au, 0x22u},
{0x3Bu, 0x40u},
{0x3Cu, 0x08u},
{0x3Eu, 0x08u},
{0x3Fu, 0x01u},
{0x40u, 0x10u},
{0x42u, 0x05u},
{0x48u, 0x05u},
{0x51u, 0x11u},
{0x59u, 0x01u},
{0x5Du, 0x01u},
{0x64u, 0x80u},
{0x67u, 0x0Au},
{0x69u, 0x50u},
{0x6Bu, 0x10u},
{0x71u, 0x90u},
{0x72u, 0x20u},
{0x73u, 0x28u},
{0x80u, 0x80u},
{0x83u, 0x80u},
{0x84u, 0x40u},
{0x86u, 0x80u},
{0x89u, 0x01u},
{0x8Au, 0x08u},
{0x8Cu, 0x10u},
{0x8Fu, 0x40u},
{0x90u, 0x10u},
{0x91u, 0x80u},
{0x93u, 0x01u},
{0x95u, 0x50u},
{0x99u, 0x08u},
{0x9Au, 0x02u},
{0x9Eu, 0x80u},
{0x9Fu, 0x14u},
{0xA0u, 0x01u},
{0xA2u, 0x02u},
{0xA4u, 0x40u},
{0xA9u, 0x20u},
{0xAAu, 0x40u},
{0xB4u, 0x80u},
{0xB7u, 0x10u},
{0xC0u, 0x9Fu},
{0xC2u, 0xDFu},
{0xC4u, 0x87u},
{0xCAu, 0x0Fu},
{0xCCu, 0x0Fu},
{0xCEu, 0x8Fu},
{0xD0u, 0x0Eu},
{0xD2u, 0x0Cu},
{0xD6u, 0x81u},
{0xD8u, 0xB0u},
{0xEEu, 0x08u},
{0x03u, 0x80u},
{0x0Bu, 0x04u},
{0x67u, 0x02u},
{0x6Bu, 0x40u},
{0x6Fu, 0xA0u},
{0x83u, 0x41u},
{0x87u, 0x04u},
{0xA3u, 0x20u},
{0xAFu, 0x20u},
{0xC0u, 0x10u},
{0xC2u, 0x40u},
{0xD6u, 0x80u},
{0xDAu, 0x80u},
{0xDCu, 0x60u},
{0xE0u, 0x40u},
{0xE6u, 0xA0u},
{0xEEu, 0x10u},
{0x0Fu, 0x02u},
{0xC2u, 0x01u},
{0xAFu, 0x01u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
CYPACKED typedef struct {
void CYFAR *dest;
const void CYCODE *src;
uint16 size;
} CYPACKED_ATTR cfg_memcpy_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 640u},
{(void CYFAR *)(CYDEV_UDB_P1_ROUTE_BASE), 256u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
/* UDB_0_0_0_CONFIG Address: CYDEV_UDB_P1_U1_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_0_0_CONFIG_VAL[] = {
0x00u, 0x60u, 0x33u, 0x00u, 0x03u, 0x00u, 0x00u, 0x04u, 0x4Fu, 0x18u, 0x30u, 0x00u, 0x01u, 0x1Cu, 0x00u, 0xE2u,
0x5Cu, 0x10u, 0x23u, 0x00u, 0x7Fu, 0xE7u, 0x00u, 0x18u, 0x73u, 0x08u, 0x0Cu, 0x00u, 0x08u, 0x00u, 0x00u, 0x63u,
0x00u, 0x40u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x00u, 0x0Cu, 0x1Cu, 0x00u, 0xE1u, 0x02u, 0x24u, 0x00u, 0x00u,
0x40u, 0x1Fu, 0x2Cu, 0x60u, 0x0Fu, 0x00u, 0x1Cu, 0x80u, 0x00u, 0x80u, 0x28u, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u,
0x23u, 0x06u, 0x01u, 0x00u, 0x05u, 0x00u, 0xC0u, 0xE0u, 0x28u, 0xFFu, 0xFFu, 0xFFu, 0x62u, 0xA0u, 0xF0u, 0x41u,
0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x13u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x02u, 0x00u, 0x10u, 0x30u, 0x10u, 0x00u, 0x10u, 0x10u, 0x12u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), BS_UDB_0_0_0_CONFIG_VAL, 128u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
/* Copy device configuration data into registers */
for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
{
const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
void * CYDATA destPtr = mc->dest;
const void CYCODE * CYDATA srcPtr = mc->src;
uint16 CYDATA numBytes = mc->size;
CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00300000u);
/* FORCED_HSIOM Starting address: CYDEV_HSIOM_PORT_SEL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL0), 0x00000000u);
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_PC */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00000000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0x20000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x04000000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x0000000Eu);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x0000000Eu);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00070003u);
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00480000u);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00480000u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3003u, /* Base address: 0x400F3000 Count: 3 */
0x400F3106u, /* Base address: 0x400F3100 Count: 6 */
0x400F3302u, /* Base address: 0x400F3300 Count: 2 */
0x400F4008u, /* Base address: 0x400F4000 Count: 8 */
0x400F4105u, /* Base address: 0x400F4100 Count: 5 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4302u, /* Base address: 0x400F4300 Count: 2 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0xD6u, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0x5Cu, 0x40u},
{0x5Fu, 0x20u},
{0x67u, 0x40u},
{0x87u, 0x40u},
{0xD6u, 0x30u},
{0xD8u, 0x80u},
{0xAFu, 0x20u},
{0xB4u, 0x40u},
{0x0Fu, 0x04u},
{0x6Eu, 0x80u},
{0x73u, 0x08u},
{0x86u, 0x40u},
{0xC2u, 0x80u},
{0xDAu, 0x80u},
{0xDCu, 0x20u},
{0xE6u, 0x40u},
{0x23u, 0x08u},
{0x9Fu, 0x08u},
{0xAFu, 0x04u},
{0xC8u, 0x10u},
{0xE8u, 0x40u},
{0x01u, 0x08u},
{0xC0u, 0x08u},
{0xB5u, 0x08u},
{0xEAu, 0x02u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE99u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x0000FFFFu);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG4), 0x80000000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x00020000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000005u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00200006u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00000001u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT3_BASE), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000DB1u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC2), 0x00000002u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_PRT4_BASE), 0x0000000Du);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000D8Eu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC2), 0x0000000Du);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */
CY_SET_REG32((void CYXDATA *)(CYREG_CPUSS_FLASH_CTL), (0x0012u));
/* Start the WCO */
CySysClkWcoStart();
CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
(void)CySysClkWcoSetPowerMode(CY_SYS_CLK_WCO_LPM); /* Switch to the low power mode */
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(48u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_WDT_CONFIG Starting address: CYDEV_WDT_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
/* Enable fast start mode for XO */
CY_SET_REG32((void*)CYREG_BLE_BLERD_BB_XO, CY_GET_REG32((void*)CYREG_BLE_BLERD_BB_XO) | (uint32)0x02u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLERD_BB_XO_CAPTRIM), 0x00003E2Du);
/* Disable Crystal Stable Interrupt before enabling ECO */
CY_SET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL, CY_GET_REG32((void*)CYREG_BLE_BLESS_LL_DSM_CTRL) & (~(uint32)0x08u));
/* Start the ECO and do not check status since it is not needed for HFCLK */
(void)CySysClkEcoStart(2000u);
CyDelayUs(1500u); /* Wait to stabalize */
/* Setup phase aligned clocks */
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL1, 0x00AFE300u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF41u);
CY_SET_REG32((void *)CYREG_PERI_DIV_16_CTL0, 0x00095F00u);
CY_SET_REG32((void *)CYREG_PERI_DIV_CMD, 0x8000FF40u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
/* CYDEV_PERI_PCLK_CTL11 Starting address: CYDEV_PERI_PCLK_CTL11 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL11), 0x00000041u);
/* CYDEV_PERI_PCLK_CTL10 Starting address: CYDEV_PERI_PCLK_CTL10 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL10), 0x00000040u);
/* CYDEV_PERI_PCLK_CTL9 Starting address: CYDEV_PERI_PCLK_CTL9 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL9), 0x00000040u);
/* CYDEV_PERI_PCLK_CTL8 Starting address: CYDEV_PERI_PCLK_CTL8 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL8), 0x00000040u);
/* CYDEV_PERI_PCLK_CTL7 Starting address: CYDEV_PERI_PCLK_CTL7 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PERI_PCLK_CTL7), 0x00000040u);
(void)CyIntSetVector(8u, &CySysWdtIsr);
CyIntEnable(8u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x40000000u);
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_LL_DSM_CTRL), 0x00000000u);
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F0002u, /* Base address: 0x400F0000 Count: 2 */
0x400F304Fu, /* Base address: 0x400F3000 Count: 79 */
0x400F312Du, /* Base address: 0x400F3100 Count: 45 */
0x400F3304u, /* Base address: 0x400F3300 Count: 4 */
0x400F4002u, /* Base address: 0x400F4000 Count: 2 */
0x400F410Fu, /* Base address: 0x400F4100 Count: 15 */
0x400F420Cu, /* Base address: 0x400F4200 Count: 12 */
0x400F430Eu, /* Base address: 0x400F4300 Count: 14 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x80u, 0x0Du},
{0x81u, 0x0Du},
{0x07u, 0x09u},
{0x08u, 0x01u},
{0x0Du, 0x02u},
{0x1Bu, 0x01u},
{0x23u, 0x08u},
{0x26u, 0x03u},
{0x2Fu, 0x04u},
{0x31u, 0x01u},
{0x32u, 0x02u},
{0x33u, 0x08u},
{0x35u, 0x04u},
{0x36u, 0x01u},
{0x37u, 0x02u},
{0x3Fu, 0x44u},
{0x40u, 0x20u},
{0x41u, 0x05u},
{0x45u, 0xD1u},
{0x47u, 0x20u},
{0x48u, 0x23u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Du, 0xA0u},
{0x4Fu, 0x04u},
{0x50u, 0x18u},
{0x52u, 0x80u},
{0x54u, 0x05u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x60u, 0x40u},
{0x62u, 0xC0u},
{0x64u, 0x40u},
{0x65u, 0x40u},
{0x66u, 0xC0u},
{0x68u, 0xC0u},
{0x6Au, 0xC0u},
{0x6Cu, 0xC0u},
{0x6Eu, 0xC0u},
{0x83u, 0x01u},
{0x94u, 0x01u},
{0x9Eu, 0x04u},
{0xA6u, 0x03u},
{0xAEu, 0x04u},
{0xB0u, 0x01u},
{0xB1u, 0x01u},
{0xB2u, 0x02u},
{0xB4u, 0x04u},
{0xBEu, 0x10u},
{0xC0u, 0x10u},
{0xC1u, 0x05u},
{0xC5u, 0xD0u},
{0xC6u, 0x12u},
{0xC8u, 0x0Eu},
{0xC9u, 0xFFu},
{0xCAu, 0xFFu},
{0xCBu, 0xFFu},
{0xCDu, 0xA0u},
{0xCFu, 0x04u},
{0xD0u, 0x18u},
{0xD2u, 0x80u},
{0xD4u, 0x05u},
{0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDAu, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
{0xE0u, 0x40u},
{0xE2u, 0xC0u},
{0xE4u, 0x40u},
{0xE5u, 0x40u},
{0xE6u, 0xC0u},
{0xE8u, 0xC0u},
{0xEAu, 0xC0u},
{0xECu, 0xC0u},
{0xEEu, 0xC0u},
{0x00u, 0x10u},
{0x0Du, 0x80u},
{0x0Eu, 0x20u},
{0x10u, 0x20u},
{0x16u, 0x20u},
{0x17u, 0x80u},
{0x18u, 0x10u},
{0x19u, 0x40u},
{0x1Eu, 0x68u},
{0x20u, 0x44u},
{0x22u, 0x04u},
{0x23u, 0x02u},
{0x27u, 0x80u},
{0x2Au, 0x81u},
{0x30u, 0x20u},
{0x38u, 0x44u},
{0x3Cu, 0x02u},
{0x40u, 0x04u},
{0x47u, 0x80u},
{0x48u, 0x22u},
{0x49u, 0x01u},
{0x4Fu, 0x81u},
{0x50u, 0x02u},
{0x52u, 0x01u},
{0x55u, 0x80u},
{0x56u, 0x20u},
{0x57u, 0x40u},
{0x59u, 0x41u},
{0x5Au, 0x08u},
{0x5Eu, 0x48u},
{0x5Fu, 0x01u},
{0x67u, 0x40u},
{0x72u, 0x80u},
{0x74u, 0x01u},
{0x87u, 0x40u},
{0xC0u, 0x02u},
{0xC2u, 0xA0u},
{0xC4u, 0xA4u},
{0xCAu, 0x09u},
{0xCCu, 0x04u},
{0xCEu, 0x8Au},
{0xD0u, 0x14u},
{0xD2u, 0x18u},
{0xD6u, 0xDBu},
{0xD8u, 0x80u},
{0xAFu, 0x02u},
{0xE0u, 0x80u},
{0xEAu, 0x08u},
{0xECu, 0x03u},
{0x86u, 0x40u},
{0xE6u, 0x40u},
{0x0Bu, 0x08u},
{0x0Du, 0x80u},
{0x63u, 0x10u},
{0x6Eu, 0x80u},
{0x8Bu, 0x04u},
{0x93u, 0x10u},
{0xA2u, 0x40u},
{0xA5u, 0x80u},
{0xA9u, 0x80u},
{0xAFu, 0x10u},
{0xC2u, 0xC0u},
{0xD8u, 0x40u},
{0xDAu, 0x80u},
{0xEAu, 0x10u},
{0xECu, 0x80u},
{0x15u, 0x10u},
{0x16u, 0x40u},
{0x45u, 0x80u},
{0x49u, 0x40u},
{0x5Cu, 0x02u},
{0x6Bu, 0x02u},
{0x6Du, 0x40u},
{0xC4u, 0x05u},
{0xD0u, 0x04u},
{0xD2u, 0x08u},
{0xD6u, 0x01u},
{0xDAu, 0x03u},
{0x01u, 0x40u},
{0x07u, 0x02u},
{0x5Du, 0x10u},
{0x89u, 0x40u},
{0x91u, 0x10u},
{0x95u, 0x40u},
{0x9Du, 0x40u},
{0x9Fu, 0x02u},
{0xA9u, 0x80u},
{0xACu, 0x02u},
{0xAEu, 0x40u},
{0xC0u, 0x03u},
{0xD6u, 0x04u},
{0xE0u, 0x01u},
{0x10u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_UDB_BCTL0_DRV), 0x0100u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_UDB_BCTL0_DRV + 0x2u), 0x01u);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0xEE000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00030000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x03000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x00000003u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG4), 0xA0000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x02000000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG4), 0x80000000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x10000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990004u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG4), 0x00A00000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0x00030000u);
/* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x000E00F0u);
/* TCPWM_CNT2 Starting address: CYDEV_TCPWM_CNT2_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT2_TR_CTRL0), 0x000A0070u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INT_SEL */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INT_SEL), 0x00000002u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG, (uint8)((CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_WAIT_CFG) & 0xC3u) | 0x14u));
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, (uint8)(CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x16u));
}
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
/* IOPINS0_0 Starting address: CYDEV_GPIO_PRT0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT0_PC), 0x00D80000u);
/* IOPINS0_1 Starting address: CYDEV_GPIO_PRT1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT1_BASE), 0x00000014u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT1_PC), 0x00276D80u);
/* IOPINS0_2 Starting address: CYDEV_GPIO_PRT2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT2_BASE), 0x000000C0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_PC), 0x00580000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT2_INTR_CFG), 0x00008000u);
/* IOPINS0_3 Starting address: CYDEV_GPIO_PRT3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_GPIO_PRT3_BASE), 0x00000021u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_GPIO_PRT3_PC), 0x00036276u);
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Enable HALF_EN before trimming for the flash accelerator. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(24u);
/* Disable HALF_EN since it is not required at this IMO frequency. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) & 0xFFFBFFFFu));
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT02), 0x00000021u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT05), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT06), 0x00000010u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT07), 0x00000011u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT08), 0x00000030u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT09), 0x00000030u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT10), 0x00000030u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT11), 0x00000030u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x82000000u);
/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x800000FEu);
/* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B00), 0xC00000FEu);
/* CYDEV_CLK_DIVIDER_C00 Starting address: CYDEV_CLK_DIVIDER_C00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_C00), 0x80000017u);
/* CYDEV_CLK_DIVIDER_A01 Starting address: CYDEV_CLK_DIVIDER_A01 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A01), 0x80000017u);
/* CYDEV_CLK_DIVIDER_B01 Starting address: CYDEV_CLK_DIVIDER_B01 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B01), 0x800000CFu);
(void)CyIntSetVector(9u, &CySysWdtIsr);
CyIntEnable(9u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EE00u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x000000EEu);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00031000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC2), 0x00000020u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000D80u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000024u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
CY_CFG_SECTION
static void ClockSetup(void)
{
/* Enable HALF_EN before trimming for the flash accelerator. */
CY_SET_REG32((void CYXDATA *)(CYREG_CLK_SELECT), (CY_GET_REG32((void *)CYREG_CLK_SELECT) | 0x00040000u));
/* Setup and trim IMO based on desired frequency. */
CySysClkWriteImoFreq(48u);
/* CYDEV_CLK_ILO_CONFIG Starting address: CYDEV_CLK_ILO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_ILO_CONFIG), 0x80000006u);
/* CYDEV_CLK_SELECT00 Starting address: CYDEV_CLK_SELECT00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT02), 0x00000010u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT08), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT09), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT10), 0x00000020u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT11), 0x00000020u);
/* CYDEV_CLK_IMO_CONFIG Starting address: CYDEV_CLK_IMO_CONFIG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_IMO_CONFIG), 0x80000000u);
/* CYDEV_CLK_SELECT Starting address: CYDEV_CLK_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_SELECT), 0x00040000u);
/* CYDEV_CLK_DIVIDER_A00 Starting address: CYDEV_CLK_DIVIDER_A00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_A00), 0x80000138u);
/* CYDEV_CLK_DIVIDER_B00 Starting address: CYDEV_CLK_DIVIDER_B00 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CLK_DIVIDER_B00), 0x800004AFu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_WDT_CONFIG), 0x00000000u);
}
/*******************************************************************************
* Function Name: cyfitter_cfg
********************************************************************************
* Summary:
* This function is called by the start-up code for the selected device. It
* performs all of the necessary device configuration based on the design
* settings. This includes settings from the Design Wide Resources (DWR) such
* as Clocks and Pins as well as any component configuration that is necessary.
*
* Parameters:
* void
*
* Return:
* void
*
*******************************************************************************/
CY_CFG_SECTION
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
/* Enable the clock in the interrupt controller for the routed interrupts */
CY_SET_REG8((void *)CYREG_UDB_UDBIF_INT_CLK_CTL, 0x01u);
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3123u, /* Base address: 0x400F3100 Count: 35 */
0x400F3211u, /* Base address: 0x400F3200 Count: 17 */
0x400F3342u, /* Base address: 0x400F3300 Count: 66 */
0x400F4008u, /* Base address: 0x400F4000 Count: 8 */
0x400F4106u, /* Base address: 0x400F4100 Count: 6 */
0x400F420Bu, /* Base address: 0x400F4200 Count: 11 */
0x400F4312u, /* Base address: 0x400F4300 Count: 18 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x00u, 0x44u},
{0x03u, 0x08u},
{0x0Au, 0x15u},
{0x10u, 0x80u},
{0x12u, 0x29u},
{0x18u, 0x40u},
{0x1Au, 0x05u},
{0x1Bu, 0x28u},
{0x21u, 0x69u},
{0x22u, 0x80u},
{0x2Au, 0x12u},
{0x2Bu, 0x21u},
{0x30u, 0x80u},
{0x31u, 0x28u},
{0x32u, 0x01u},
{0x38u, 0x04u},
{0x39u, 0xA2u},
{0x40u, 0x04u},
{0x42u, 0x10u},
{0x4Au, 0x08u},
{0x52u, 0x10u},
{0x68u, 0x14u},
{0x6Bu, 0x01u},
{0x79u, 0x40u},
{0x87u, 0x08u},
{0x88u, 0x14u},
{0xC0u, 0x07u},
{0xC2u, 0x07u},
{0xC4u, 0x0Fu},
{0xCAu, 0x0Fu},
{0xCCu, 0x0Fu},
{0xCEu, 0x0Fu},
{0xD0u, 0x06u},
{0xD2u, 0x04u},
{0xDEu, 0x08u},
{0x40u, 0x23u},
{0x41u, 0x06u},
{0x47u, 0xB0u},
{0x48u, 0x20u},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
{0x4Fu, 0x40u},
{0x50u, 0x30u},
{0x5Au, 0x0Cu},
{0x5Du, 0x09u},
{0x5Fu, 0x01u},
{0x60u, 0xF0u},
{0x62u, 0x40u},
{0x63u, 0x02u},
{0x64u, 0x10u},
{0x65u, 0x12u},
{0x01u, 0x02u},
{0x03u, 0x20u},
{0x0Au, 0x59u},
{0x10u, 0x02u},
{0x12u, 0xA8u},
{0x18u, 0x24u},
{0x1Au, 0x79u},
{0x21u, 0x90u},
{0x22u, 0x29u},
{0x23u, 0x20u},
{0x29u, 0x02u},
{0x2Au, 0x10u},
{0x2Bu, 0x20u},
{0x31u, 0x80u},
{0x32u, 0x25u},
{0x38u, 0x22u},
{0x39u, 0x80u},
{0x3Eu, 0x30u},
{0x40u, 0x04u},
{0x42u, 0x10u},
{0x46u, 0x20u},
{0x47u, 0x20u},
{0x49u, 0x02u},
{0x4Au, 0x08u},
{0x4Eu, 0x04u},
{0x50u, 0x83u},
{0x56u, 0x01u},
{0x57u, 0x01u},
{0x69u, 0x40u},
{0x6Bu, 0x08u},
{0x79u, 0x40u},
{0x7Du, 0x40u},
{0x82u, 0x12u},
{0x83u, 0x08u},
{0x86u, 0x01u},
{0x89u, 0x80u},
{0x91u, 0x80u},
{0x94u, 0x04u},
{0x95u, 0x60u},
{0x96u, 0x52u},
{0x9Au, 0x10u},
{0x9Eu, 0x03u},
{0xA2u, 0x80u},
{0xA3u, 0x20u},
{0xA4u, 0x80u},
{0xA6u, 0x28u},
{0xA7u, 0x01u},
{0xADu, 0x01u},
{0xAEu, 0x01u},
{0xAFu, 0x01u},
{0xB1u, 0x28u},
{0xB4u, 0x40u},
{0xB6u, 0x40u},
{0xC0u, 0x0Cu},
{0xC2u, 0x0Fu},
{0xC4u, 0x0Fu},
{0xCAu, 0x07u},
{0xCCu, 0x0Fu},
{0xCEu, 0x0Du},
{0xD0u, 0x66u},
{0xD2u, 0x24u},
{0xDEu, 0x18u},
{0xE0u, 0x0Cu},
{0xE8u, 0x0Au},
{0xECu, 0x02u},
{0xEEu, 0xE0u},
{0x50u, 0x02u},
{0x5Fu, 0x02u},
{0x6Cu, 0x10u},
{0x87u, 0x02u},
{0xD4u, 0x80u},
{0xD6u, 0x80u},
{0xDAu, 0x80u},
{0xE6u, 0x40u},
{0x56u, 0x80u},
{0x9Au, 0x80u},
{0xB0u, 0x02u},
{0xB2u, 0x80u},
{0xB4u, 0x10u},
{0xD4u, 0x40u},
{0x52u, 0x40u},
{0x54u, 0x80u},
{0x58u, 0x14u},
{0x5Fu, 0x88u},
{0x66u, 0x02u},
{0x88u, 0x90u},
{0xD4u, 0x07u},
{0xD6u, 0x07u},
{0xD8u, 0x01u},
{0xE0u, 0x04u},
{0xE4u, 0x01u},
{0x5Au, 0x02u},
{0x5Cu, 0x04u},
{0x66u, 0x08u},
{0x80u, 0x04u},
{0x86u, 0x40u},
{0x8Au, 0x08u},
{0x92u, 0x02u},
{0x9Eu, 0x40u},
{0xACu, 0x04u},
{0xAEu, 0x01u},
{0xAFu, 0x80u},
{0xB6u, 0x02u},
{0xB7u, 0x08u},
{0xD6u, 0x03u},
{0xD8u, 0x01u},
{0xE0u, 0x04u},
{0xE8u, 0x02u},
{0xECu, 0x02u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
CYPACKED typedef struct {
void CYFAR *dest;
const void CYCODE *src;
uint16 size;
} CYPACKED_ATTR cfg_memcpy_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U1_BASE), 512u},
{(void CYFAR *)(CYDEV_UDB_P1_ROUTE_BASE), 256u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
/* UDB_0_1_0_CONFIG Address: CYDEV_UDB_P0_U0_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_1_0_CONFIG_VAL[] = {
0x00u, 0x04u, 0x00u, 0x08u, 0x7Eu, 0xFDu, 0x81u, 0x02u, 0x10u, 0x02u, 0x20u, 0x00u, 0x01u, 0x01u, 0x02u, 0x00u,
0x00u, 0xC3u, 0x00u, 0x3Cu, 0xCDu, 0x10u, 0x32u, 0x20u, 0x40u, 0x40u, 0x00u, 0x80u, 0x04u, 0x08u, 0x08u, 0x04u,
0x20u, 0x3Fu, 0x10u, 0xC0u, 0x80u, 0x02u, 0x00u, 0x00u, 0xF1u, 0x20u, 0x0Cu, 0x10u, 0x08u, 0x80u, 0x04u, 0x40u,
0x03u, 0x0Cu, 0x30u, 0x30u, 0xC0u, 0xC0u, 0x0Cu, 0x03u, 0x00u, 0x00u, 0xAAu, 0xAAu, 0x00u, 0x00u, 0x00u, 0x00u,
0x63u, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0xB0u, 0x00u, 0x08u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x40u,
0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, 0x99u, 0x09u, 0x00u, 0x01u,
0xF0u, 0x00u, 0x40u, 0x02u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
/* UDB_0_0_0_CONFIG Address: CYDEV_UDB_P1_U1_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_0_0_0_CONFIG_VAL[] = {
0x04u, 0x00u, 0x41u, 0x02u, 0x45u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x33u, 0x00u, 0x08u, 0x00u, 0x00u,
0x01u, 0xF1u, 0x02u, 0x04u, 0x4Du, 0x30u, 0xB2u, 0x4Cu, 0xBAu, 0x88u, 0x45u, 0x00u, 0x40u, 0x10u, 0x80u, 0x20u,
0x45u, 0x00u, 0x00u, 0x08u, 0x45u, 0x08u, 0x00u, 0x00u, 0x55u, 0x20u, 0x8Au, 0x10u, 0x22u, 0x00u, 0x00u, 0x00u,
0x03u, 0x0Fu, 0x3Cu, 0x0Fu, 0x08u, 0xC0u, 0xC0u, 0x30u, 0x08u, 0x00u, 0x82u, 0xA0u, 0x00u, 0x00u, 0x00u, 0x00u,
0x63u, 0x02u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x0Bu, 0xF0u, 0x26u, 0xFFu, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x40u,
0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x0Cu, 0x0Cu, 0x04u, 0x99u, 0x09u, 0x00u, 0x01u,
0xF0u, 0x00u, 0x40u, 0x02u, 0x10u, 0x12u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), BS_UDB_0_1_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYDEV_UDB_P1_U1_BASE), BS_UDB_0_0_0_CONFIG_VAL, 128u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
/* Copy device configuration data into registers */
for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
{
const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
void * CYDATA destPtr = mc->dest;
const void CYCODE * CYDATA srcPtr = mc->src;
uint16 CYDATA numBytes = mc->size;
CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_HSIOM_BASE), 0x30000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x33033333u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x3330EE00u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL4), 0x00000099u);
/* IOPINS0_0 Starting address: CYDEV_PRT0_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_DR), 0x00000081u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT0_PC), 0x00C00006u);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000001u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000006u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x000000DFu);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00D86DB6u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x000000E0u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00DB0D80u);
/* IOPINS0_4 Starting address: CYDEV_PRT4_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_DR), 0x00000002u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT4_PC), 0x00000031u);
/* UDB_PA_0 Starting address: CYDEV_UDB_PA0_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA0_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA0_CFG8), 0x40020000u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00010000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x311B0000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA3_CFG8), 0xD0000000u);
/* INT_SELECT Starting address: CYDEV_CPUSS_INTR_SELECT */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_CPUSS_INTR_SELECT), 0x00000001u);
/* INT_CONFIG Starting address: CYDEV_UDB_INT_CFG */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_INT_CFG), 0x00000002u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
void cyfitter_cfg(void)
{
/* Disable interrupts by default. Let user enable if/when they want. */
CyGlobalIntDisable;
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x400F3004u, /* Base address: 0x400F3000 Count: 4 */
0x400F3101u, /* Base address: 0x400F3100 Count: 1 */
0x400F3302u, /* Base address: 0x400F3300 Count: 2 */
0x400F4103u, /* Base address: 0x400F4100 Count: 3 */
0x400F4202u, /* Base address: 0x400F4200 Count: 2 */
0x400F4306u, /* Base address: 0x400F4300 Count: 6 */
0x400F6002u, /* Base address: 0x400F6000 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x3Au, 0xC0u},
{0x58u, 0x04u},
{0x5Cu, 0x09u},
{0x5Fu, 0x01u},
{0x18u, 0x01u},
{0xB4u, 0x01u},
{0xE6u, 0x80u},
{0x5Du, 0x80u},
{0x89u, 0x80u},
{0xD6u, 0x20u},
{0x61u, 0x02u},
{0xD8u, 0x02u},
{0x1Cu, 0x20u},
{0x88u, 0x10u},
{0xB5u, 0x02u},
{0xC6u, 0x04u},
{0xE6u, 0x01u},
{0xECu, 0x08u},
{0x02u, 0x01u},
{0x11u, 0x01u},
};
typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED cfg_memset_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYDEV_UDB_P0_U0_BASE), 1024u},
{(void CYFAR *)(CYDEV_UDB_DSI0_BASE), 1024u},
};
uint8 CYDATA i;
/* Zero out critical memory blocks before beginning configuration */
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
CYMEMZERO(ms->address, (uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* HSIOM Starting address: CYDEV_HSIOM_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL1), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL2), 0x30080000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_HSIOM_PORT_SEL3), 0x0000EEEEu);
/* IOPINS0_1 Starting address: CYDEV_PRT1_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_DR), 0x00000009u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT1_PC), 0x00000C06u);
/* IOPINS0_2 Starting address: CYDEV_PRT2_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_DR), 0x00000090u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT2_PC), 0x00C06000u);
/* IOPINS0_3 Starting address: CYDEV_PRT3_DR */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_DR), 0x00000003u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_PRT3_PC), 0x00000DA4u);
/* UDB_PA_1 Starting address: CYDEV_UDB_PA1_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA1_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA1_CFG8), 0x00030000u);
/* UDB_PA_2 Starting address: CYDEV_UDB_PA2_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA2_BASE), 0x00990000u);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_UDB_PA2_CFG8), 0x80000000u);
/* UDB_PA_3 Starting address: CYDEV_UDB_PA3_BASE */
CY_SET_XTND_REG32((void CYFAR *)(CYDEV_UDB_PA3_BASE), 0x00990000u);
/* TCPWM_CNT0 Starting address: CYDEV_TCPWM_CNT0_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT0_TR_CTRL0), 0x00000010u);
/* TCPWM_CNT1 Starting address: CYDEV_TCPWM_CNT1_TR_CTRL0 */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_TCPWM_CNT1_TR_CTRL0), 0x00000010u);
/* Enable digital routing */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x02u);
/* Enable UDB array */
CY_SET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL, CY_GET_XTND_REG8((void *)CYREG_UDB_UDBIF_BANK_CTL) | 0x06u);
}
/* Setup clocks based on selections from Clock DWR */
ClockSetup();
/* Perform basic analog initialization to defaults */
AnalogSetDefault();
}
