TCgReturnCode CgxDriverTcxoEnable(U32 aEnable)
{
// default implementation assumes direct manipulation of TCXO LDO via a dedicated GPIO pin.
// either CG_DRIVER_GPIO_TCXO_ENABLE or CG_DRIVER_GPIO_TCXO_DISABLE should be defined depending
// on the LDO control level (active high / active low)
#if defined(CG_DRIVER_GPIO_TCXO_ENABLE)
if (aEnable)
CgCpuGpioSet(CG_DRIVER_GPIO_TCXO_ENABLE);
else
CgCpuGpioReset(CG_DRIVER_GPIO_TCXO_ENABLE);
#elif defined(CG_DRIVER_GPIO_TCXO_DISABLE)
if (aEnable)
CgCpuGpioReset(CG_DRIVER_GPIO_TCXO_DISABLE);
else
CgCpuGpioSet(CG_DRIVER_GPIO_TCXO_DISABLE);
#endif
return ECgOk;
}
TCgReturnCode CgCpuIPMasterResetOn(void)
{
TCgReturnCode rc = ECgOk;
DBG_FUNC_NAME("CgCpuIPMasterResetOn");
DBGMSG("start");
// Set master reset pin to '0' (reset on - device inactive)
CgCpuGpioReset(CG_DRIVER_GPIO_GPS_MRSTN);
return rc;
}
TCgReturnCode CgxDriverExecuteSpecific(
void *pDriver,
TCgxDriverState *pState,
U32 aRequest,
TCgDriverControl *pControl,
TCgDriverStatus *pResults)
{
DBG_FUNC_NAME("CgxDriverExecuteSpecific")
DBGMSG1("aRequest =%x",aRequest);
switch (aRequest) {
case CGX_IOCTL_INIT:
DBGMSG("CGX_IOCTL_INIT");
// This is 1st time initialization, meaning the software is restarted, not resumed, so set the state accordingly.
DBGMSG1("pState = 0x%x", pState);
pState->flags.resume = FALSE;
DBGMSG("after pState->flags.resume = FALSE;");
pResults->rc = CgxDriverInit(pDriver);
break;
case CGX_IOCTL_STOP:
pResults->rc = CgxDriverDestroy(pDriver);
break;
case CGX_IOCTL_READ_REG:
pState->transfer.cancel.request = FALSE;
// Verify register is of the CGX_sat_ram group
pResults->readReg.value = 0;
DBGMSG1("readReg.offset %x ",pControl->readReg.offset);
if ( pControl->readReg.offset >= CGCORE_REG_OFFSET_SAT_RAM && pControl->readReg.offset <= CGCORE_REG_OFFSET_SAT_RAM_LAST )
{
// Write read command to the APB (9 bits of the register offset, with 0x80000000, as the read command)
pResults->rc = CGCORE_WRITE_REG( CGCORE_REG_OFFSET_APB_COMMAND, (0x000001FF & pControl->readReg.offset) | 0x80000000);
// Wait 4 system clocks
CgCpuDelay(100); // TODO : what is the actual period of this wait. Is it 4 system clocks?
// Read data from the APB
if (OK(pResults->rc))
pResults->rc = CGCORE_READ_REG( CGCORE_REG_OFFSET_APB_DATA, &pResults->readReg.value);
}
else
{
// It is not part of the CGX_sat_ram. Read register normaly, via the APB
pResults->rc = CGCORE_READ_REG( pControl->readReg.offset, &pResults->readReg.value);
}
break;
case CGX_IOCTL_WRITE_REG:
pState->transfer.cancel.request = FALSE;
// Write to CGsnap register
pResults->rc = CGCORE_WRITE_REG( pControl->writeReg.offset, pControl->writeReg.value);
// DBGMSG2("CGX_IOCTL_WRITE_REG *0x%08X = 0x%08X", CGCORE_BASE_ADDR_VA + pControl->writeReg.offset, pControl->writeReg.value);
break;
case CGX_IOCTL_PREPARE_RECEIVE:
DBGMSG("CGX_IOCTL_PREPARE_RECEIVE");
// Prepare driver for massive data receive (snap)
pState->transfer.cancel.request = FALSE;
pResults->rc = CgxDriverPrepareRecieve(pState, pControl->read.buf, pControl->read.bufPhys,
pState->buffer.length, pControl->read.alignedLength, pControl->read.blockLength,
pControl->read.byteOrder);
break;
case CGX_IOCTL_STATUS:
pResults->rc = pState->constructionRc;
break;
case CGX_IOCTL_RESUME_CLEAR:
DBGMSG("CGX_IOCTL_RESUME_CLEAR!");
pState->flags.resume = FALSE;
pState->transfer.cancel.request = FALSE;
break;
case CGX_IOCTL_RESET:
DBGMSG1("CGX_IOCTL_RESET level %d", pControl->reset.resetLevel);
pState->transfer.cancel.request = FALSE;
switch( pControl->reset.resetLevel )
{
case 0: // Full reset
#if 0
if (OK(pResults->rc)) pResults->rc = CgCpuIPMasterResetOn();
if (OK(pResults->rc)) pResults->rc = CgCpuDelay(CGCORE_RESET_DELAY);
if (OK(pResults->rc)) pResults->rc = CgCpuIPMasterResetClear();
#endif
if (OK(pResults->rc)) pResults->rc = CGCORE_WRITE_REG( CGCORE_REG_OFFSET_CORE_RESETS, CGCORE_CORE_RESETS_ENABLE);
break;
case 1: // Semi reset
if (OK(pResults->rc)) pResults->rc = CGCoreReset(CGCORE_ENABLE_CORE);
#ifdef CGCORE_ACCESS_VIA_SPI
init_spi_block_var();
#endif
break;
case 2: // CPU reset
break;
default : // Semi reset, also.
if (OK(pResults->rc)) pResults->rc = CGCoreReset(CGCORE_ENABLE_CORE);
break;
}
pResults->rc = CgCpuDmaStop(CG_DRIVER_DMA_CHANNEL_READ);
break;
case CGX_IOCTL_COUNTER_RESET:
DBGMSG("CGX_IOCTL_COUNTER_RESET!");
pResults->rc = CgCpuDmaStop(CG_DRIVER_DMA_CHANNEL_READ);
if (OK(pResults->rc)) pResults->rc = CGCoreReset(CGCORE_ENABLE_TCXO);
break;
case CGX_IOCTL_POWER_DOWN:
DBGMSG("CGX_IOCTL_POWER_DOWN!");
flag_power_up = 0;
pResults->rc = CgxDriverPowerDown();
if (OK(pResults->rc)) pResults->rc = CgxDriverRFPowerDown();
break;
case CGX_IOCTL_POWER_UP:
flag_power_up = 1;
pState->transfer.cancel.request = FALSE;
pResults->rc = CgxDriverPowerUp();
if (OK(pResults->rc)) pResults->rc = CgxDriverRFPowerUp();
break;
case CGX_IOCTL_POWER_OFF :
pResults->rc = CgxDriverPowerOff();
break;
case CGX_IOCTL_POWER_ON :
pResults->rc = CgxDriverPowerOn();
break;
case CGX_IOCTL_GPIO_SET:
//DBGMSG2("CGX_IOCTL_GPIO_SET 0x%08X = %d", pControl->GPIO.code, pControl->GPIO.out);
if (pControl->GPIO.out)
pResults->rc = CgCpuGpioSet(pControl->GPIO.code);
else
pResults->rc = CgCpuGpioReset(pControl->GPIO.code);
//rc = CgxDriverDebugGpio((int)pControl->GPIO.code, (int)pControl->GPIO.out);
break;
case CGX_IOCTL_GPIO_GET:
//DBGMSG1("CGX_IOCTL_GPIO_GET 0x%08X", pControl->GPIO.code);
//pResults->GPIO.in = 0x5a5a;
//DBGMSG2("CGX_IOCTL_GPIO_GET before 0x%08X=0x%08X", pControl->GPIO.code, pResults->GPIO.in)
pResults->rc = CgCpuGpioGet(pControl->GPIO.code, (int *)&(pResults->GPIO.val));
pResults->GPIO.code = pControl->GPIO.code;
//DBGMSG2("CGX_IOCTL_GPIO_GET after 0x%08X=0x%08X", pControl->GPIO.code, pResults->GPIO.in)
//rc = CgxDriverDebugGpioRead((int)pResults->GPIO.code, (int*)&pResults->GPIO.in);
break;
case CGX_IOCTL_GET_VERSION:
memcpy(pResults->version.buildVersion, gCgDriverVersion.buildVersion, sizeof(pResults->version.buildVersion));
memcpy(pResults->version.buildMode, gCgDriverVersion.buildMode, sizeof(pResults->version.buildNumber));
memcpy(pResults->version.buildNumber, gCgDriverVersion.buildNumber, sizeof(pResults->version.buildNumber));
memcpy(pResults->version.buildTime, gCgDriverVersion.buildTime, sizeof(pResults->version.buildTime));
memcpy(pResults->version.buildDate, gCgDriverVersion.buildDate, sizeof(pResults->version.buildDate));
break;
case CGX_IOCTL_CANCEL_RECEIVE:
DBGMSG1("Request cancel on byte %d", pControl->cancel.onByteCount);
// set up receive abort flag.
// the flag is cleared be prepare receive command
if (pControl->cancel.onByteCount > (U32)CgxDriverSnapLengthExtraBytes) {
pState->transfer.cancel.onByte = pControl->cancel.onByteCount - CgxDriverSnapLengthExtraBytes;
CG_MATH_ALIGNMENT((pState->transfer.cancel.onByte), NUMBER_1K);
DBGMSG1("cancel on Byte: 0x%08X", pState->transfer.cancel.onByte);
}
else {
pState->transfer.cancel.onByte = 0; // Cancel snap req immediately
}
pState->transfer.cancel.request = TRUE;
DBGMSG1("cancel on Byte: 0x%08X", ((pState->transfer.cancel.onByte / 16) & 0x00FFFFF) | 0x0F000000);
CGCORE_WRITE_REG( 0x30, ((pState->transfer.cancel.onByte / 16) & 0x00FFFFF) | 0x0F000000);
CGCORE_WRITE_REG( 0x34, 0);
// check if cancel point passed
pResults->rc = CgxDriverIsReadCanceled(pState);
if ((pControl->cancel.onByteCount == 0) || // Cancel snap req immediately
(!OK(pResults->rc) && pState->flags.wait)) {// release a waiting thread, if any
CGCoreReset(CGCORE_ENABLE_CORE);
CgCpuDmaStop(CG_DRIVER_DMA_CHANNEL_READ);
CgxDriverDataReadyInterruptHandler(pDriver, pState);
}
break;
case CGX_IOCTL_ALLOC_BUFF:
DBGMSG1("CGX_IOCTL_ALLOC_BUFF, pControl->alloc.length=%d", pControl->alloc.length);
// pControl->alloc.length = 1 *1024 * 1024; // 1M
pResults->rc = CgxDriverAllocInternalBuff(pDriver, pControl->alloc.length,
(void**)&(pResults->buffer.bufferPhysAddr), pControl->alloc.processId);
DBGMSG1("alloc p =0x%08X", pState->buffer.virtAddr);
if (OK(pResults->rc)) {
pResults->buffer.size = pControl->alloc.length;
pResults->buffer.bufferAppVirtAddr = pState->buffer.virtAddr;
}
break;
case CGX_IOCTL_FREE_BUFF:
DBGMSG("CGX_IOCTL_FREE_BUFF");
pResults->rc = CgxDriverFreeInternalBuff(pDriver, pControl->alloc.processId);
break;
case CGX_IOCTL_READ_MEM:
DBGMSG("CGX_IOCTL_READ_MEM");
pState->transfer.cancel.request = FALSE;
DBGMSG1("read from 0x%08X", pControl->readReg.offset);
pResults->rc = CgxCpuReadMemory(pControl->readReg.offset, 0, &pResults->readReg.value);
break;
case CGX_IOCTL_CPU_REVISION:
pResults->rc = CgCpuRevision(pResults->cpuRevision.revisionCode); // TODO - fix CgCpuRevision so it reads from the right address
break;
case CGX_IOCTL_TCXO_ENABLE:
DBGMSG("CGX_IOCTL_TCXO_ENABLE");
pResults->rc = CgxDriverTcxoControl(pControl->tcxoControl.enable);
break;
case CGX_IOCTL_RF_WRITE_CONTROL:
DBGMSG("CGX_IOCTL_RF_WRITE_CONTROL");
pResults->rc = CgCpuRFControlWriteByte(pControl->writeReg.value);
break;
default:
return ECgGeneralFailure;
}
return ECgOk;
}