void Chip_SetupIrcClocking(void)
{
/* Disconnect the Main PLL if it is connected already */
if (Chip_Clock_IsMainPLLConnected()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
Chip_Clock_SetCPUClockDiv(0);
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_IRC);
/* FCCO = ((44+1) * 2 * 4MHz) / (0+1) = 360MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 44, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
Chip_Clock_SetCPUClockDiv(2);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
void Chip_SetupXtalClocking(void)
{
/* Disconnect the Main PLL if it is connected already */
if (Chip_Clock_IsMainPLLConnected()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Set PLL0 Source to Crystal Oscillator */
Chip_Clock_SetCPUClockDiv(0);
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = ((15+1) * 2 * 12MHz) / (0+1) = 384MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 15, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
/* 384MHz / (3+1) = 96MHz */
Chip_Clock_SetCPUClockDiv(3);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
void setupClock(void) {
/* Disconnect the Main PLL if it is connected already */
if (Chip_Clock_IsMainPLLConnected()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
}
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Set PLL0 Source to Crystal Oscillator */
Chip_Clock_SetCPUClockDiv(0);
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = ((19+1) * 2 * 12MHz) / (0+1) = 480MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 19, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
/* 480MHz / (3+1) = 120MHz */
Chip_Clock_SetCPUClockDiv(3);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_CONNECT);
Chip_SYSCTL_SetFLASHAccess(FLASHTIM_120MHZ_CPU);
}
/* Clock and PLL initialization based on the external oscillator */
void Chip_SetupXtalClocking(void)
{
/* Enable the crystal */
if (!Chip_Clock_IsCrystalEnabled())
Chip_Clock_EnableCrystal();
while(!Chip_Clock_IsCrystalEnabled()) {}
/* Clock the CPU from SYSCLK, in case if it is clocked by PLL0 */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_SYSCLK);
/* Disable the PLL if it is enabled */
if (Chip_Clock_IsMainPLLEnabled()) {
Chip_Clock_DisablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
}
/* It is safe to switch the PLL Source to Crystal Oscillator */
Chip_Clock_SetMainPLLSource(SYSCTL_PLLCLKSRC_MAINOSC);
/* FCCO = 12MHz * (9+1) * 2 * (0+1) = 240MHz */
/* Fout = FCCO / ((0+1) * 2) = 120MHz */
Chip_Clock_SetupPLL(SYSCTL_MAIN_PLL, 9, 0);
Chip_Clock_EnablePLL(SYSCTL_MAIN_PLL, SYSCTL_PLL_ENABLE);
Chip_Clock_SetCPUClockDiv(1);
while (!Chip_Clock_IsMainPLLLocked()) {} /* Wait for the PLL to Lock */
Chip_Clock_SetCPUClockSource(SYSCTL_CCLKSRC_MAINPLL);
/* Peripheral clocking will be derived from PLL0 with a divider of 2 (60MHz) */
Chip_Clock_SetPCLKDiv(2);
}
void HAL_USBDeInit(uint8_t corenum, uint8_t mode)
{
NVIC_DisableIRQ(USB_IRQn); /* disable USB interrupt */
LPC_SYSCTL->PCONP &= (~(1UL << 31)); /* disable USB Per. */
Chip_IOCON_PinMux(LPC_IOCON, 0, 29, IOCON_MODE_INACT, IOCON_FUNC0); /* P0.29 D+, P0.30 D- reset to GPIO function */
Chip_IOCON_PinMux(LPC_IOCON, 0, 30, IOCON_MODE_INACT, IOCON_FUNC0);
/* Disable PLL1 to save power */
Chip_Clock_DisablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
}
void HAL_USBDeInit(uint8_t corenum, uint8_t mode)
{
HAL_DisableUSBInterrupt(corenum);
if (mode == USB_MODE_Device) {
#if defined(USB_CAN_BE_HOST)
USB_REG(corenum)->USBSTS_H = 0xFFFFFFFF; /* clear all current interrupts */
USB_REG(corenum)->PORTSC1_H &= ~(1 << 12); /* clear port power */
USB_REG(corenum)->USBMODE_H = (1 << 0); /* set USB mode reserve */
#endif
}
else if (mode == USB_MODE_Host) {
#if defined(USB_CAN_BE_DEVICE)
/* Clear all pending interrupts */
USB_REG(corenum)->USBSTS_D = 0xFFFFFFFF;
USB_REG(corenum)->ENDPTNAK = 0xFFFFFFFF;
USB_REG(corenum)->ENDPTNAKEN = 0;
USB_REG(corenum)->ENDPTSETUPSTAT = USB_REG(corenum)->ENDPTSETUPSTAT;
USB_REG(corenum)->ENDPTCOMPLETE = USB_REG(corenum)->ENDPTCOMPLETE;
while (USB_REG(corenum)->ENDPTPRIME) ; /* Wait until all bits are 0 */
USB_REG(corenum)->ENDPTFLUSH = 0xFFFFFFFF;
while (USB_REG(corenum)->ENDPTFLUSH) ; /* Wait until all bits are 0 */
#endif
}
/* Disable USB PHY if both USB cores are disabled */
if (coreEnabled[1 - corenum]) {
/* Turn off the phy (prior to PLL disabled) */
Chip_CREG_EnableUSB0Phy(false);
}
/* Power down USB clocking */
if (corenum == 0) {
Chip_Clock_Disable(CLK_MX_USB0);
Chip_Clock_DisableBaseClock(CLK_BASE_USB0);
}
else {
Chip_Clock_Disable(CLK_MX_USB1);
Chip_Clock_DisableBaseClock(CLK_BASE_USB1);
}
/* Disable USB PLL if both USB cores are disabled */
if (coreEnabled[1 - corenum]) {
/* Disable USB PLL */
Chip_Clock_DisablePLL(CGU_USB_PLL);
}
coreEnabled[corenum] = false;
}
void HAL_USBDeInit(uint8_t corenum, uint8_t mode)
{
NVIC_DisableIRQ(USB_IRQn); /* disable USB interrupt */
LPC_SYSCTL->PCONP &= (~(1UL << 31)); /* disable USB Per. */
#if defined(__LPC175X_6X__)
//LPC_PINCON->PINSEL1 &= ~((3 << 26) | (3 << 28)); /* P0.29 D+, P0.30 D- reset to GPIO function */
Chip_IOCON_PinMux(LPC_IOCON, 0, 29, MD_PLN, FUNC0);
Chip_IOCON_PinMux(LPC_IOCON, 0, 30, MD_PLN, FUNC0);
#elif defined(__LPC177X_8X__) || defined(__LPC407X_8X__)
//LPC_IOCON->P0_29 &= ~0x07; /* P0.29 D1+, P0.30 D1- reset to GPIO function */
//LPC_IOCON->P0_30 &= ~0x07;
Chip_IOCON_PinMux(LPC_IOCON, 0, 29, MD_PLN, FUNC0);
Chip_IOCON_PinMux(LPC_IOCON, 0, 30, MD_PLN, FUNC0);
#endif
/* Disable PLL1 to save power */
Chip_Clock_DisablePLL(SYSCTL_USB_PLL, SYSCTL_PLL_ENABLE);
}
/**
* Set IRC as source clock fo all the output clocks & power down
* before going to 'Deep Sleep'/'Power Down'/'Deep Power Down' modes
*/
static void PMC_Pre_SleepPowerDown(void)
{
int i;
#ifndef BOARD_NGX_XPLORER_18304330
/* SDRAM in self refresh mode only for Keil & Hitex boards */
LPC_EMC->DYNAMICCONTROL |= (1 << 2);
while (!(LPC_EMC->STATUS & (1 << 2))) {}
#endif
/* Shutdown perpheral clocks with wake up enabled */
Chip_Clock_StartPowerDown();
/* Get state of individual base clocks & store them for restoring.
* Sets up the IRC as base clock source
*/
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
/* Get the Base clock settings */
Chip_Clock_GetBaseClockOpts(InitClkStates[i].clk, &InitClkStates[i].clkin,
&InitClkStates[i].autoblock_enab, &InitClkStates[i].powerdn);
/* Set IRC as clock input for all the base clocks */
Chip_Clock_SetBaseClock(InitClkStates[i].clk, CLKIN_IRC, InitClkStates[i].autoblock_enab,
InitClkStates[i].powerdn);
}
/* Set IRC as clock source for SPIFI */
Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IRC, true, false);
/* Set IRC as source clock for Core */
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_IRC, true, false);
#ifdef BOARD_KEIL_MCB_18574357
/* Set Flash acceleration */
Chip_CREG_SetFlashAcceleration(CRYSTAL_MAIN_FREQ_IN);
#endif
/* Power down the main PLL */
Chip_Clock_DisableMainPLL();
Chip_Clock_DisablePLL(CGU_USB_PLL);
Chip_Clock_DisableCrystal();
}
