static void initHardware(void)
{
SystemCoreClockUpdate();
SysTick_Config(SystemCoreClock/1000);
Board_Init();
Board_LED_Set(0, false);
/* Timer */
Chip_TIMER_Init(LPC_TIMER1);
Chip_TIMER_PrescaleSet(LPC_TIMER1,
#ifdef lpc1769
Chip_Clock_GetPeripheralClockRate(SYSCTL_PCLK_TIMER1) / 1000000 - 1
#else
Chip_Clock_GetRate(CLK_MX_TIMER1) / 1000000 - 1
#endif
);
/* Match 0 (period) */
Chip_TIMER_MatchEnableInt(LPC_TIMER1, 0);
Chip_TIMER_ResetOnMatchEnable(LPC_TIMER1, 0);
Chip_TIMER_StopOnMatchDisable(LPC_TIMER1, 0);
Chip_TIMER_SetMatch(LPC_TIMER1, 0, 1000);
/* Match 1 (duty) */
Chip_TIMER_MatchEnableInt(LPC_TIMER1, 1);
Chip_TIMER_ResetOnMatchDisable(LPC_TIMER1, 1);
Chip_TIMER_StopOnMatchDisable(LPC_TIMER1, 1);
Chip_TIMER_SetMatch(LPC_TIMER1, 1, 100);
Chip_TIMER_Reset(LPC_TIMER1);
Chip_TIMER_Enable(LPC_TIMER1);
NVIC_EnableIRQ(TIMER1_IRQn);
}
/* Get divider value */
STATIC Status getClkDiv(LPC_I2S_T *pI2S, I2S_AUDIO_FORMAT_T *format, uint16_t *pxDiv, uint16_t *pyDiv, uint32_t *pN)
{
uint32_t pClk;
uint32_t x, y;
uint64_t divider;
uint16_t dif;
uint16_t xDiv = 0, yDiv = 0;
uint32_t N;
uint16_t err, ErrorOptimal = 0xFFFF;
pClk = Chip_Clock_GetRate(CLK_APB1_I2S);
/* divider is a fixed point number with 16 fractional bits */
divider = (((uint64_t) (format->SampleRate) * 2 * (format->WordWidth) * 2) << 16) / pClk;
/* find N that make x/y <= 1 -> divider <= 2^16 */
for (N = 64; N > 0; N--) {
if ((divider * N) < (1 << 16)) {
break;
}
}
if (N == 0) {
return ERROR;
}
divider *= N;
for (y = 255; y > 0; y--) {
x = y * divider;
if (x & (0xFF000000)) {
continue;
}
dif = x & 0xFFFF;
if (dif > 0x8000) {
err = 0x10000 - dif;
}
else {
err = dif;
}
if (err == 0) {
yDiv = y;
break;
}
else if (err < ErrorOptimal) {
ErrorOptimal = err;
yDiv = y;
}
}
xDiv = ((uint64_t) yDiv * (format->SampleRate) * 2 * (format->WordWidth) * N * 2) / pClk;
if (xDiv >= 256) {
xDiv = 0xFF;
}
if (xDiv == 0) {
xDiv = 1;
}
*pxDiv = xDiv;
*pyDiv = yDiv;
*pN = N;
return SUCCESS;
}
/* Determines best dividers to get a target baud rate */
Status Chip_UART_SetBaud(LPC_USART_Type *UARTx, uint32_t baudrate)
{
uint32_t uClk;
/* Get UART clock rate */
uClk = Chip_Clock_GetRate(Chip_UART_DetermineClk(UARTx));
return IP_UART_SetBaud(UARTx, baudrate, uClk);
}
/* Setup EEPROM clock */
STATIC void setClkDiv(LPC_EEPROM_T *pEEPROM)
{
uint32_t clk;
/* Setup EEPROM timing to 375KHz based on PCLK rate */
clk = Chip_Clock_GetRate(CLK_MX_EEPROM);
/* Set EEPROM clock divide value*/
pEEPROM->CLKDIV = clk / EEPROM_CLOCK_DIV - 1;
}
/* Initializes the EEPROM peripheral with specified parameter */
void Chip_EEPROM_Init(LPC_EEPROM_T *pEEPROM)
{
uint32_t cclk;
/* Setup EEPROM timing to 1500KHz based on CCLK rate */
cclk = Chip_Clock_GetRate(CLK_MX_EEPROM);
IP_EEPROM_Init(pEEPROM, cclk / EEPROM_CLOCK_DIV - 1);
/* Setup EEPROM wait states*/
IP_EEPROM_SetReadWaitState(pEEPROM, EEPROM_READ_WAIT_STATE_VAL);
IP_EEPROM_SetWaitState(pEEPROM, EEPROM_WAIT_STATE_VAL);
}
/* Initialize stopwatch */
void StopWatch_Init(void)
{
/* Use timer 1. Set prescaler to divide by 8 */
const uint32_t prescaleDivisor = 8;
Chip_TIMER_Init(LPC_TIMER0);
Chip_TIMER_PrescaleSet(LPC_TIMER0, prescaleDivisor - 1);
Chip_TIMER_Enable(LPC_TIMER0);
/* Pre-compute tick rate. */
ticksPerSecond = Chip_Clock_GetRate(CLK_MX_TIMER0) / prescaleDivisor;
ticksPerMs = ticksPerSecond / 1000;
ticksPerUs = ticksPerSecond / 1000000;
}
/**
* @brief Main entry point
* @return Nothing
*/
int main(void)
{
SPIFIobj *obj = &spifi_obj;
uint32_t spifi_clk_mhz;
SPIFIopers opers;
int ret;
spifi_rom_init(spifi);
/* Initialize the board & LEDs for error indication */
Board_Init();
/* Since this code runs from SPIFI no special initialization required here */
prepare_write_data(data_buffer, sizeof(data_buffer));
spifi_clk_mhz = Chip_Clock_GetRate(CLK_MX_SPIFI) / 1000000;
/* Typical time tCS is 20 ns min, we give 200 ns to be on safer side */
if (spifi_init(obj, spifi_clk_mhz / 5, S_RCVCLK | S_FULLCLK, spifi_clk_mhz)) {
DEBUGSTR("Error initializing SPIFI interface!\r\n");
Board_LED_Set(1, 1);
goto end_prog;
}
/* Prepare the operations structure */
memset(&opers, 0, sizeof(SPIFIopers));
opers.dest = (char *) SPIFI_WRITE_SECTOR_OFFSET;
opers.length = sizeof(data_buffer);
/* opers.options = S_VERIFY_PROG; */
/* NOTE: All interrupts must be disabled before calling program as
* any triggered interrupts might attempt to run a code from SPIFI area
*/
ret = spifi_program(obj, (char *) data_buffer, &opers);
if (ret) {
DEBUGOUT("Error 0x%x: Programming of data buffer to SPIFI Failed!\r\n", ret);
Board_LED_Set(1, 1);
goto end_prog;
}
DEBUGSTR("SPIFI Programming successful!\r\n");
if (verify_spifi_data((uint8_t *) SPIFI_WRITE_SECTOR_ADDRESS, sizeof(data_buffer))) {
DEBUGSTR("Error verifying the SPIFI data\r\n");
Board_LED_Set(1, 1);
goto end_prog;
}
Board_LED_Set(0, 1);
DEBUGSTR("SPIFI Data verified!\r\n");
end_prog:
while(1) {__WFI();}
}
/* Set timer interval value */
void Chip_RIT_SetTimerInterval_(LPC_RITIMER_T *pRITimer, uint32_t time_interval)
{
uint32_t cmp_value;
/* Determine aapproximate compare value based on clock rate and passed interval */
cmp_value = ((Chip_Clock_GetRate(CLK_MX_RITIMER) / 1000) * time_interval )/ 1000;
/* Set timer compare value */
Chip_RIT_SetCOMPVAL(pRITimer, cmp_value);
/* Set timer enable clear bit to clear timer to 0 whenever
counter value equals the contents of RICOMPVAL */
Chip_RIT_EnableCTRL(pRITimer, RIT_CTRL_ENCLR);
}
/**
* @brief Main entry point
* @return Nothing
*/
int main(void)
{
uint32_t SCT_FRQ;
Board_Init();
/* Initialize SCT */
Chip_SCT_Init(LPC_SCT);
LPC_SCU->SFSCLK[3] = SCU_MODE_MODE_REPEATER | SCU_MODE_FUNC1; /* function 1; CGU clk out, pull up */
/* Attach IRC clock to divider B with a divider of 16 */
Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IRC, 16);
/* Route divider B output to Clock output base clock and enable base out clock */
Chip_Clock_SetBaseClock(CLK_BASE_OUT, CLKIN_IDIVB, true, false);
/* Configure SCT pins */
SCT_PinsConfigure();
SCT_FRQ = Chip_Clock_GetRate(CLK_MX_SCT);
DEBUGOUT("SCT_FRQ: %d\r\n", SCT_FRQ);
Chip_SCT_ControlSetClr(LPC_SCT, SCT_CTRL_CLRCTR_L | SCT_CTRL_HALT_L | SCT_CTRL_PRE_L(256 - 1)
| SCT_CTRL_HALT_H | SCT_CTRL_CLRCTR_H | SCT_CTRL_PRE_H(256 - 1),
ENABLE);
/* Now use the FSM code to configure the state machine */
sct_fsm_init();
/* initialize random seed: */
srand(0x5EED);
/* 12000000 / 256 / 16 = 2929 Hz
* 65535 / 2929 =~ 22 */
/* generate a random delay from 1 to 22 seconds */
delay = (rand() % 22 + 1) * 2929;
NVIC_ClearPendingIRQ(SCT_IRQn);
NVIC_EnableIRQ(SCT_IRQn);
/* Start the SCT */
Chip_SCT_ControlSetClr(LPC_SCT, SCT_CTRL_STOP_L | SCT_CTRL_HALT_L | SCT_CTRL_STOP_H | SCT_CTRL_HALT_H, DISABLE);
while (1) {
__WFI();
}
}
void vConfigureTimerForRunTimeStats( void )
{
uint32_t timerFreq;
/* Enable timer 1 clock and reset it */
Chip_TIMER_Init(LPC_TIMER1);
Chip_RGU_TriggerReset(RGU_TIMER1_RST);
while (Chip_RGU_InReset(RGU_TIMER1_RST)) {}
/* Get timer 1 peripheral clock rate */
timerFreq = Chip_Clock_GetRate(CLK_MX_TIMER1);
/* Timer setup for match and interrupt at TICKRATE_HZ */
Chip_TIMER_Reset(LPC_TIMER1);
Chip_TIMER_SetMatch(LPC_TIMER1, 1, (timerFreq / TICKRATE_HZ));
Chip_TIMER_ResetOnMatchEnable(LPC_TIMER1, 1);
Chip_TIMER_Enable(LPC_TIMER1);
}
/* Set the clock frequency for SSP interface */
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate)
{
uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
ssp_clk = Chip_Clock_GetRate(Chip_SSP_GetClockIndex(pSSP));
cr0_div = 0;
cmp_clk = 0xFFFFFFFF;
prescale = 2;
while (cmp_clk > bitRate) {
cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
if (cmp_clk > bitRate) {
cr0_div++;
if (cr0_div > 0xFF) {
cr0_div = 0;
prescale += 2;
}
}
}
Chip_SSP_SetClockRate(pSSP, cr0_div, prescale);
}
/** \brief Set timer interval value in microseconds */
void Chip_RIT_SetTimerIntervaluS(LPC_RITIMER_T *pRITimer, uint32_t time_interval_us)
{
/** \details
* This method is a copy of Chip_RIT_SetTimerInterval provided by vendor, in which
* I made a minimal change to obtain a function that uses as parameter a number
* in microseconds to interrupt with the RIT timer
*
* \param LPC_RITIMER_T *pRITimer: pointer to the RIT timer.
* \param uint32_t time_interval_us: time interval in microseconds.
*
* \return nothing
* */
uint32_t cmp_value;
/* Determine approximate compare value based on clock rate and passed interval */
cmp_value = (Chip_Clock_GetRate(CLK_MX_RITIMER)/1000000) * time_interval_us;
/* Set timer compare value */
Chip_RIT_SetCOMPVAL(pRITimer, cmp_value);
/* Set timer enable clear bit to clear timer to 0 whenever
counter value equals the contents of RICOMPVAL */
Chip_RIT_EnableCTRL(pRITimer, RIT_CTRL_ENCLR);
}
/* Get divider value */
STATIC uint8_t getClkDiv(LPC_ADC_T *pADC, bool burstMode, uint32_t adcRate, uint8_t clks)
{
uint32_t adcBlockFreq;
uint32_t fullAdcRate;
uint8_t div;
/* The APB clock (PCLK_ADC0) is divided by (CLKDIV+1) to produce the clock for
A/D converter, which should be less than or equal to 4.5MHz.
A fully conversion requires (bits_accuracy+1) of these clocks.
ADC Clock = PCLK_ADC0 / (CLKDIV + 1);
ADC rate = ADC clock / (the number of clocks required for each conversion);
*/
adcBlockFreq = Chip_Clock_GetRate(Chip_ADC_GetClockIndex(pADC));
if (burstMode) {
fullAdcRate = adcRate * clks;
}
else {
fullAdcRate = adcRate * getFullConvClk();
}
/* Get the round value by fomular: (2*A + B)/(2*B) */
div = ((adcBlockFreq * 2 + fullAdcRate) / (fullAdcRate * 2)) - 1;
return div;
}
/**
* @brief Main entry point
* @return Nothing
*/
int main(void)
{
bool bool_status;
uint32_t mainpll_freq, clkin_frq, dive_value, baseclk_frq, perclk_frq;
CHIP_CGU_CLKIN_T clk_in, base_input;
bool autoblocken;
bool powerdn;
int i;
volatile int k = 1;
SystemCoreClockUpdate();
Board_Init();
/* Print the Demo Information */
DEBUGOUT(menu);
/* Main PLL should be locked, Check if Main PLL is locked */
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("PLL functions \r\n");
DEBUGOUT("Main PLL : ");
bool_status = Chip_Clock_MainPLLLocked();
if (bool_status == true) {
DEBUGOUT("Locked\r\n");
}
else {
DEBUGOUT("Not Locked\r\n");
return 1;
}
/* Read Main PLL frequency in Hz */
mainpll_freq = Chip_Clock_GetMainPLLHz();
if (mainpll_freq == 0) {
DEBUGOUT("Error in reading Main PLL frequency \r\n");
return 2;
}
DEBUGOUT("Main PLL Frequency in Hz : %d \r\n", mainpll_freq);
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("Clock Divider functions \r\n");
/*
* Divider E divider is used for SPIFI, source is set to
* Main PLL in SysInit code.
* Read Divider E source & verify it
*/
clk_in = Chip_Clock_GetDividerSource(CLK_IDIV_E);
if (clk_in != CLKIN_MAINPLL) {
DEBUGOUT("Divider E source wrong %d \r\n", clk_in);
return 3;
}
DEBUGOUT("Divider E source set to Main PLL \r\n");
/*
* Divider E divider is used for SPIFI, divider value should be
* between 3 and 5 set in SysInit code.
* Read Divider E divider value & verify it
*/
dive_value = Chip_Clock_GetDividerDivisor(CLK_IDIV_E);
if ( (dive_value < 3) && (dive_value > 5)) {
DEBUGOUT("Divider E divider wrong %d \r\n", dive_value);
return 4;
}
DEBUGOUT("Divider E divider value: %d \r\n", dive_value);
DEBUGOUT("=========================================== \r\n");
/*
* Read the frequencies of the input clock sources,
* print it on UART prompt
*/
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("Input clock frequencies \r\n");
DEBUGOUT("=========================================== \r\n");
for ( i = 0; i < (sizeof(clkin_info) / sizeof(CLKIN_NAME_T)); i++) {
clkin_frq = Chip_Clock_GetClockInputHz(clkin_info[i].clk_in);
DEBUGOUT(" %s Frequency : %d Hz \r\n", clkin_info[i].clkin_name, clkin_frq);
}
DEBUGOUT("=========================================== \r\n");
/*
* Read the base clock settings & print on UART
*/
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("Base Clock Setting Information \r\n");
DEBUGOUT("=========================================== \r\n");
for ( i = 0; i < (sizeof(baseclk_info) / sizeof(BASECLK_INFO_T)); i++) {
/* Read Base clock info, only if base clock is enabled */
bool_status = Chip_Clock_IsBaseClockEnabled(baseclk_info[i].clock);
if ( bool_status == true) {
Chip_Clock_GetBaseClockOpts(baseclk_info[i].clock, &base_input,
&autoblocken, &powerdn);
/* Read Frequency of the base clock */
baseclk_frq = Chip_Clock_GetBaseClocktHz(baseclk_info[i].clock);
/* Print details on UART */
DEBUGOUT("%s Input Clk: %d Base Clk Frq : %d Hz Auto block: %d Power down: %d \r\n",
baseclk_info[i].clock_name, base_input, baseclk_frq, autoblocken, powerdn);
}
}
DEBUGOUT("=========================================== \r\n");
/*
* Read the peripheral clock rate & print on UART
*/
DEBUGOUT("=========================================== \r\n");
DEBUGOUT("Peripheral Clock Rates \r\n");
DEBUGOUT("=========================================== \r\n");
for ( i = 0; i < (sizeof(ccu_clk_info) / sizeof(CCUCLK_INFO_T)); i++) {
/* Read Frequency of the peripheral clock */
perclk_frq = Chip_Clock_GetRate(ccu_clk_info[i].per_clk);
/* Print the per clock only if it is enabled */
if (perclk_frq) {
/* Print details on UART */
DEBUGOUT("%s Per Frq : %d Hz \r\n", ccu_clk_info[i].clock_name,
perclk_frq);
}
}
DEBUGOUT("=========================================== \r\n");
while (k) ;
return 0;
}
/* Update system core clock rate, should be called if the system has
a clock rate change */
void SystemCoreClockUpdate(void)
{
/* CPU core speed */
SystemCoreClock = Chip_Clock_GetRate(CLK_MX_MXCORE);
}
/* Configure I2S for Audio Format input */
Status Chip_I2S_Config(LPC_I2S_Type *I2Sx, uint8_t TRMode, Chip_I2S_Audio_Format_Type *audio_format)
{
uint32_t pClk;
uint32_t x, y;
uint64_t divider;
uint16_t dif;
uint16_t x_divide = 0, y_divide = 0;
uint32_t N;
uint16_t err, ErrorOptimal = 0xFFFF;
pClk = (uint64_t)Chip_Clock_GetRate(CLK_APB1_I2S);
/* divider is a fixed point number with 16 fractional bits */
divider = (((uint64_t)(audio_format->SampleRate) * 2 * (audio_format->WordWidth) * 2) << 16) / pClk;
/* find N that make x/y <= 1 -> divider <= 2^16 */
for (N = 64; N > 0; N--) {
if ((divider * N) < (1 << 16)) {
break;
}
}
if (N == 0) {
return ERROR;
}
divider *= N;
for (y = 255; y > 0; y--) {
x = y * divider;
if (x & (0xFF000000)) {
continue;
}
dif = x & 0xFFFF;
if (dif > 0x8000) {
err = 0x10000 - dif;
}
else {
err = dif;
}
if (err == 0) {
y_divide = y;
break;
}
else if (err < ErrorOptimal) {
ErrorOptimal = err;
y_divide = y;
}
}
x_divide = ((uint64_t)y_divide * (audio_format->SampleRate) * 2 * (audio_format->WordWidth) * N * 2) / pClk;
if (x_divide >= 256) {
x_divide = 0xFF;
}
if (x_divide == 0) {
x_divide = 1;
}
if (audio_format->WordWidth <= 8) {
IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_8);
}
else if (audio_format->WordWidth <= 16) {
IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_16);
}
else {
IP_I2S_SetWordWidth(I2Sx, TRMode, I2S_WORDWIDTH_32);
}
IP_I2S_SetMono(I2Sx, TRMode, (audio_format->ChannelNumber) == 1 ? I2S_MONO : I2S_STEREO);
IP_I2S_SetMasterSlaveMode(I2Sx, TRMode, I2S_MASTER_MODE);
IP_I2S_SetWS_Halfperiod(I2Sx, TRMode, audio_format->WordWidth - 1);
IP_I2S_ModeConfig(I2Sx, TRMode, I2S_TXMODE_CLKSEL(0), !I2S_TXMODE_4PIN_ENABLE, !I2S_TXMODE_MCENA);
IP_I2S_SetBitRate(I2Sx, TRMode, N - 1);
IP_I2S_SetXYDivider(I2Sx, TRMode, x_divide, y_divide);
return SUCCESS;
}
void adc_g_v_Init(void) {
clock_g_vInit();
// clock_g_vSetupAdchsClock(HSADC_CLOCK_RATE);
uint32_t fg_ui32FreqHSADC =0;
fg_ui32FreqHSADC = Chip_Clock_GetRate(CLK_MX_TIMER1);
//clock_g_vSetupAdchsClock(HSADC_CLOCK_RATE);
//Chip_USB0_Init(); /* Initialize the USB0 PLL to 480 MHz */
// Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_USBPLL, 2); /* Source DIV_A from USB0PLL, and set divider to 2 (Max div value supported is 4) [IN 480 MHz; OUT 240 MHz */
// Chip_Clock_SetDivider(CLK_IDIV_B, CLKIN_IDIVA, 3); /* Source DIV_B from DIV_A, [IN 240 MHz; OUT 80 MHz */
// Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVB, true, false); /* Source ADHCS base clock from DIV_B */
// Chip_Clock_SetDivider(CLK_IDIV_A, CLKIN_MAINPLL, 3); /* Setup divider A for main PLL rate divided by 3 */
// Chip_Clock_SetBaseClock(CLK_BASE_ADCHS, CLKIN_IDIVA, true, false); /* HSADC base clock = divider A input */
// Chip_Clock_EnableOpts(CLK_ADCHS, true, true, 1); /* Enable the clock */
/* Initialize HSADC */
Chip_HSADC_Init(LPC_ADCHS);
/* Setup FIFO trip points for interrupt/DMA to 16 samples, no packing */
Chip_HSADC_SetupFIFO(LPC_ADCHS, 8, false);
fg_ui32FreqHSADC = Chip_HSADC_GetBaseClockRate(LPC_ADCHS);
/* Software trigger only, 0x90 recovery clocks, add channel IF to FIFO entry */
Chip_HSADC_ConfigureTrigger(LPC_ADCHS, HSADC_CONFIG_TRIGGER_SW,
HSADC_CONFIG_TRIGGER_RISEEXT, HSADC_CONFIG_TRIGGER_NOEXTSYNC,
HSADC_CHANNEL_ID_EN_NONE, 0x90);
/* Select both positive and negative DC biasing for input 3 */
//Chip_HSADC_SetACDCBias(LPC_ADCHS, 3, HSADC_CHANNEL_DCBIAS, HSADC_CHANNEL_DCBIAS);
Chip_HSADC_SetACDCBias(LPC_ADCHS, 0, HSADC_CHANNEL_DCBIAS,
HSADC_CHANNEL_DCBIAS);
Chip_HSADC_SetACDCBias(LPC_ADCHS, 1, HSADC_CHANNEL_DCBIAS,
HSADC_CHANNEL_DCBIAS);
/* Setup data format for 2's complement and update clock settings. This function
should be called whenever a clock change is made to the HSADC */
Chip_HSADC_SetPowerSpeed(LPC_ADCHS, false);
/* Enable HSADC power */
Chip_HSADC_EnablePower(LPC_ADCHS);
/* Update Descriptor Table for use with channel 0 and 1 in loop*/
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 0, (HSADC_DESC_CH(0) |
HSADC_DESC_BRANCH_FIRST| /*HSADC_DESC_MATCH(1)*/ HSADC_DESC_MATCH(ADC_DEF_CLK_DIV) | HSADC_DESC_THRESH_NONE |
HSADC_DESC_RESET_TIMER));
Chip_HSADC_SetupDescEntry(LPC_ADCHS, 0, 1, (HSADC_DESC_CH(5) |
HSADC_DESC_BRANCH_FIRST| HSADC_DESC_HALT | HSADC_DESC_MATCH(1) | HSADC_DESC_THRESH_NONE|
HSADC_DESC_RESET_TIMER));
/* Update descriptor tables - needed after updating any descriptors */
Chip_HSADC_UpdateDescTable(LPC_ADCHS, 0);
Chip_HSADC_UpdateDescTable(LPC_ADCHS, 1);
}
